Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
  • H04L69/40—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass for recovering from a failure of a protocol instance or entity, e.g. service redundancy protocols, protocol state redundancy or protocol service redirection
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
  • H04L9/40—Network security protocols
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
  • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
  • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
  • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
  • H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC

Definitions

• the present invention relates to a method and to an appara- tus for transferring data on a bus to or from a device to be controlled by said bus, wherein bus blocking is to be avoided.
• the IEEE1394 bus is a low cost, high performance serial bus. It has a read/write memory architecture and a highly sophisticated communication protocol. Data rates of 100, 200 or 400Mbit/s can be transmitted in nearly real time. Simultaneously, data can be transmitted bi-directionally.
• the first ten bits of transmitted address values refer to one of up to 1023 possible IEEE1394 bus clusters.
• the following six bits of the transmitted address values refer within a specific cluster to one of up to 63 nodes to which an application or device is assigned. Data between nodes can be exchanged without interaction of a host controller. Devices can be connected to or disrupted from the network at any time, allowing a plug and play behaviour.
• the standardised cable connection for the nodes has a length of 4.5m and contains three twisted cable pairs of which two pairs serve for data and control information transmission and the further pair carries supply voltages of 8V to 40V.
• Three level coding is used: HIGH (H) , LOW (L) , and HIGH IMPEDANCE (Z).
• H overrides L, L overrides Z.
• the characteristic impedance is 110 ⁇ .
• IEEE1394- 1995 of the bus specification including only two twisted pairs of cables on which no power supply voltage is present.
• the communication protocol has three layers: physical layer, link layer, and transaction layer. Typically, the transaction layer is realised by firmware whereas the other layers are implemented using chip sets.
• the physical layer contains analog transceivers and a digital state machine. It handles bus auto-configuration and hot plug. It reclocks, regenerates and repeats all packets and forwards all packets to the local link layer. It carries out-packet framing, for example speed code, prefix, and packet end assembling. It arbitrates and transmits packets from the local link layer.
• Available IC types are e.g. TSB11C01, TSB11LV01, TSB21LV03, and TSB41LV03 of Texas In- struments, MB86611 of Fujitsu, and 21S750 of IBM.
• the link layer performs all digital logic. It recognises packets addressed to the node by address recognition and decodes the packet headers. It delivers packets to higher layers and generates packets from higher layers. It works ei- ther isochronous for AV data use or asynchronous for control data use.
• isochronous mode a channel having a guaranteed bandwidth is established. There is a defined latency. The transmission is performed in 125 ⁇ s time slots or cycles. Headers and data blocks of a packet have separate CRCs (cyclic redundancy check) . This mode has a higher priority than the asynchronous data transfer mode.
• the asynchronous mode is not time critical, but safe. It operates as an acknowledged service with a busy and retry pro- tocol. Fixed addresses are used. Transmission takes place when the bus is idle.
• the asynchronous mode handles read request/response, write request/response, and lock request/ response. It performs cycle control, CRC generation and validation.
• Available link layer IC types are e.g. TSB12C01A, TSB12LV21, TSB12LV31, and TSB12LV41 of Texas Instruments, and PDI1394L11 of Philips.
• the transaction layer implements asynchronous bus transactions :
• Read request/read response Write request/write response Lock request/lock response can be implemented by software running on a microcontroller, such as e.g. the i960 of SparcLite. There may also be an AV (audio video) layer carrying out de ⁇ vice control, connection management, timestamping, and pack- etising.
• AV audio video
• a link layer IC implements the interface to an external application, e.g. a VCR, and prepares IEEE1394 data for sending on the IEEE1394 bus, or interprets incoming IEEE1394 data packets from the IEEE1394 bus.
• a physical layer IC implements the direct electrical connection to the bus and controls many functions as mentioned above, including arbitration for sending data on the bus. The procedure for sending data from a link layer IC onto the bus is that the link layer IC requests access to the bus and then waits until the physical layer IC grants the desired access. Upon detecting the grant status, the link layer IC is free to send data onto the bus. But if in the meantime the link layer status has changed, i.e.
• the link layer IC refrains from sending data onto the bus, the granted bus access will not be given up according to the current IEEE1394 bus specification. As a consequence the bus is blocked for an indefinite time period because the bus access granted cannot be overwritten by the physical layer IC. A bus lock-up is very serious and means that the whole bus is jammed, no other node can get access to the bus to send data.
• an additional timer function is implemented in the link layer IC. This bus grant missed' timer function controls the link layer IC in such a way that it automatically gives back the bus control to the physical layer IC after a predetermined fixed time period has elapsed during which the link layer IC has sent no data onto the bus.
• the predetermined fixed time period can be user pro- grammable in order to adapt it to a given bus configuration or application, respectively.
• the inventive method is suited for transferring data on a bus to or from a device to be controlled by said bus, wherein for interfacing between the bus and said device a physical layer IC and a link layer IC are used and wherein said physical layer IC generates a grant signal in order to give to said link layer IC access to said bus for sending data onto said bus and until said link layer IC has finished sending said data onto said bus following said grant signal, said bus remains occupied by said link layer IC, wherein said link layer IC includes a timer function which in case said physical layer IC grants to said link layer IC access for sending data onto said bus but said link layer IC does not send data onto said bus, generates a link release signal in order to release the link layer IC bus occupation after a predetermined time period following said grant signal has elapsed.
• the inventive bus interface is suited for transferring data to or from a device to be controlled by the bus, and includes:
• said physical layer IC generates a grant signal in order to give to said link layer IC access to said bus for sending data onto said bus and wherein, until said link layer IC has finished sending said data onto said bus following said grant signal, said link layer IC keeps said bus occupied;
• Fig. 1 IEEE1394 double-node for bi-directional real-time video applications
• Fig. 2 an IEEE1394 bus-connected set-top box, VCR and DVD player
• Fig. 3 a blocked bus
• Fig. 4 a bus in which blocking is prevented.
• a first physical layer IC PLI1 is connected via an IEEE1394 bus cable connection to a second physical layer IC PLI2 which itself is also connected to the further IEEE1394 bus cable B.
• PLIl is at the other side assigned to a first link layer IC LLIl for data input
• PLI2 is assigned to a second link layer IC LLI2 for data output.
• LLIl and LLI2 are both assigned to the same application device APP .
• LLIl and PLIl via LLIl are controlled by a first microcontroller ⁇ Pl .
• LLI2 and PLI2 via LLI2 are controlled by a second microcontroller ⁇ P2.
• Application device APP can be controlled by ⁇ Pl and ⁇ P2, or by one of them. In both cases ⁇ Pl and ⁇ P2 may interact with each other (not depicted) .
• a set-top box STB with receiving unit RU, MPEG decoder MDEC and IEEE1394 interface 1394S receives a digital TV program via satellite or cable.
• the receiving unit output signal is transmitted via IEEE1394 bus for the purpose of recording to a video recorder VCRR including also a IEEE1394 interface 1394V.
• a DVD player DVDP replays a DVD disc and the DVD data is also transported via an IEEE1394 bus interface 1394D to the IEEE1394 bus in- terface 1394S of the set-top box in order to be decoded by the MPEG decoder MDEC and to be displayed on the screen of a television receiver TV.
• TV may still have an analog signal connection to the set-top box, but may also be connected to STB by an IEEE1394 bus interface. So, the set-top box IEEE1394 bus node 1394S needs a bi-directional functionality.
• FIG. 3 the clock CLK, the status of the physical layer PHST, the status LIST of a link layer IC and the bus control BCTL time periods of the physical layer and of the link layer IC are depicted.
• a physical layer IC grants bus access to a link layer IC by sending a PHYGRT bit or impulse. Thereafter bus control for sending data is assigned to that link layer IC. After sending data onto the bus the link layer IC would signal to the physical layer IC that it needs no longer bus access whereupon the physical layer could give access to another device demanding bus access. However, as long as the link layer IC does not send data onto the bus, for example because a user has switched off that device in the meantime, the bus will be blocked for the physical layer IC and for all other devices connected to the bus.
• a link release bit or impulse LIRL is added to the link layer IC which sends a link release bit or impulse LIRL after a predetermined time period, beginning basically with PHYGRT, has elapsed.
• LIRL is sent in correlation with e.g. slope TLR of clock CLK, as depicted in Fig. 4.
• the bus control BCTL is given back to the physical layer.
• the other details of Fig. 4 correspond to that of Fig. 3.
• the corresponding timer TIM is shown in the block diagram of Fig. 1.
• the invention can also be used to achieve spike protection. It can happen that the physical layer IC grants unintended bus access to the link layer IC because of spike signals on control signals of the physical layer/link layer IC connection. Also in such cases the above described timer function on the link layer IC ensures that, even though the link layer IC didn't request bus access, the bus is released again by the link layer IC after a predetermined time period has elapsed. That time period may differ from the above described time period, according to the current application or bus environment. The length of the time period is then controlled by the presence or absence of a prior bus request from the link layer IC.

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• Engineering & Computer Science (AREA)
• Computer Security & Cryptography (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Small-Scale Networks (AREA)
• Information Transfer Systems (AREA)

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• 1999
  • 1999-03-03 EP EP99250060A patent/EP1033855A1/en not_active Withdrawn
• 2000
  • 2000-02-21 JP JP2000603214A patent/JP4398592B2/ja not_active Expired - Fee Related
  • 2000-02-21 WO PCT/EP2000/001413 patent/WO2000052899A1/en not_active Ceased
  • 2000-02-21 EP EP00909226A patent/EP1157516B1/en not_active Expired - Lifetime
  • 2000-02-21 DE DE60021355T patent/DE60021355T2/de not_active Expired - Lifetime
  • 2000-02-21 AU AU31581/00A patent/AU3158100A/en not_active Abandoned
  • 2000-02-21 CN CN00804394.9A patent/CN1130058C/zh not_active Expired - Fee Related
  • 2000-02-21 US US09/913,683 patent/US6643723B1/en not_active Expired - Lifetime

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