WO2000045508A1 - Amplificateurs hyperfrequence - Google Patents

Amplificateurs hyperfrequence Download PDF

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Publication number
WO2000045508A1
WO2000045508A1 PCT/GB2000/000225 GB0000225W WO0045508A1 WO 2000045508 A1 WO2000045508 A1 WO 2000045508A1 GB 0000225 W GB0000225 W GB 0000225W WO 0045508 A1 WO0045508 A1 WO 0045508A1
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WO
WIPO (PCT)
Prior art keywords
amplifier
transistor
output
amplifiers
stage
Prior art date
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PCT/GB2000/000225
Other languages
English (en)
Inventor
Andrew Robert Barnes
Mark Terence Moore
Michael Barry Allenson
Robert Gordon Davis
Original Assignee
Qinetiq Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qinetiq Limited filed Critical Qinetiq Limited
Priority to EP00901224A priority Critical patent/EP1151533A1/fr
Priority to JP2000596662A priority patent/JP2002536861A/ja
Priority to AU21184/00A priority patent/AU2118400A/en
Publication of WO2000045508A1 publication Critical patent/WO2000045508A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
    • H03F3/602—Combinations of several amplifiers
    • H03F3/604—Combinations of several amplifiers using FET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers

Definitions

  • the present invention relates to microwave amplifiers and particularly to such amplifiers which are solid state and which provide high power output over a broad band of frequencies.
  • microwave amplifiers having a high power output over a broad band of frequencies are used.
  • high power output is meant in the region of 4 to 25W and by a broad band of frequencies about or at least a frequency bandwidth of 200%.
  • Such applications include general purpose instrumentation, electromagnetic compatibility testing, and radar applications.
  • TWTAs travelling wave tube amplifiers
  • TWTAs travelling wave tube amplifiers
  • these have a number of disadvantages. They are expensive to manufacture, and are bulky and heavy. They are often unreliable, in some situations they can require replacement at a rate of one per day. They also need to be warmed up prior to use, so are usually kept in a stand-by mode which requires electrical power to be supplied to them even when not in actual use.
  • Solid state microwave amplifiers overcome many of these problems. They have small size and weight, low voltage operation, high intrinsic reliability, excellent repeatability and negligible warm-up time.
  • the highest reported output power signal from a commercially available 6 to 18 GHz solid state monolithic microwave integrated circuit (MMIC) amplifier is 1.8W.
  • a solid state amplifier having a higher output power signal is disclosed in 'A 6 to 18 GHz broadband high power MMIC for EW applications' A R Barnes, M T Moore M B Allenson, IEEE MTT-S Digest, 1997. However, even this amplifier does not have a sufficiently high output power over the broad band frequency range for the above applications.
  • a solid state microwave power amplifier module comprising at least two solid state microwave power amplifiers each having at least one channel comprising at least one transistor, each amplifier having an output power signal of at least 5W and being capable of amplifying signals having a frequency bandwidth of about or at least 200%, the output power signal of the amplifier module being the combined output power signals of the amplifiers.
  • the frequency bandwidth of the amplifier module is preferably at least 200%.
  • the amplifier module amplifies signals having frequencies of at least 6 to 18 GHz, but could amplify signals having frequencies of at least 5 to 17 GHz or at least 7 to 19 GHz.
  • Each amplifier may comprise two or more channels.
  • the channels are preferably provided on the same semiconductor chip.
  • the amplifier module comprises at least two (preferably two) amplifiers, each of which comprises at least two (preferably two) channels.
  • Each channel has an output power signal of at least 2.5W. These are combined to give an output power signal for each amplifier of at least 5W, which in turn are combined to give an amplifier module output power signal of at least 10W.
  • the amplifier module preferably comprises one or more power dividers. These may be used to divide power signals received by the module, and/or power signals generated within the module.
  • the input power signal received by the amplifier module is preferably divided and fed to each of the amplifiers.
  • the amplifiers comprise two or more channels
  • the input power signal received by each of the amplifiers may be divided and fed into each of the channels.
  • the input power signal received by the amplifier module may be divided and fed into each of the channels.
  • the channels comprise more than one transistor
  • the input power signal received by each channel may be divided and fed into each of the transistors.
  • the output power signal of one or more of the transistors may be divided and fed to further transistors .
  • the or a or each divider may be a symmetric divider. These have a number of advantages. They are easier to realise over a broad band of frequencies than non-symmetric dividers. The possibility of overdriving any transistors to which the dividers are connected is reduced. Any variations introduced during processing of the divider affect each part of the divider in a similar manner.
  • the or a or each divider may be a corporate power divider.
  • the or a or each divider may be a serial power divider.
  • a combination of corporate and serial dividers may be used.
  • Serial dividers can be manufactured in a narrow strip and therefore take up less space. However, they are difficult to realise over a broad band of frequencies, more so than corporate dividers, which are the preferred type of divider.
  • the or a or each divider, whether corporate or serial, may comprise a number of building blocks.
  • the most important requirements for the building blocks are broadband operation (preferably over a bandwidth of at least 200%), low insertion loss (preferably less than 0.5 dB per section of divider) , equal power division over the operating band, good port return loss (preferably greater than 15dB), small size (preferably of a size comparable to the size of the amplifier chip of the module, or two or three times this size), compatibility with monolithic microwave integrated circuit (MMIC) integration and ease of manufacture.
  • the building blocks are preferably combined in a planar topology and use printed circuit techniques.
  • the building blocks may act to divide power signals in phase, or may act to divide power signals in phase quadrature.
  • Each have different advantages and disadvantages.
  • realisable quadrature power dividers have to be overcoupled resulting in unequal power division.
  • an advantage of the quadrature approach is that it does permit balanced amplifier topologies to be used, thereby allowing good input and output return loss to be easily achieved.
  • phase dividers are good for use in a broadband amplifier module since they are inherently symmetric and give equal power division at all frequencies.
  • phase delay is preferably introduced between the signals to be divided. This helps to cancel out mismatch reflections between, for example, the amplifiers of the module and the circuitry of the or each divider. It is preferable to stagger the insertion phase between divider outputs such that any reflections appear out of phase and can be dissipated across, for example, isolation resistors. Preferably, such phase delays are introduced over a number of frequencies of the signals being divided, and preferably over a substantial proportion of the frequency bandwidth of the amplifier module.
  • the amplifier module may further comprise one or more power combiners. These may be used to combine power signals generated within the module. For example, the output power signals of the amplifiers may be so combined. When the amplifiers comprise more than one channel the output power signals of these may be combined. When the channels comprise more than one transistor, the output power signals of these may be combined.
  • the or a or each combiner may be a symmetric combiner. The or each combiner may be a corporate power combiner. The or a or each combiner may be a serial power combiner. When the amplifier module comprises more than one combiner, a combination of corporate and serial combiners may be used. The advantages/disadvantages of each type of combiner are similar to those for these types of dividers. Corporate combiners are preferably used.
  • the or a or each combiner may comprise a number of building blocks.
  • the most important requirements for the power combiner building blocks are similar to those above for the power divider building blocks.
  • the key requirement for the combiner building blocks is that they minimise any loss of signal combined by them.
  • the building blocks may also act to combine power signals in phase (e.g. Wilkinson combiners or N-way planar combiners) or may act to combine power signals in phase quadrature (e.g. branch arm couplers, or Lange couplers, or parallel coupled striplines) .
  • the combiner may be integrated with the chip or external to the chip.
  • one or more Wilkinson combiners are preferably used to combine the output power signals of the channels.
  • These combiners preferably incorporate thin film microstrip on 0.015" alumina. This gives a good compromise between achieving operation over the required frequency band, excellent power combiner amplitude balance (preferably at least ⁇ 0.25dB) , low insertion loss and ease of manufacture and low cost.
  • the or each combiner is provided external to the chip on which the channels are provided.
  • phase delay is preferably introduced between the output signals to be combined. This helps to cancel out mismatch reflections between the amplifiers of the module and the circuitry of the or each combiner. It is preferable to stagger the insertion phase between combiner inputs such that any reflections appear out of phase and can be dissipated across, for example, isolation resistors.
  • phase delays are introduced over a number of frequencies of the signals being combined, and preferably over a substantial proportion of the frequency bandwidth of the amplifier module.
  • equal and opposite phase delays are introduced into dividers used to divide the signal input to the amplifier module, and combiners used to combine the signals from the amplifiers.
  • the amplifiers preferably have good input and output return loss i.e. at least 15dB. If the amplifiers have poor input and output return loss this is also seen at the input and output of the amplifier module and can lead to unwanted gain ripple over multi-octave bandwidths.
  • the amplifiers Prior to assembly, the amplifiers are preferably RF on wafer (RFOW) measured and pre-selected to ensure optimum gain and insertion phase tracking, important for efficient power signal combination.
  • RFOW RF on wafer
  • the amplifiers are preferably soldered onto Silvar carriers, e.g. 1mm thick, preferably using a AuSn paste. It is important to achieve die attach uniformity in a power module assembly, any variations in thermal resistance result in amplifier channels operating at different temperatures producing gain and output power imbalance.
  • a scanning infra-red microscope was used to make thermal measurements on the carriers under nominal operating bias conditions. This showed that solder voids were present, particularly near concentrations of via-holes on the circuit. This problem was overcome by pre-tinning the Silvar carrier with solder.
  • the pre-tinned carrier has a much more uniform temperature distribution and is typically 20 to 30 degrees cooler. This results in improved gain and output power and also better component reliability.
  • the amplifiers are preferably replaceable, and test measurements may be performed on them in isolation.
  • the amplifiers are preferably interfaced with 1.5mm long 50ohm lines for such testing. These lines are preferably microstrip transmission lines.
  • a DC bias voltage is applied symmetrically to each amplifier. This minimises voltage imbalance and maximises output power capability.
  • the amplifiers may be monolithic microwave integrated circuit (MMIC) amplifiers and are manufactured using known GaAs manufacturing techniques. This is particularly suitable for such amplifiers as it offers reduced and tightly controlled parasitic elements, and largely eliminates wire bond interconnects. These benefits enable broad operating bandwidths to be achieved at low cost, whilst good chip to chip repeatability and 50ohm impedance allows power combination to be implemented more readily.
  • MMIC monolithic microwave integrated circuit
  • the amplifiers may each be connected to an input circuit by an input network, and to an output circuit by an output network.
  • the input and/or output networks may be transmission line networks.
  • Impedance matching components are preferably provided in the input and/or output networks. These components may be capacitive, inductive or resistive components or a combination thereof. Lossy matching techniques may be used.
  • the or each channel of the amplifiers is preferably connected to an input circuit by an input network, and to an output circuit by an output network.
  • the input and/or output networks are preferably transmission line networks.
  • Impedance matching components are preferably provided in the input network, to match the impedance of the input circuit to that of the or the first transistor of the channel.
  • Impedance matching components are preferably provided in the output network, to match the impedance of the or the last transistor of the channel to that of the output circuit.
  • the matching components may be capacitive, inductive or resistive components or a combination thereof. Lossy matching techniques may be used.
  • the or each channel of the amplifiers may comprise three stages of amplification.
  • the first stage may use a distributed amplifier or feedback topology. This is used to achieve a good input signal match over the bandwidth and to provide positive gain slope compensation.
  • the second stage may consist of two 1200 ⁇ m gate width transistors.
  • the third stage may consist of four 1200 ⁇ m gate width transistors.
  • the output power signal or signals of the first stage are preferably fed into the second stage, and the output power signal or signals of the second stage are preferably fed into the third stage.
  • the stages are preferably interconnected using transmission line networks.
  • Impedance matching components e.g. capacitive, inductive, or resistive components, or a combination thereof are preferably provided in the networks between stages. These provide gain slope compensation and the optimum impedance level for impedance matching.
  • the output network preferably presents the optimum impedance to the final amplification stage (e.g. four 1200 ⁇ m transistors) over the range of frequencies used.
  • the matching network topology is selected to offer a good compromise between impedance matching and insertion loss. Lossy matching techniques may be used.
  • the amplifier is provided with one or more test structures. This allows, for example, the distributed amplifier and/or output amplifier stages to be measured in isolation for diagnostic purposes.
  • the capability of solid state microwave power amplifiers critically depends on the performance of the transistors therein.
  • the transistors are preferably pseudomorphic high electron mobility transistors (PHEMT), but could be FET or HBT transistors.
  • the transistors are preferably manufactured from GaAs.
  • the MMIC process used is preferably a 0.25 ⁇ m power PHEMT process.
  • the process preferably has an f, of at least 32GHz, and provides transistors with a typical gate drain breakdown of 16 to 18N and an output power density of approximately 0.7W/mm.
  • a metal bus-bar typically about 2mm thick, is used to interconnect the or each transistor drain bias pads. This minimises resistive voltage drops in the drain bias line.
  • the bus-bar is provided in the module, but preferably not on the amplifier chips.
  • an external bias regulation board is used to provide the gate and drain bias voltages of the or each transistor, and to allow pulsed bias operation if required.
  • a resistor is connected between the gate bias lines of each transistor, and between the drain bias lines of each transistor. This helps to prevent the occurrence of odd mode oscillations.
  • the amplifier module may be interfaced with Wiltron 'K' connectors and mounted onto a heat sink with forced air-cooling, for power measurements.
  • the amplifier module size may be 40mm x 53mm x 16mm, but is preferably smaller.
  • a solid state microwave power amplifier having at least one channel comprising at least one transistor, the amplifier having an output power signal of about or at least 8W and being capable of amplifying signals having a frequency bandwidth of at least 200%.
  • the amplifier is capable of amplifying signals having frequencies of at least 6 to 18GHz, but could amplify signals having frequencies of at least 5 to 17 GHz or at least 7 to 19 GHz.
  • the gain of the amplifier is preferably in the region of 20dB, or at least 20dB.
  • the amplifier preferably comprises more than one channel.
  • the channels are preferably manufactured on the same chip. Providing the channels on the same chip improves channel tracking and improves any subsequent power combination. Differences in the operation of the channels due to differences in characteristics of the chip material which can occur if different chips are used, are reduced.
  • the amplifier comprises two channels. Each of these produces an output power signal of about or at least 4W, and these are combined to give an amplifier output power signal of about or at least 8W.
  • a Wilkinson combiner is used to combine the output signals of the channels.
  • This is preferably mounted on an insulator which may be alumina, particularly 0.015" thick alumina.
  • the output signals of the channels are preferably combined using a combiner which is external to the chip on which the channels are provided. This reduces the cost of manufacture of the chip.
  • the or each channel is preferably connected to an input circuit by an input network, and to an output circuit by an output network.
  • the input and/or output networks are preferably transmission line networks.
  • Impedance matching components are preferably provided in the input network, to match the impedance of the input circuit to that of the or the first transistor of the channel.
  • Impedance matching components are preferably provided in the output network, to match the impedance of the or the last transistor of the channel to that of the output circuit.
  • the matching components may be capacitive, inductive or resistive components or a combination thereof.
  • the or each channel may comprise three, or preferably less than three, stages of amplification.
  • the first stage may comprise a transistor of about or at least 0.75mm gate width.
  • the second stage may comprise a single transistor, of about or at least 3mm gate width.
  • the third stage may comprise a single transistor of about 7.68mm gate width (or about or at least 7 or 8 mm gate width) . This is to be compared with the multiple transistors used in these stages in the amplifier of the prior art. Using a signal transistor covering approximately the same area as the multiple transistors in the prior art, results in an increased transistor size and therefore amplification capability.
  • a bias voltage is preferably applied to the transistor of the third stage at two or more points. This helps to balance the bias voltage on this transistor.
  • the output power signal or signals of the first stage is preferably split and fed into the second stage at four points (or at least four points, or less than four points) along the transistor of this stage, and the output power signal or signals of the second stage is preferably split and fed into the third stage at eight points (or at least eight points, or less than eight points) along the transistor of this stage.
  • the stages are preferably interconnected using transmission line networks.
  • micro strip transmission line networks are preferably micro strip transmission line networks.
  • Impedance matching components are preferably provided in the network between the first stage and the second stage, to match the impedance of the first stage to that of the second stage.
  • Impedance matching components are preferably provided in the network between the second stage and the third stage, to match the impedance of the second stage to that of the third stage. Such impedance matching ensures the proper operation of the amplifier.
  • the matching components may be capacitive, inductive or resistive components or a combination thereof.
  • the sizes of the transistors in this amplifier have been increased. As the size of a transistor increases the impedance thereof decreases.
  • the input and output circuits used with the amplifier of the prior art have an impedance of approximately 50ohm. If these are used with the amplifier of the invention, as the transistors in this amplifier have smaller impedances, the impedance matching of the transistors is more difficult, especially over a broad range of frequencies. The topology of the impedance matching components of the amplifier of the invention has therefore been carefully designed.
  • the or each transistor is preferably a pseudomorphic high electron mobility transistor (PHEMT).
  • PHEMT pseudomorphic high electron mobility transistor
  • the or each transistor is preferably manufactured from GaAs.
  • Gallium nitride or silicon carbide can also be used. Whilst silicon might be used it is unlikely to give the performance wanted in the preferred embodiment; silicon may be more useful for amplification of signals having low frequencies.
  • the or each transistor preferably comprises a number of fingers.
  • the length of the fingers is preferably in the region of 0.25 ⁇ m.
  • the width of the fingers is preferably in the region of 80 ⁇ m, or less than 80 ⁇ m. The width chosen will depend on the impedance matching required and the required output power. If the fingers are too short the power output signal of the transistor can be decreased, if they are too long this can cause phasing problems. For operation of the amplifier at frequencies of about 18GHz, the width of the transistor fingers should not be much greater than 80 ⁇ m otherwise phasing problems will occur.
  • the spacing between the gate fingers is preferably in the region of 30 ⁇ m ⁇ O.l ⁇ m. This provides a good compromise between packing density of the fingers and the thermal considerations.
  • the number of fingers used in the or each transistor depends on the power output signal required from that transistor. Increasing the number of fingers used increases the current the transistor can handle and therefore the power amplification the transistor can achieve. The number of fingers also depends on the width and spacing chosen for the transistors and the width chosen for the transistor.
  • the number of fingers in the transistor of the first stage is preferably about 8
  • the number of fingers in the transistor of the second stage is preferably about 48
  • the number of fingers in the transistor of the third stage is preferably about 96.
  • the or each transistor is capable of carrying approximately 2.5 A of current (at least) .
  • the input power signal received by the or each transistor is preferably input through a resistor and capacitor in parallel. This helps to stabilise the gain slope of the transistor.
  • the impedance of the output power signal of the or each transistor generally has an unwanted capacitive component.
  • Each output power signal is preferably fed into one or more inductive elements, which help to cancel the capacitive component.
  • the gate bias lines of the transistors are strapped together by damping resistors so that they have equal potentials.
  • the drain bias lines are also strapped together. This helps to prevent ring mode or odd-mode oscillations in the amplifier which are undesirable.
  • damping elements are provided on the gate and/or drain bias lines for the or each transistor. These may be RC networks. These help prevent parametric oscillations in the amplifier which are undesirable. Additional RC damping elements are preferably provided on the drain bias lines of the or each transistor of the second and third stages of amplification.
  • an external bias regulation board is used to provide the gate and drain bias voltages of the or each transistor. This preferably allows pulsed bias operation if required.
  • the amplifier is preferably a monolithic microwave integrated circuit (MMIC) amplifier and may be manufactured using known GaAs manufacturing techniques. This is particularly suitable as it offers reduced and tightly controlled parasitic elements, and largely eliminates wire bond interconnects. These benefits enable broad operating bandwidths to be achieved at low cost, whilst good chip to chip repeatability and 50ohm impedance allows power combination to be implemented more readily.
  • MMIC monolithic microwave integrated circuit
  • the amplifier is provided with one or more test structures. These are preferably adapted to enable the operation of parts of the amplifier circuit to be tested. This allows, for example, the distributed amplifier and output amplifier stages to be measured in isolation for diagnostic purposes.
  • the amplifier as described has low noise, from 6 to 18 GHz this is below 7dB.
  • Each channel of the amplifier may have dimensions of 6.731 mm by 3.124 mm.
  • the channel area is preferably less than 20mm 2 and preferably approximately 19mm 2 . This area ensures good commercial viability of amplifiers comprising such a channel or channels.
  • Solid state amplifiers comprising such channels are much smaller and lighter than TWTAs or other available solid state amplifiers. Their weight is preferably less than 500g, compared with perhaps 5kg for a TWTA.
  • a solid state microwave power amplifier module comprising at least two amplifiers according to the second aspect of the invention, the power output signal of the amplifier module being the combined power output signals of the amplifiers.
  • the module comprises four (or at least four) of the amplifiers and their power output signals are combined to provide an amplifier module power output signal of approximately 25 W or at least 25W.
  • the amplifiers are preferably pre-selected before combination to form an amplifier module, to give good phase and amplitude tracking.
  • a solid state phased array system comprising two or more of the amplifier modules of the first aspect of the invention.
  • a solid state phased array system comprising two or more of the amplifiers of the second aspect of the invention.
  • a solid state phased array system comprising two or more of the amplifier modules of the third aspect of the invention.
  • a phased array system comprises a number of power amplification elements in phase.
  • increasing the number of elements also increases the cost of the system.
  • the larger the power output signal of each array element (or the better the sensitivity) the smaller the number of elements required.
  • Using solid state amplifiers or amplifier modules having large power output capabilities in the array elements decreases the number of elements required. This may allow linear arrays to be used which are cheaper than 2D arrays.
  • a broadband radar system comprising a phased array system according to the fourth aspect, the fifth aspect or the sixth aspect of the invention.
  • an electromagnetic emitter apparatus comprising a phased array system according to the fourth aspect, or the fifth aspect or the sixth aspect of the invention.
  • Such an apparatus may be used in a jammer system, for jamming electromagnetic waves.
  • Previously such systems have relied on TWTAs, but these can be unreliable and need to be kept in a 'stand-by' mode.
  • Moving to solid state phased arrays can increase the reliability of the jammer systems and no stand-by mode is necessary. Hitherto it has been conventionally thought impossible to get enough power through a solid state amplifier to make these worth considering for this application.
  • an electromagnetic receiver system comprising one or more amplifier modules or amplifiers according to the first aspect, the second aspect or the third aspect of the invention.
  • the amplifiers and amplifiers modules are particularly suited for use in such receivers as they have a high output power signal over a large frequency range and have low noise. They are particularly suited for use at the 'front end' of such receivers. They can have a large dynamic range without saturating, because of their high power output capabilities.
  • an electromagnetic emitter system comprising one or more amplifier modules or amplifiers according to the first aspect, the second aspect or the third aspect of the invention.
  • Such an emitter system could be used for broadband communications such as radar communications.
  • a broadband transmitter apparatus for use in conformal array radar systems, comprising one or more amplifiers according to the second aspect of the invention.
  • emitter and receiver systems may be used in combination as transceiver systems. This may enable less components to be used.
  • Figure 1 is a photograph of a prior art amplifier
  • Figure 2 is a schematic representation of the components of one channel of the amplifier of Figure 1 ;
  • Figure 3 is a top view of the amplifier module of the first aspect of the invention.
  • Figure 4 is a view of a combiner used with the amplifier module of Figure 3;
  • Figure 5 is a graph of the measured output power signal of the amplifier module of Figure 3.
  • Figure 6 is a to-scale physical layout of one channel of the amplifier of the second aspect of the invention
  • Figure 7 is a schematic representation of the components of the channel of Figure 6.
  • Figure 1 shows a prior art amplifier.
  • This type of amplifier is used in the amplifier module of Figure 3.
  • the amplifier comprises a first 1 and a second 2 channel, each having the same components.
  • the channels are provided on the same semiconductor chip, as mirror images. This allows access for gate and drain bias lines to each channel.
  • Each channel comprises three stages of amplification. The stages are interconnected by transmission line networks. Each stage comprises one or more transistors. All of these are PHEMT transistors manufactured from GaAs.
  • the amplifier as a whole is manufactured using known GaAs manufacturing techniques.
  • the first stage of amplification comprises a transistor 3, which has a gate bias line 4 and a drain bias line 5 thereto.
  • the drain bias line is provided with damping elements 6, to help prevent parametric oscillations.
  • the output power signal from the transistor 3 is fed to the second stage of amplification along transmission line 8. This is provided with impedance matching components 9, used to match the impedance of the transistor 3 with that of the second stage.
  • the output power signal of the transistor 3 is fed along transmission line 8 to a divider 10, where it is divided into two signals which are fed to the second stage.
  • the second stage of amplification comprises a first transistor 15 and a second transistor 16. Each of these has a gate width of 1200 ⁇ m.
  • the first transistor has a gate bias line 17 and a drain bias line 18 thereto, and the second transistor has a gate bias line 19 and a drain bias line 20 thereto.
  • the drain bias line 18 is provided with damping elements 21, and the drain bias line 20 is provided with damping elements 22.
  • the output power signal of transistor 15 is fed along transmission line 23 to a divider 24.
  • the transmission line 23 is provided with an impedance matching component 25.
  • the output power signal is divided into two and fed along transmission lines 26,27 to the third stage of amplification.
  • the transmission lines 26,27 are provided with impedance matching components 28.
  • the various matching components are used to match the impedance of the transistor 15 with that of the third stage.
  • the output power signal of the second transistor 16 is fed along transmission line 29 to a divider 30.
  • the transmission line 29 is provided with an impedance matching component 31.
  • the output power signal is divided into two and fed along transmission lines 32,33 to the third stage of amplification.
  • the transmission lines 32,33 are provided with impedance matching components 34.
  • the various matching components are used to match the impedance of the transistor 16 with that of the third stage.
  • the third stage of amplification comprises a first transistor 40, a second transistor 41, a third transistor 42 and a fourth transistor 43. Each of these has a gate width of 1200 ⁇ m.
  • the first transistor 40 has a gate bias line 45 and a drain bias line 46 thereto.
  • the drain bias line is provided with damping elements 47.
  • the second transistor 41 has a gate bias line 48 and a drain bias line 49 thereto.
  • the drain bias line is provided with damping elements 50.
  • the third transistor 42 has a gate bias line 51 and a drain line bias 52 thereto.
  • the drain bias line is provided with damping elements 53.
  • the fourth transistor 43 has a gate bias line 54 and a drain bias line 55 thereto.
  • the drain bias line is provided with damping elements 56.
  • the output power signal of the first transistor 40 is fed along transmission line 57 to combiner 58.
  • the output power signal of the second transistor 41 is fed along transmission line 59 to the combiner 58.
  • the two signals are combined and fed along transmission line 60 to combiner 61.
  • the transmission line 60 is provided with impedance matching components 62, to match the impedance of the combined output power signals of transistors 40, 41 with that of the circuit to which the output of the channel is connected for use (not shown) .
  • the impedance of this circuit is approximately 50ohm.
  • the output power signal of the fourth transistor 43 is fed along transmission line 65 to the combiner 64.
  • the two signals are combined and fed along transmission line 66 to the combiner 61.
  • the transmission line 66 is provided with impedance matching components 67 to match the impedance of the combined output power signals of transistors 42, 43 with that of the circuit to which the output of the channel is connected for use (not shown) .
  • the impedance of the circuit is approximately 50ohm.
  • the second channel 2 has the same components and operates in the same manner to the first channel.
  • the channels have mirror symmetry. In use, the output signals from the two channels may be combined producing a single output signal from the amplifier.
  • Figure 2 shows a schematic representation of the components of the channels 1,2 of Figure 1. This shows the input power signal etc. being divided, matched, amplified, combined and output.
  • FIG 3 is a top view of the amplifier module of the first aspect of the invention.
  • This has dimensions of 40mm x 53mm x 16mm.
  • This comprises a first amplifier 80 and a second amplifier 81.
  • Each of these is an amplifier of the type described above.
  • the amplifiers are soldered onto 1mm thick Silvar carriers using a AuSn paste.
  • the carriers are pre- tinned with solder.
  • Each of the amplifiers comprises two channels. Each channel has an output power signal of at least 2.5W. These are combined to give an output power signal for each amplifier of at least 5W, which in turn are combined to give an amplifier module output power signal of at least 10 W.
  • the microwave power signal to be amplified is fed into an input circuit 82 of the module. It is fed along transmission line 83 to divider 84. Here it is divided into a first signal fed along transmission line 85 to divider 86, and a second signal fed along transmission line 87 to divider 88. The first signal is divided again at divider 86 and fed along transmission lines 89,90 into the first amplifier 80. The second signal is also divided again at divider 88 and fed along transmission lines 91,92 into the second amplifier 81.
  • the output signals of the amplifiers are fed to an output circuit 103 of the amplifier module.
  • the output power signals of amplifier 80 are fed along transmission lines 93,94 to a combiner 95.
  • the output power signals of amplifier 81 are fed along transmission lines 96,97 to a combiner 98.
  • the signals from amplifier 80 are combined and fed along transmission line 99 to combiner 100.
  • the signals from amplifier 81 are combined and fed along transmission line 101 to combiner 100.
  • the combined signals are combined again to produce a single output power signal and fed along transmission line 102 to the output of the amplifier module.
  • the input and output circuits 82,103 of the amplifier module are provided with a first phase delay 105, a second phase delay 106 and a third phase delay 107.
  • a first phase delay 105 is produced by making the transmission line along which the first signal travels longer than the transmission line along which the second signal travels.
  • phase delays help to prevent oscillations being set up in the amplifier module, and minimise mis-match reflections between building blocks of the combiners and dividers.
  • Figure 5 is a graph of the measured output power signal of the amplifier module of Figure 3.
  • the output signal was measured for 2dB of gain compression under pulsed bias conditions. Over the 6 to 14 GHz frequency range greater than 10W (40dBm) of output power is obtained, and from 6 to 17.5 GHz the output is greater than or equal to 7.9W (39 dBm).
  • Figure 6 shows a to-scale physical layout of one channel of the amplifier of the second aspect of the invention. This has dimensions of 6.731mm x 3.124mm.
  • the channel comprises three stages of amplification. The stages are interconnected by transmission line networks. Each stage comprises one or more transistors. All of these are PHEMT transistors manufactured from GaAs.
  • the amplifier as a whole is manufactured using known GaAs manufacturing techniques.
  • impedance matching components are used throughout the amplifier. These comprise capacitive, inductive or resistive components, or a combination thereof. They are referenced in Figure 6 as follows:
  • the stub capacitor is an open circuit transmission line which acts as a capacitor. These are very effective, but are rather bulky and are therefore not used after the first stage of amplification due to lack of space.
  • the transmission lines provide the inductive components.
  • the first stage comprises a transistor 120 which has a gate width of 0.75mm and comprises 8 fingers each having a width of 93.75 ⁇ m.
  • This has a gate bias line 121 and a drain bias line 122 thereto.
  • the gate and drain bias lines are provided with damping elements 123, to help prevent parametric oscillations.
  • the input power signal to the amplifier is fed to the input 124 of the channel and from there along transmission line 125 to the transistor 120.
  • the transmission line 125 is provided with impedance matching components 126, used to match the impedance of the circuit (not shown) to which the input of the channel is connected for use with that of the transistor 120.
  • the impedance of this circuit is approximately 50 ohm.
  • the output power signal from the transistor 120 is fed to the second stage of amplification along transmission line 127.
  • This is provided with impedance matching components 128, a DC blocking capacitor, used to match the impedance of the transistor 120 with that of the second stage.
  • the output power signal of the transistor 120 is fed along transmission line 127 to a divider 129, where it is divided into a first signal fed along transmission line 130 to divider 132, and a second signal fed along transmission line 131 to divider 135.
  • the transmission lines 130,131 are provided with matching components 138.
  • the first signal is divided and fed along transmission lines 133,134 into the second stage of amplification via resistors 139.
  • the second signal is divided and fed along transmission lines 136, 137 into the second stage of amplification via resistors 139.
  • the second stage of amplification comprises a transistor 140. This has a gate width of 3mm and comprises 48 fingers each finger having a width of 62.5 ⁇ m.
  • the transistor is earthed by terminals 141.
  • the transistor has a first gate bias line 142 and a second gate bias line 143 thereto.
  • the transistor also has a first drain bias line 144 and a second drain bias line 145 thereto. Two gate and two drain bias lines are provided for better voltage balancing of the transistor. Each drain bias line is provided with damping elements 146.
  • Output power signals are taken from the transistor 140 at four points.
  • a first signal is fed along transmission line 147 to a combiner 149.
  • a second signal is fed along transmission line 148 to the combiner 149.
  • a third signal is fed along transmission line 150 to the combiner 152.
  • a fourth signal is fed along transmission line 151 to the combiner 152.
  • the first and second signals are combined and fed along transmission line 153 to divider 154.
  • the transmission line 153 is provided with impedance matching components 155.
  • the third and fourth signals are combined and fed along transmission line 156 to divider 157.
  • the transmission line 156 is provided with impedance matching components 158.
  • the divider 154 divides the signal into two signals and feeds these along transmission lines 159, 160 to further dividers 161,162.
  • the transmission lines 159,160 are also provided with matching components 163.
  • the divider 157 divides the signal into two signals and feeds these along transmission lines 164, 165 to further dividers 166,167.
  • the transmission lines 164,165 are also provided with matching components 168.
  • the dividers 161,162, 166,167 divide the signals received by them and feed the divided signals to the third stage of amplification.
  • the third stage of amplification comprises a transistor 170.
  • This has a gate width of 7.68mm and comprises 96 fingers each having a width of 80 ⁇ m.
  • the transistor has a first gate bias line 171 and a second gate bias line 172 thereto.
  • the transistor also has a first drain bias line 173 and a second drain bias line 174 thereto.
  • the drain bias lines are provided with damping elements 175.
  • the transistor is earthed via terminals 176.
  • Output power signals are taken from the transistor at eight points. These are fed along transmission lines 177 to a combiner 178. This combines the eight signals into two signals and feeds these along transmission lines 179, 180 to combiner 181.
  • the transmission lines 179,180 are provided with impedance matching components 182, to match the impedance of the combined output power signals of the transistor 170 with that of the circuit (not shown) to which the output of the channel is connected for use.
  • the impedance of this circuit is approximately 50ohm.
  • the combiner 181 combines the signals received by it and feeds a single output power signal along transmission line 183 to the output 184 of the channel of the amplifier.
  • the transmission line 183 is provided with impedance matching components 185, to match the impedance of the combined output power signal with that of the circuit to which the output of the channel is connected for use.
  • the amplifier of the second aspect of the invention comprises two such channels.
  • the output power signal of each of these is at least 4W, and these are combined to give an output power signal of the amplifier of at least 8W.
  • Figure 7 shows the circuit details of the components of the amplifier channel of Figure 6.
  • Figure 7 is shown split into two parts for convenience the parts being joined at reference numerals 1 and 2 as shown.
  • the invention may be applicable to wavelengths other than microwaves.
  • the topology of the amplifiers and amplifier modules may be modified to allow amplification of electromagnetic signals other than microwaves.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microwave Amplifiers (AREA)

Abstract

L'invention concerne un amplificateur à semi-conducteurs comprenant au moins un canal muni d'au moins un transistor. L'amplificateur a une puissance de signal de sortie d'au moins 8 W et est capable d'amplifier des signaux possédant une largeur de bande de fréquence d'au moins 200 %. Un module d'amplificateur comprend deux ou plusieurs amplificateurs, le signal d'amplification de puissance du module se présentant comme une combinaison des signaux de sortie des amplificateurs. Un module amplificateur comprend au moins deux amplificateurs à semi-conducteurs (80, 81) dont chacun possède au moins un canal comprenant au moins un transistor. Chaque amplificateur possède une sortie d'au moins 5 W et est capable d'amplifier des signaux possédant une largeur de bande de fréquence d'à peu près ou d'au moins 200 %. Le signal de puissance de sortie du module constitue les signaux de puissance combinés des amplificateurs.
PCT/GB2000/000225 1999-01-27 2000-01-27 Amplificateurs hyperfrequence WO2000045508A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP00901224A EP1151533A1 (fr) 1999-01-27 2000-01-27 Amplificateurs hyperfrequence
JP2000596662A JP2002536861A (ja) 1999-01-27 2000-01-27 マイクロ波増幅器
AU21184/00A AU2118400A (en) 1999-01-27 2000-01-27 Microwave amplifiers

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9901634.7 1999-01-27
GBGB9901634.7A GB9901634D0 (en) 1999-01-27 1999-01-27 Microwave amplifiers

Publications (1)

Publication Number Publication Date
WO2000045508A1 true WO2000045508A1 (fr) 2000-08-03

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EP (1) EP1151533A1 (fr)
JP (1) JP2002536861A (fr)
AU (1) AU2118400A (fr)
GB (1) GB9901634D0 (fr)
WO (1) WO2000045508A1 (fr)

Cited By (6)

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Publication number Priority date Publication date Assignee Title
EP1201028A1 (fr) * 1999-06-10 2002-05-02 Raytheon Company Amplificateur a transistors a oscillations parasites reduites
WO2003098795A1 (fr) * 2002-05-22 2003-11-27 Koninklijke Philips Electronics N.V. Amplificateur de puissance radioelectrique
EP1962418A1 (fr) 2007-02-23 2008-08-27 NTT DoCoMo, Inc. Amplificateur de réception cryogénique et procédé d'amplification
CN101252344B (zh) * 2007-02-23 2011-09-28 株式会社Ntt都科摩 低温接收放大器以及放大方法
EP2980990A4 (fr) * 2013-03-26 2017-03-08 Nec Corporation Amplificateur de puissance
CN108462475A (zh) * 2017-02-21 2018-08-28 波音公司 3d低通量、高功率mmic放大器

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102655394B (zh) * 2012-05-23 2014-12-10 中国电子科技集团公司第五十五研究所 一种直流与微波信号交叉布线的放大器电路
CN113632374A (zh) * 2019-04-04 2021-11-09 三菱电机株式会社 功率放大器
JPWO2022180658A1 (fr) * 2021-02-24 2022-09-01

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COOPER S ET AL: "8-WATT HIGH EFFICIENCY X-BAND POWER AMPLIFIER USING ALGAAS/GAAS HFET TECHNOLOGY", PROCEEDINGS OF THE GALLIUM ARSENIDE INTEGRATED CIRCUIT SYMPOSIUM. (GAAS IC),US,NEW YORK, IEEE, vol. SYMP. 14, 1992, pages 183 - 185, XP000346803, ISBN: 0-7803-0773-9 *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1201028A1 (fr) * 1999-06-10 2002-05-02 Raytheon Company Amplificateur a transistors a oscillations parasites reduites
EP1201028A4 (fr) * 1999-06-10 2004-03-10 Raytheon Co Amplificateur a transistors a oscillations parasites reduites
WO2003098795A1 (fr) * 2002-05-22 2003-11-27 Koninklijke Philips Electronics N.V. Amplificateur de puissance radioelectrique
EP1962418A1 (fr) 2007-02-23 2008-08-27 NTT DoCoMo, Inc. Amplificateur de réception cryogénique et procédé d'amplification
US7795965B2 (en) 2007-02-23 2010-09-14 Ntt Docomo, Inc. Cryogenic receiving amplifier and amplifying method
CN101252344B (zh) * 2007-02-23 2011-09-28 株式会社Ntt都科摩 低温接收放大器以及放大方法
EP2980990A4 (fr) * 2013-03-26 2017-03-08 Nec Corporation Amplificateur de puissance
US9667198B2 (en) 2013-03-26 2017-05-30 Nec Corporation Power amplifier
CN108462475A (zh) * 2017-02-21 2018-08-28 波音公司 3d低通量、高功率mmic放大器
CN108462475B (zh) * 2017-02-21 2023-08-04 波音公司 3d低通量、高功率mmic放大器

Also Published As

Publication number Publication date
GB9901634D0 (en) 1999-07-14
JP2002536861A (ja) 2002-10-29
EP1151533A1 (fr) 2001-11-07
AU2118400A (en) 2000-08-18

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