WO2000043849A3 - Elektronischer phasenregelkreis (pll) - Google Patents

Elektronischer phasenregelkreis (pll) Download PDF

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Publication number
WO2000043849A3
WO2000043849A3 PCT/DE2000/000021 DE0000021W WO0043849A3 WO 2000043849 A3 WO2000043849 A3 WO 2000043849A3 DE 0000021 W DE0000021 W DE 0000021W WO 0043849 A3 WO0043849 A3 WO 0043849A3
Authority
WO
WIPO (PCT)
Prior art keywords
pll
locking loop
phase
electronic phase
networks
Prior art date
Application number
PCT/DE2000/000021
Other languages
English (en)
French (fr)
Other versions
WO2000043849A2 (de
Inventor
Siegfried Hart
Heinz Werker
Original Assignee
Infineon Technologies Ag
Siegfried Hart
Heinz Werker
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Siegfried Hart, Heinz Werker filed Critical Infineon Technologies Ag
Priority to US09/889,260 priority Critical patent/US6747495B1/en
Publication of WO2000043849A2 publication Critical patent/WO2000043849A2/de
Publication of WO2000043849A3 publication Critical patent/WO2000043849A3/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S331/00—Oscillators
    • Y10S331/02—Phase locked loop having lock indicating or detecting means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

Der elektronische Phasenregelkreis (PLL) in digitaler Ausbildung wird durch einen zusätzlichen analogen Phasendetektor (APD) ergänzt, womit sich der Phasenfehler ('Jitter') noch besser als bisher bedämpfen läßt. Der PLL findet insbesondere als integrierte Schaltung (IC) seine Anwendung in dienstintegrierten Kommunikationsnetzen (ISDN), Datenkommunikation oder Netzwerken.
PCT/DE2000/000021 1999-01-21 2000-01-03 Elektronischer phasenregelkreis (pll) WO2000043849A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/889,260 US6747495B1 (en) 1999-01-21 2000-01-03 Low jitter analog-digital locker loop with lock detection circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19902335 1999-01-21
DE19902335.2 1999-01-21

Publications (2)

Publication Number Publication Date
WO2000043849A2 WO2000043849A2 (de) 2000-07-27
WO2000043849A3 true WO2000043849A3 (de) 2001-05-31

Family

ID=7894985

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2000/000021 WO2000043849A2 (de) 1999-01-21 2000-01-03 Elektronischer phasenregelkreis (pll)

Country Status (2)

Country Link
US (1) US6747495B1 (de)
WO (1) WO2000043849A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004006996B4 (de) * 2004-02-12 2006-09-28 Infineon Technologies Ag Digitaler Phasenregelkreis mit schnellem Einschwingverhalten
US9735679B2 (en) * 2015-12-03 2017-08-15 Nuvoton Technology Corporation Method and apparatus for a delay locked power supply regulator
CN112084733B (zh) * 2020-08-14 2024-06-21 深圳天狼芯半导体有限公司 芯片的时钟树布图方法及装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4864253A (en) * 1987-12-22 1989-09-05 Siemens Aktiengesellschaft Phase locked loop wherein phase comparing and filtering are performed by microprocessor
JPH02149018A (ja) * 1988-11-30 1990-06-07 Nec Eng Ltd 自動周波数制御回路
US5487093A (en) * 1994-05-26 1996-01-23 Texas Instruments Incorporated Autoranging digital analog phase locked loop
US5546433A (en) * 1995-03-21 1996-08-13 National Semiconductor Corporation Digital phase lock loop having frequency offset cancellation circuitry

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4490688A (en) * 1981-04-06 1984-12-25 Motorola, Inc. Digital and analog phase detector for a frequency synthesizer
US4686560A (en) * 1986-05-30 1987-08-11 Rca Corporation Phase locked loop system including analog and digital components
US5057793A (en) * 1989-11-13 1991-10-15 Cowley Nicholas P Frequency synthesizer PLL having digital and analog phase detectors
US6028460A (en) * 1998-06-08 2000-02-22 Comtech Communications Corp. Hybrid analog-digital phase lock loop multi-frequency synthesizer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4864253A (en) * 1987-12-22 1989-09-05 Siemens Aktiengesellschaft Phase locked loop wherein phase comparing and filtering are performed by microprocessor
JPH02149018A (ja) * 1988-11-30 1990-06-07 Nec Eng Ltd 自動周波数制御回路
US5487093A (en) * 1994-05-26 1996-01-23 Texas Instruments Incorporated Autoranging digital analog phase locked loop
US5546433A (en) * 1995-03-21 1996-08-13 National Semiconductor Corporation Digital phase lock loop having frequency offset cancellation circuitry

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MIHAI BANU: "DESIGN OF HIGH-SPEED, WIDE-BAND MOS OSCILLATORS FOR MONOLITHIC PHASE-LOCKED LOOP APPLICATIONS", PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS,US,NEW YORK, IEEE, vol. CONF. 21, 7 June 1988 (1988-06-07), pages 1673 - 1677, XP000014651, ISBN: 951-721-240-2 *
PATENT ABSTRACTS OF JAPAN vol. 014, no. 396 (E - 0970) 27 August 1990 (1990-08-27) *

Also Published As

Publication number Publication date
WO2000043849A2 (de) 2000-07-27
US6747495B1 (en) 2004-06-08

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