WO2000042649A1 - Test device of semiconductor integrated circuit - Google Patents

Test device of semiconductor integrated circuit Download PDF

Info

Publication number
WO2000042649A1
WO2000042649A1 PCT/SG1999/000150 SG9900150W WO0042649A1 WO 2000042649 A1 WO2000042649 A1 WO 2000042649A1 SG 9900150 W SG9900150 W SG 9900150W WO 0042649 A1 WO0042649 A1 WO 0042649A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
array
reject
mounting
marking points
Prior art date
Application number
PCT/SG1999/000150
Other languages
French (fr)
Inventor
Kian Teng Eng
Chuen Khiang Wang
Original Assignee
Kian Teng Eng
Chuen Khiang Wang
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kian Teng Eng, Chuen Khiang Wang filed Critical Kian Teng Eng
Publication of WO2000042649A1 publication Critical patent/WO2000042649A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0293—Individual printed conductors which are adapted for modification, e.g. fusable or breakable conductors, printed switches
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/168—Wrong mounting prevention

Definitions

  • the present invention relates to integrated circuit (IC) manufacture and particularly to a method of identifying rejects at the IC packaging stage.
  • IC integrated circuit
  • the completed circuit on a silicon substrate or chip, is physically attached to a lead frame or printed circuit board (PCB) substrate and electrical connections to the chip are made with gold wire.
  • PCB printed circuit board
  • the connected chip is then encapsulated, e.g. in resin, to form the completed package.
  • the ICs are tested and marked as rejects if found to be defective in any way. How this marking is done depends on the stage of manufacture at which the reject is detected. If the encapsulation has not been completed, a known method is to attach a piece of polyimide adhesive tape on or near the rejected IC. If the encapsulation has been completed, it is. known to use a diamond pen to mark, e.g. with an X, the surface of the reject IC. These methods have disadvantages. For example, marking with a diamond pen by hand does not always produce an easily visible or consistent mark. Another known method of identifying rejects is to punch a hole in the lead frame adjacent the rejected unit.
  • a method of manufacturing integrated circuits comprising: providing a substrate having an array of mounting positions for semiconductor devices and an array of predefined reject marking points corresponding to said mounting positions; testing said substrate; and where a fault is detected in said testing step, effecting a mark at the reject marking point corresponding to the mounting position at which the fault was detected.
  • the present invention also provides a substrate for mounting semiconductor devices, the substrate comprising: an array of mounting positions for a plurality of semiconductor devices; and an array of predefined reject marking points corresponding to respective mounting positions.
  • the predefined reject mark comprises a partially formed through-hole which is completed to indicate a rejected IC.
  • the partially formed through-hole may be an incomplete annular through-hole that leaves an island joined to the rest of the substrate by relatively narrow tie- bars. These are easily broken out to leave a complete through-hole.
  • the island may be circular, which is usable if the substrate is a lead frame or ball grid array (BGA) substrate.
  • BGA ball grid array
  • the island may take the form of a zig-zag path or Greek key pattern, this is useful with BGA substrates. In this way, the present invention allows the location of a faulty device to be quickly and reliably indicated.
  • the use of a partial through- hole which is then completed to indicate a reject ensures that rejects are indicated by a through-hole of consistent size which ensures their recognition by human operators as well as vision recognition systems or other automated detectors.
  • the present invention is applicable to lead frame, BGA and other printed circuit board (PCB) substrates.
  • Figure 1 is a schematic cross-sectional view of a lead-on-chip (LOC) DRAM device to the manufacture of which the present invention may be applied;
  • LOC lead-on-chip
  • Figure 2 is a schematic view of a lead frame substrate to which the present invention is applied;
  • Figures 3A and B are enlarged views of the reject mark according to a first embodiment of the present invention.
  • Figures 4A and B are enlarged views of the reject mark according to a second embodiment of the present invention.
  • Figure 5 is a schematic view of a lead frame substrate showing alternative ways in which the present invention may be applied.
  • like parts are identified by like references.
  • a silicon chip 1 is bonded to lead frame 2 by adhesive, e.g . polyimide, tape 3. Electrical connections are made by gold wires 4 which connects bond pads 5 on the chip to tracks on the lead frame 2. At the chip end the wires 4 are connected by gold ball bonds 6 and the lead frame 2 end by stitch bonds 7. The whole chip is then encased in resin to form the complete package 8.
  • Figure 1 shows a typical lead-on-chip (LOC) dynamic random access memory (DRAM) design but the present invention may be readily applied to other types of integrated circuit and other packaging methods.
  • LOC lead-on-chip
  • DRAM dynamic random access memory
  • a typical lead frame substrate will have a number of IC packages set out in a rectangular array.
  • Figure 2 shows a lead frame substrate 2 having a 3x3 array of IC package mounts but other arrangements are possible.
  • a row of predefined reject markers 1 0a-c is provided at the top of each column of IC package mounts, with one marker for each IC package mount in the column, in this case 3.
  • the row of markers 10a-c is in this case inclined but may be horizontal or vertical as space permits. The inclination of the row forms a visual reminder that marker 1 0a corresponds to IC package mount 8a, marker 10b to IC package mount 8b and marker 1 0c to IC package mount 8c.
  • each marker 1 0 comprises an island 1 1 joined to the remainder of the substrate by tie-bars 1 2.
  • the island and tie bars are defined by making part-annular through-holes 1 3 in the substrate.
  • the IC mounts, the associated wiring, the silicon chip mounted on each IC mount and the encapsulation are tested in various ways. If, at any stage a mount or the IC mounted there fails a test and is considered a reject, the island 1 1 in the corresponding reject marker 1 0 is broken out to indicate the reject status of the associated IC. The island can easily be broken. out by breaking the tie bars, either automatically or manually with an appropriate tool. Once broken out, the marker will appear as in Figure 3B, with only short stubs 1 2' of the tie bars remaining. The marker thus presents a through-hole of regular size and shape which can easily be detected visually or automatically.
  • the marker takes the form of a zig-zag path or Greek key pattern 14 joined to the remainder of the substrate by two tie bars 1 5.
  • a uniform through-hole is again presented and can again be easily recognised or detected.
  • the predefined reject marking points of the invention need not be arrayed as shown in Figure 2. Instead, the array of reject marking points may be interleaved with the array of IC mounting positions.
  • Figure 5 shows two possibilities. Reject marking points 20a to 20c, which may be the same as the reject marking points shown in Figures

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Automation & Control Theory (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A lead frame or PCB (e.g. a ball grid array) has an array of IC package mounts (8a-c). At the head of each column an inclined line of reject markers (10a-c) is provided, one for each IC package mount in the column. Each reject marker (10) comprises an island joined to the remainder of the substrate by short tie-bars. The islands are broken out to indicate the corresponding IC mount or an IC package mounted there is a reject.

Description

TEST DEVICE OF SEMICONDUCTOR INTEGRATED CIRCUIT
The present invention relates to integrated circuit (IC) manufacture and particularly to a method of identifying rejects at the IC packaging stage.
In manufacture of ICs, the completed circuit, on a silicon substrate or chip, is physically attached to a lead frame or printed circuit board (PCB) substrate and electrical connections to the chip are made with gold wire. The connected chip is then encapsulated, e.g. in resin, to form the completed package.
At various stages in the manufacturing process the ICs are tested and marked as rejects if found to be defective in any way. How this marking is done depends on the stage of manufacture at which the reject is detected. If the encapsulation has not been completed, a known method is to attach a piece of polyimide adhesive tape on or near the rejected IC. If the encapsulation has been completed, it is. known to use a diamond pen to mark, e.g. with an X, the surface of the reject IC. These methods have disadvantages. For example, marking with a diamond pen by hand does not always produce an easily visible or consistent mark. Another known method of identifying rejects is to punch a hole in the lead frame adjacent the rejected unit. However, in this case, it is necessary to provide substantial space between the ICs on the lead frame to prevent damage being caused to other ICs when the hole is made. Punching a hole can cause stresses in the lead frame that affect neighbouring ICs and can deform the lead frame out of planarity.
On PCB substrates such as Ball Grid Array (BGA) substrates, rejects that are detected before encapsulation are known to be marked by writing on the substrate with a permanent marker or by punching a hole through the electrical circuitry. Both of these methods suffer from the defect that the mark is not visible after the encapsulation process. According to the present invention, there is provided a method of manufacturing integrated circuits, the method comprising: providing a substrate having an array of mounting positions for semiconductor devices and an array of predefined reject marking points corresponding to said mounting positions; testing said substrate; and where a fault is detected in said testing step, effecting a mark at the reject marking point corresponding to the mounting position at which the fault was detected. The present invention also provides a substrate for mounting semiconductor devices, the substrate comprising: an array of mounting positions for a plurality of semiconductor devices; and an array of predefined reject marking points corresponding to respective mounting positions.
Preferably, the predefined reject mark comprises a partially formed through-hole which is completed to indicate a rejected IC. The partially formed through-hole may be an incomplete annular through-hole that leaves an island joined to the rest of the substrate by relatively narrow tie- bars. These are easily broken out to leave a complete through-hole. The island may be circular, which is usable if the substrate is a lead frame or ball grid array (BGA) substrate. Alternatively, the island may take the form of a zig-zag path or Greek key pattern, this is useful with BGA substrates. In this way, the present invention allows the location of a faulty device to be quickly and reliably indicated. The use of a partial through- hole which is then completed to indicate a reject ensures that rejects are indicated by a through-hole of consistent size which ensures their recognition by human operators as well as vision recognition systems or other automated detectors. The present invention is applicable to lead frame, BGA and other printed circuit board (PCB) substrates.
The present invention will be further described below with reference to exemplary embodiments and the accompanying drawings, in which:
Figure 1 is a schematic cross-sectional view of a lead-on-chip (LOC) DRAM device to the manufacture of which the present invention may be applied;
Figure 2 is a schematic view of a lead frame substrate to which the present invention is applied;
Figures 3A and B are enlarged views of the reject mark according to a first embodiment of the present invention;
Figures 4A and B are enlarged views of the reject mark according to a second embodiment of the present invention; and Figure 5 is a schematic view of a lead frame substrate showing alternative ways in which the present invention may be applied. In the drawings, like parts are identified by like references.
As shown in Figure 1 , a silicon chip 1 is bonded to lead frame 2 by adhesive, e.g . polyimide, tape 3. Electrical connections are made by gold wires 4 which connects bond pads 5 on the chip to tracks on the lead frame 2. At the chip end the wires 4 are connected by gold ball bonds 6 and the lead frame 2 end by stitch bonds 7. The whole chip is then encased in resin to form the complete package 8. Figure 1 shows a typical lead-on-chip (LOC) dynamic random access memory (DRAM) design but the present invention may be readily applied to other types of integrated circuit and other packaging methods.
A typical lead frame substrate will have a number of IC packages set out in a rectangular array. Figure 2 shows a lead frame substrate 2 having a 3x3 array of IC package mounts but other arrangements are possible. ln the embodiment of the invention shown in Figure 2, a row of predefined reject markers 1 0a-c is provided at the top of each column of IC package mounts, with one marker for each IC package mount in the column, in this case 3. The row of markers 10a-c is in this case inclined but may be horizontal or vertical as space permits. The inclination of the row forms a visual reminder that marker 1 0a corresponds to IC package mount 8a, marker 10b to IC package mount 8b and marker 1 0c to IC package mount 8c. Any suitable mapping of reject markers in their array to IC mount positions in their array may be used. As shown enlarged in Figure 3A, each marker 1 0 comprises an island 1 1 joined to the remainder of the substrate by tie-bars 1 2. The island and tie bars are defined by making part-annular through-holes 1 3 in the substrate.
At various stages in the manufacturing process, the IC mounts, the associated wiring, the silicon chip mounted on each IC mount and the encapsulation are tested in various ways. If, at any stage a mount or the IC mounted there fails a test and is considered a reject, the island 1 1 in the corresponding reject marker 1 0 is broken out to indicate the reject status of the associated IC. The island can easily be broken. out by breaking the tie bars, either automatically or manually with an appropriate tool. Once broken out, the marker will appear as in Figure 3B, with only short stubs 1 2' of the tie bars remaining. The marker thus presents a through-hole of regular size and shape which can easily be detected visually or automatically. In an alternative embodiment of the invention shown in Figure 4A, the marker takes the form of a zig-zag path or Greek key pattern 14 joined to the remainder of the substrate by two tie bars 1 5. When broken out, as shown in Figure 4B, a uniform through-hole is again presented and can again be easily recognised or detected. As mentioned above, the predefined reject marking points of the invention need not be arrayed as shown in Figure 2. Instead, the array of reject marking points may be interleaved with the array of IC mounting positions. Figure 5 shows two possibilities. Reject marking points 20a to 20c, which may be the same as the reject marking points shown in Figures
3 and 4, are arrayed alongside the column of IC mounting positions with each reject marking point alongside the respective IC mounting position- Reject marking points 30a to 30c, which again may be the same as the reject marking points shown in Figures 3 and 4, are arrayed within the column of IC mounting positions with each reject marking point below the respective IC mounting position.

Claims

1 . A method of manufacturing integrated circuits, the method comprising: providing a substrate having an array of mounting positions for semiconductor devices and an array of predefined reject marking points corresponding to said mounting positions; testing said substrate; and where a fault is detected in said testing step, effecting a mark at the reject marking point corresponding to the mounting position at which the fault was detected.
2. A method according to claim 1 wherein said step of providing a substrate comprises the step of partially forming through-holes in the substrate at said predefined reject marking points; and wherein said step of effecting a mark comprises completing the formation of a through-hole at the reject marking point corresponding to the mounting position at which the fault was detected .
3. A method according to claim 2 wherein said step of partially forming through-holes comprises forming an incomplete annular through-hole in the substrate to form an island connected to the remainder of the substrate by one or more tie-bars and said step of effecting a mark comprises breaking the or each tie bar to detach said island.
4. A method according to claim 3 wherein said island is disc shaped.
5. A method according to claim 3 wherein said island is in the shape of a zig-zag path.
6. A method according to any one of the preceding claims, wherein said substrate comprises a lead frame or a printed circuit board such as a ball grid array substrate.
7. A method according to any one of the preceding claims, wherein said steps of testing and effecting a mark are carried out at one or more of: before mounting of ICs on the substrate, before encapsulation of ICs mounted on the substrate, and after encapsulation of ICs mounted on the substrate.
8. A substrate for mounting semiconductor devices, the substrate comprising : an array of mounting positions for a plurality of semiconductor devices; and an array of predefined reject marking points corresponding to respective mounting positions.
9. A substrate according to claim 8 wherein said reject marking points comprise partially formed through-holes in said substrate.
10. A substrate according to claim 9 wherein said partially formed through-holes comprise incomplete annular through-holes forming islands connected to the remainder of said substrate by one or more tie-bars.
1 1 . A substrate according to claim 1 0 wherein said islands are circular in shape.
1 2. A substrate according to claim 1 0 wherein said islands have the shape of a zig-zag path.
1 3. A substrate according to any one of claims 8 to 1 2 wherein said array of reject marking points is situated outside of the area covered by said array of mounting positions.
1 4. A substrate according to any one of claims 8 to 1 3 wherein each said reject marking points is located in the array thereof at a location corresponding to the location of its respective mounting position.
1 5. A method of manufacturing integrated circuits substantially as hereinbefore described with reference to the accompanying drawings.
1 6. A substrate for mounting integrated circuits constructed substantially as hereinbefore described with reference to the accompanying drawings.
PCT/SG1999/000150 1999-01-11 1999-12-29 Test device of semiconductor integrated circuit WO2000042649A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SG9900010A SG115324A1 (en) 1999-01-11 1999-01-11 Integrated circuit manufacture
SG9900010-1 1999-01-11

Publications (1)

Publication Number Publication Date
WO2000042649A1 true WO2000042649A1 (en) 2000-07-20

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1517403A2 (en) * 2003-08-29 2005-03-23 Fujitsu Ten Limited Circular polarization antenna and composite antenna including this antenna

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Publication number Priority date Publication date Assignee Title
US4779981A (en) * 1984-10-22 1988-10-25 Canon Kabushiki Kaisha Reject chip marking device and method of discriminating reject mark
JPH03237751A (en) * 1990-02-15 1991-10-23 Hitachi Ltd Lead frame, and semiconductor integrated circuit device and marking device using it
JPH05152388A (en) * 1991-11-28 1993-06-18 Sharp Corp Test device of semiconductor integrated circuit device
JPH0917831A (en) * 1995-04-26 1997-01-17 Nec Corp Wafer probing device

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Publication number Priority date Publication date Assignee Title
JPH0917830A (en) * 1995-06-27 1997-01-17 Canon Inc Wire bonding inspection device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4779981A (en) * 1984-10-22 1988-10-25 Canon Kabushiki Kaisha Reject chip marking device and method of discriminating reject mark
JPH03237751A (en) * 1990-02-15 1991-10-23 Hitachi Ltd Lead frame, and semiconductor integrated circuit device and marking device using it
JPH05152388A (en) * 1991-11-28 1993-06-18 Sharp Corp Test device of semiconductor integrated circuit device
JPH0917831A (en) * 1995-04-26 1997-01-17 Nec Corp Wafer probing device

Non-Patent Citations (3)

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Title
PATENT ABSTRACTS OF JAPAN & JP 03237751 A (HITACHI LTD.) 23-10-1991 *
PATENT ABSTRACTS OF JAPAN & JP 05152388 A (SHARP CORP.) 18-06-1993 *
PATENT ABSTRACTS OF JAPAN & JP 09017831 A (CANON INC.) 17-01-1997 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1517403A2 (en) * 2003-08-29 2005-03-23 Fujitsu Ten Limited Circular polarization antenna and composite antenna including this antenna
EP1517403A3 (en) * 2003-08-29 2006-04-12 Fujitsu Ten Limited Circular polarization antenna and composite antenna including this antenna
US7286098B2 (en) 2003-08-29 2007-10-23 Fujitsu Ten Limited Circular polarization antenna and composite antenna including this antenna

Also Published As

Publication number Publication date
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