WO2000028401A1 - Procede et dispositif de synchronisation d'une horloge locale sur l'horloge d'un reseau de communication sans fil - Google Patents
Procede et dispositif de synchronisation d'une horloge locale sur l'horloge d'un reseau de communication sans fil Download PDFInfo
- Publication number
- WO2000028401A1 WO2000028401A1 PCT/FR1999/002599 FR9902599W WO0028401A1 WO 2000028401 A1 WO2000028401 A1 WO 2000028401A1 FR 9902599 W FR9902599 W FR 9902599W WO 0028401 A1 WO0028401 A1 WO 0028401A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- phase shift
- clock
- local clock
- network
- correction
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40052—High-speed IEEE 1394 serial bus
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/10—Arrangements for initial synchronisation
Definitions
- the invention relates to a method for synchronizing a local clock of a device with the clock of a wireless communication network to which said device is connected. It also relates to a synchronization device capable of operating according to said method in such a network.
- the invention is particularly applicable in the context of a wireless home communication network.
- each device (node" according to IEEE 1394 terminology) connected to the bus stamps the packets it sends with time information indicating when the packet should be returned by the receiving device.
- Each device (or “node”) connected to the bus has a 32-bit clock register, incremented at the clock frequency of the bus, namely 24.576 MHz.
- This register (called “Cycle Time Register” according to the English terminology of the IEEE 1394-1995 standard) is divided into three ranges (the least significant 12 bits, the intermediate weight 13 bits and the most significant 7 bits ), which are therefore incremented respectively at frequencies of 24.576 MHz, 8 kHz and 1 kHz.
- cycle master device In the presence of devices likely to participate in isochronous traffic, and to synchronize these devices, one of them is elected “cycle master device or node” (“Cycle master” according to the English terminology IEEE 1394) .
- the cycle master device generates a cycle start packet ("cycle start packet” in English IEEE 1394 terminology) or an isochronous frame every 125 ⁇ s, which corresponds to a frequency of 8 kHz.
- This packet contains the value of the 32-bit clock register of the cycle master device at the time of transmission. It is then expected that a device receiving the packet slaves its own 32-bit register to the values received from the cycle master device.
- one of the devices connected to one of the buses is elected “network cycle master device"("net cycle master” according to IEEE 1394 terminology).
- the portal which is the network cycle master device, or the portal connected to the bus to which the network cycle master device is connected, is referred to as “cycle server” according to the terminology. IEEE 1394).
- the cycle server is responsible for transmitting the clock from the network cycle master device to the other portals.
- the cycle master devices of the other buses are thus calibrated on the clock received from their portals.
- the local clocks of the portals must be able to synchronize correctly with the clock of the cycle server.
- the object of the invention is to propose a solution making it possible to meet this requirement.
- the subject of the invention is a method of synchronizing a local clock of a device with a clock of a wireless communication network to which said device is connected, characterized in that, the transmission of frames being carried out according to a TDMA type mode, said method comprises the following steps:
- the network clock having been correctly recovered, the received signal is sampled with the right phase, which will allow reception between samples without interference.
- a control window being a predetermined time interval the start of which is defined relatively with respect to the start of the transmitted frame, a control window per frame being allocated to each transmitting apparatus, the determination step comprises a step of detecting an invariable pattern present at the start of each control window allocated to a device transmitting the network clock, said pattern making it possible to provide the instant corresponding to the network clock pulse.
- the detection step is performed by correlation between the pulse of the network clock and that of the local clock of the device.
- the repeated appearance of the pattern in the received frames makes it possible to specify the knowledge of the exact instant at the start of the control window dedicated to the reference device.
- the maximum of the correlation made to a multiple of the sampling frequency of the local clock provides the start time of the control window of the reference device with an accuracy equal to a submultiple of the period d sampling of the local clock.
- said method comprises on a transmission a step of transmission of the network clock determined on the reception channel.
- said method makes it possible to propagate the network clock and to transmit it, for example, to a device of the wireless network which is not in direct connection with the cycle server.
- the determining step comprises a step of slaving the pulse of the network clock.
- said correction of the entire part is carried out by phase shift of the pulse of the local clock to a submultiple of the sampling period of the device.
- said second correction of the fractional part is carried out in the frequency domain by rotation of vectors translating the samples received.
- said step of determining the time phase shift is used for a third correction of the whole part of said phase shift and a fourth correction of the fractional part to be carried out on the local clock transmitted on a transmission channel.
- said fourth correction is carried out in the frequency domain by interpolation of the vectors translating the samples transmitted.
- the corrections of fractional part are carried out in the time domain by interpolation.
- the phase shift introduced on the transmission channel is greater than that introduced on the reception channel, in order to take into account, during the transmission of the frames, the processing time due to coding, to the addressing the constellation, modulating the symbols and in order to anticipate this processing time when establishing the clock to be transmitted.
- the invention also relates to a synchronization device suitable for implementing the method according to one of the preceding claims for synchronizing a local clock of an apparatus with the clock of a wireless communication network.
- said device comprises:
- a first set of means for correcting the local clock of the device on the reception channel as a function of said determined phase shift comprising first means for correcting the entire part of the phase shift in the time domain and second means for correcting of the fractional part of the phase shift able to recover the residual phase shift.
- said determination means comprise a correlator intended to supply the clock pulse of the network to a submultiple of the sampling period of the device close to and a servo block of the local clock for locking the local clock on the network clock.
- said first set of correction means comprises:
- said synchronization device comprises a second set of means for correcting the local clock of the apparatus on an emission channel as a function of said determined phase shift, comprising third means for correcting the entire part of the phase shift in the time domain and fourth means for correcting the fractional part capable of recovering the residual phase shift.
- said second set of correction means comprises:
- phase shift block on the transmission channel for the phase shift of the pulse of the local clock by a delay corresponding to the whole part of said determined phase shift, - a second processing block for the phase shift corresponding to the part fractional determined on the receiving channel.
- said first and second processing blocks respectively comprise a block for calculating the Transformation of
- each of the processing blocks comprising a phase shifter capable of applying, in the frequency domain, a rotation of the vectors representing the samples of the frame.
- said first and second processing blocks respectively comprise an interpolator capable of interpolating the phase shift corresponding to the determined fractional part and of delaying the clock of the device by a delay calculated on the transmission channel.
- FIG. 1 represents a diagram representing three IEEE 1394 buses connected by a bridge consisting of three portals communicating with each other by wireless transmission,
- FIG. 2 represents a synchronization device according to an embodiment of the invention
- FIG. 3 shows a synchronization device according to a variant of the invention.
- the same references will be used to designate the elements fulfilling identical functions.
- the exemplary embodiment relates to IEEE 1394 buses and an associated wireless network, and the description uses certain terms derived from the terminology associated with this type of bus, the invention is not limited to the IEEE 1394 bus and can apply in other environments.
- FIG. 1 represents a network consisting of three IEEE 1394 type buses, referenced 1, 2 and 3, interconnected by a wireless network 50 to which the buses are connected respectively by so-called “portal” devices ("portais” according to the terminology adopted by document P 1394.1) WL1, WL2 and WL3.
- the gates communicate with each other by wireless transmission, using radio frequencies according to the present case.
- the meeting of the portals constitutes what will be called in the following a "bridge” wireless, realizing the interconnection of the buses.
- portals WL1, WL2, WL3 are each also members of buses 1, 2, 3 respectively, and therefore constitute nodes within the meaning of the IEEE 1394 standard in the same way as other devices 5, 6 connected to the buses.
- the device 4 connected to bus 1 is elected “network cycle master device” ("net cycle master” according to IEEE 1394 terminology). It should be noted that this concept is broader than that of "cycle master” which is limited to a bus.
- the network cycle master device 4, which can also be one of the portals, is designated by the bridge manager (IEEE 1394 terminology) from among the cycle master devices of the various buses.
- the portal WL1 being the portal connected to the bus to which the device 4 master of the network cycle is connected, is designated by the name of "cycle server” ("cycle server” according to the terminology IEEE 1394).
- the WL1 device is the cycle server. It is the cycle server WL1 which is responsible for transmitting to the other portal devices WL2, WL3 the clock coming from the device 4 cycle master of the network.
- the cycle master devices of the other buses 2, 3 will be set to the clock received from their respective portal devices WL2, WL3.
- the wireless network uses a TDMA (Time Division Multiplex Access') type mechanism for access to the wireless transmission channel, a TDMA frame being subdivided into windows during which the devices can transmit.
- a control window is a predetermined time interval whose start is defined relatively by report at the start of the frame, a control window per frame being allocated to each portal device of the wireless network capable of transmitting
- the WL1 portal device sends the network clock to the wireless network, which is received at the WL2, WL3 devices.
- the synchronization of the device 5 on the clock we will limit our hereinafter to the explanation of the synchronization of the device 5 on the clock.
- this explanation can be extended to any other device on the wireless network.
- a device not shown in the wireless network is in incomplete connectivity with the device WL1, that is to say that the device is not in direct connection with the device WL1, it will be considered that the device synchronizes with the clock of a device with which it is in direct connection and which is capable of carrying the network clock.
- FIG. 2 represents a synchronization device 7 included in the WL2 device according to a first embodiment of the invention.
- This device 7 comprises two reception and transmission channels 8, 9 respectively connected to the wireless network 50.
- the device 7 comprises on its reception channel 8 receiving the TDMA frames a phase correlator 10 in parallel with a first block of phase shift 1 1 comprising a delay line known per se and capable of applying a variable delay to the sampling time of the local clock.
- the output of the correlator 10 is connected to the input of a phase estimator 1 2, another input of which is connected to the output of a first integrator 1 3 capable of accumulating the phase shift of the local clock with that of the network received on the receiving lane.
- the output of the phase estimator 12 is connected to the input of a loop filter 14 whose output delivers the phase error to the phase integrator 1 3 and to a second phase integrator 1 30.
- the integrator 13 controls an input of the phase shift block 1 1 and of a phase shifter 1 5 while, on the transmission channel, the integrator 1 30 controls an input of a second phase shift block 1 6 and a phase shifter 1 7.
- An output of the phase shift block 1 1 is connected to a block 1 8 of Fourier Transform calculation delivering samples in the frequency domain to the phase shifter 1 6.
- the output of the phase shifter 1 6 which is the output of the device 7 is in turn connected, for example, to a constellation decoding block ("Constellation Demapping block" in English) which attacks a Viterbi decoder, not shown.
- the device 7 comprises, at the input of its transmission channel 9, the phase shifter 17 controlled by the integrator 130, the output of which is connected to a block 19 for calculating the Reverse Fourier Transform capable of transmitting the samples in the time domain. These samples are then delivered to the phase shift block 16.
- the input of the device 7 on the side of the transmission channel is connected, for example, to a constellation addressing circuit followed by a coding circuit, not shown.
- the integrator 13 controls the phase shifter 17 and the second phase shift block 16. The output of the latter is the output of the device 7 which emits a clock synchronized with that of the network, as explained below.
- the device WL1 transmits, as much in the acquisition phase (that is to say after restarting the network, for example) as in steady state, the preamble P known to all wireless network devices, at the start of the dedicated control window.
- the preamble is only sent periodically once every q control windows, with q positive integer.
- the device 7 detects the presence of this preamble P known by conventional correlation operation thanks to the correlator 10. The maximum of the correlation is carried out at a multiple of the sampling frequency of the device 7, providing the start time of the window for controlling the device WL1 with an accuracy equal to a submultiple of the sampling period of the device 7.
- the correlator 10 transmits a signal between 0 and 1, the maximum value of which corresponds to the detection of the preamble P.
- the phase estimator 12 receives this last signal and compares it with the output signal of the integrator 13.
- the phase estimator 12 delivers a DC voltage which is a function of the phase difference between the two signals applied to its entry.
- the loop filter 14 lets this voltage pass and delivers it to the first and second integrators 1 3, 130. In this way, as long as the correlator 10 has not detected the preamble P at the start of the control window, the integrator 13 is incremented until it is locked at the instant of the network clock.
- the locking time can of course be improved as a function of the gain of the loop filter 14.
- the integrator 13 commands the phase shift block 11 to phase shift the local clock by a value equivalent to the whole part of the recorded phase shift.
- the integrators 1 3, 130 respectively control an 8-bit time phase shift to the phase shift circuits 1 1, 1 6.
- the 0.3 bit residual sampling phase difference is then less than the submultiple of the sampling period considered.
- the samples arriving according to a temporal logic are then applied to the block 1 8 for calculating the Fourier Transform which transposes them into the frequency plane.
- the device 7 uses the phase shift information obtained by the integrator 130 and uses the principle seen above for setting on the reception channel for the transmission of the clock.
- the vectors in the input frequency domain undergo a correction of a linear phase shift corresponding to the fractional part of the phase shift measured by the integrator 130, and the output samples of block 1 9 undergo in the time domain a phase shift corresponding to the part whole of the correction to the local clock.
- the phase shift introduced on the transmission channel is greater than that introduced on the reception channel in order to take account of the processing time necessary for the transmission of the frames.
- This solution for operating the frequency domain for fine correction of the phase shift is advantageous when various disturbances can hinder the propagation of waves such as multiple echoes, in which case it is preferable to use a multicarrier modulation of the OFDM type.
- FIG. 3 represents a synchronization device 20 according to a variant of the device 7.
- the block 18 and the phase shifter 5 are replaced by an interpolator capable of correcting the fractional part by interpolation in the time domain.
- the block 1 9 and the phase shifter 1 7 are replaced by an interpolator 22 also capable of correcting the fractional part by interpolation in the time domain.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Mobile Radio Communication Systems (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99950832A EP1127305A1 (fr) | 1998-11-05 | 1999-10-26 | Procede et dispositif de synchronisation d'une horloge locale sur l'horloge d'un reseau de communication sans fil |
AU63461/99A AU6346199A (en) | 1998-11-05 | 1999-10-26 | Method for synchronising a local clock on a cordless communication network clock |
JP2000581521A JP2002529991A (ja) | 1998-11-05 | 1999-10-26 | ローカルクロックをコードレス通信網クロックと同期させる方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9813939A FR2785751A1 (fr) | 1998-11-05 | 1998-11-05 | Procede de synchronisation d'une horloge locale d'un appareil sur l'horloge d'un reseau de communication sans fil et dispositif de synchronisation associe |
FR98/13939 | 1998-11-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000028401A1 true WO2000028401A1 (fr) | 2000-05-18 |
Family
ID=9532405
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR1999/002599 WO2000028401A1 (fr) | 1998-11-05 | 1999-10-26 | Procede et dispositif de synchronisation d'une horloge locale sur l'horloge d'un reseau de communication sans fil |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP1127305A1 (fr) |
JP (1) | JP2002529991A (fr) |
CN (1) | CN1325508A (fr) |
AU (1) | AU6346199A (fr) |
FR (1) | FR2785751A1 (fr) |
WO (1) | WO2000028401A1 (fr) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6983161B2 (en) | 1999-09-08 | 2006-01-03 | Nokia Corporation | Method for performing frequency synchronization of a base station and a network part |
CN100452731C (zh) * | 2001-10-18 | 2009-01-14 | 英特尔公司 | 用于同步移动ad-hoc网络中的设备的方法和装置 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6944249B2 (en) | 2000-08-17 | 2005-09-13 | Broadcom Corporation | Method and system for transmitting isochronous voice in a wireless network |
CN102354257A (zh) * | 2011-07-13 | 2012-02-15 | 南京中兴软创科技股份有限公司 | 一种通讯平台的精确时钟管理方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5327468A (en) * | 1992-06-19 | 1994-07-05 | Westinghouse Electric Corp. | Synchronization of time-of-day clocks in a distributed processing network system |
EP0702464A1 (fr) * | 1994-09-14 | 1996-03-20 | Racotek, Inc. | Système de transmission de données avec synchronisation du temps |
EP0722233A2 (fr) * | 1994-12-21 | 1996-07-17 | Hewlett-Packard Company | Synchronisation dans un réseau de communication de données |
-
1998
- 1998-11-05 FR FR9813939A patent/FR2785751A1/fr not_active Withdrawn
-
1999
- 1999-10-26 CN CN99813038A patent/CN1325508A/zh active Pending
- 1999-10-26 AU AU63461/99A patent/AU6346199A/en not_active Abandoned
- 1999-10-26 WO PCT/FR1999/002599 patent/WO2000028401A1/fr not_active Application Discontinuation
- 1999-10-26 EP EP99950832A patent/EP1127305A1/fr not_active Withdrawn
- 1999-10-26 JP JP2000581521A patent/JP2002529991A/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5327468A (en) * | 1992-06-19 | 1994-07-05 | Westinghouse Electric Corp. | Synchronization of time-of-day clocks in a distributed processing network system |
EP0702464A1 (fr) * | 1994-09-14 | 1996-03-20 | Racotek, Inc. | Système de transmission de données avec synchronisation du temps |
EP0722233A2 (fr) * | 1994-12-21 | 1996-07-17 | Hewlett-Packard Company | Synchronisation dans un réseau de communication de données |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6983161B2 (en) | 1999-09-08 | 2006-01-03 | Nokia Corporation | Method for performing frequency synchronization of a base station and a network part |
US7190963B2 (en) | 1999-09-08 | 2007-03-13 | Nokia Corporation | Method for performing frequency synchronization of a base station and a network part |
CN100452731C (zh) * | 2001-10-18 | 2009-01-14 | 英特尔公司 | 用于同步移动ad-hoc网络中的设备的方法和装置 |
Also Published As
Publication number | Publication date |
---|---|
AU6346199A (en) | 2000-05-29 |
EP1127305A1 (fr) | 2001-08-29 |
JP2002529991A (ja) | 2002-09-10 |
CN1325508A (zh) | 2001-12-05 |
FR2785751A1 (fr) | 2000-05-12 |
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