WO2000025210A9 - Environnement integre de developpement de logiciels et de debogage - Google Patents

Environnement integre de developpement de logiciels et de debogage

Info

Publication number
WO2000025210A9
WO2000025210A9 PCT/US1999/025002 US9925002W WO0025210A9 WO 2000025210 A9 WO2000025210 A9 WO 2000025210A9 US 9925002 W US9925002 W US 9925002W WO 0025210 A9 WO0025210 A9 WO 0025210A9
Authority
WO
WIPO (PCT)
Prior art keywords
interface
workstation
target
based device
processor based
Prior art date
Application number
PCT/US1999/025002
Other languages
English (en)
Other versions
WO2000025210A1 (fr
Inventor
Yogendra Champaklal Shah
Original Assignee
Algorex Inc
Yogendra Champaklal Shah
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Algorex Inc, Yogendra Champaklal Shah filed Critical Algorex Inc
Priority to DE19982342T priority Critical patent/DE19982342T1/de
Priority to KR1020007007037A priority patent/KR20010015893A/ko
Priority to AU21434/00A priority patent/AU2143400A/en
Publication of WO2000025210A1 publication Critical patent/WO2000025210A1/fr
Publication of WO2000025210A9 publication Critical patent/WO2000025210A9/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/20—Software design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/2733—Test interface between tester and unit under test

Definitions

  • the present invention relates to microprocessor-based products. More specifically, the present invention relates to products such as Mobile Terminals, where the system design employs a microprocessor performing software based functions for development and debugging.
  • a set of software development tools is currently available to aid the development of complex software systems. These software tools, which run on a host Development and Debug Workstation, are based upon an object oriented design methodology. This allows software to be debugged from a higher level functional point of view, rather than by analyzing memory based variables, and inferring higher layer software information.
  • MSC Message Sequence Charts
  • FSM Finite State Machines
  • the current method of communication is based upon a variety of communication links, including Ethernet connections and serial ports. These communication link requirements dictate a need for dedicated hardware in the product. However, the product design may not include these peripherals, or it may not be possible to provide these peripherals on the final manufactured product. In these situations, therefore, the above described new generation of software development tools could not be used for product development.
  • ICE (In-Circuit Emulation) port It is an object of the present invention to eliminate the need for Ethernet links, serial ports, or other specifically engineered communication hardware for software development and debugging.
  • a method for interfacing a development and debugging workstation with a microprocessor based device having preexisting diagnostic software comprises the following steps:
  • identifying the type of interface associated with the preexisting diagnostic software in the microprocessor based device such as JTAG
  • FIG 1 shows a block diagram of a development environment, in accordance with the invention.
  • FIG 2 shows a block diagram of an alternative development environment, in accordance with the invention.
  • FIG. 1 a diagram of a development environment is shown in Figure 1.
  • the product under development 100 includes a microprocessor with a JTAG based serial interface. This type of interface can be used to connect a host development platform with a target microprocessor.
  • a JTAG interface cable 105 is connected from product 100 to an interface board 110 on a development workstation 120.
  • Interface board 110 also includes a JTAG interface, which provides workstation development tool 120 with a mechanism for communicating directly with target microprocessor 100.
  • this interface 110 eliminates the need for Ethernet links, serial ports, or any other specifically engineered communication hardware for the software development and debugging process.
  • the software running on target microprocessor 100 allows data to be passed between target microprocessor 100 and development workstation 120.
  • Workstation 120 interprets this data and displays and animates the resultant information visually, by way of Message Sequencing Charts (MSC) and Finite State
  • FSM Machine transitions
  • the present invention is clearly applicable to any form of product in which a microprocessor or digital signal processor (DSP) implements software based instructions.
  • DSP digital signal processor
  • any form of communication mechanism may be employed which allows the capability of transferring data between a development workstation and a product under development.
  • workstation 120 can still communicate with a JTAG interface device even when workstation 120 has a typical Ethernet or serial port interface 130.
  • an interface translator device 140 is added at the input to target hardware 100. This converter device 140 translates data between the workstation Ethernet or serial interface 130 and the target microprocessor 100 JTAG interface.
  • a method and apparatus which enables communication between a development and debugging workstation and a target microprocessor product having a JTAG serial interface. That is, the workstation-to- product communication does not require any dedicated product communication links, such as Ethernet connections or serial ports, to be included in the product.
  • the development and debugging of the product is made more versatile and efficient.
  • the debugging and analysis process is enhanced from the initial prototype stage through final product development.
  • the present invention also enables software to be debugged and analyzed more efficiently, using the new generation of development tools.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Quality & Reliability (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Debugging And Monitoring (AREA)

Abstract

Selon cette invention, un environnement de développement comprend une station de travail de développement (120) et un produit basé sur microprocesseur cible (100) tel qu'un terminal mobile. Les messages de diagnostic circulent entre la station de travail et le microprocesseur grâce à une interface série qui met à profit les capacités du logiciel de diagnostic déjà existant dans le produit basé sur microprocesseur cible. En règle générale, ce logiciel existant comprend un port interface JTAG ou ICE. Si la station de travail est également pourvue d'une interface JTAG, ce port interface élimine le besoin d'avoir des liaisons Ethernet, des ports série ou tout autre matériel de communication spécialement conçu. En revanche, si la station de travail est pourvue d'une interface Ethernet ou d'un port série (130), on connecte entre le produit basé sur microprocesseur cible et l'interface de station de travail un traducteur d'interface (140).
PCT/US1999/025002 1998-10-26 1999-10-25 Environnement integre de developpement de logiciels et de debogage WO2000025210A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE19982342T DE19982342T1 (de) 1998-10-26 1999-10-25 Integrierte Softwareentwicklungs- und Fehlerbeseitigungsumgebung
KR1020007007037A KR20010015893A (ko) 1998-10-26 1999-10-25 통합된 소프트웨어 디벨럽먼트 및 디버그 환경
AU21434/00A AU2143400A (en) 1998-10-26 1999-10-25 Integrated software development and debug environment

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10559698P 1998-10-26 1998-10-26
US60/105,596 1998-10-26

Publications (2)

Publication Number Publication Date
WO2000025210A1 WO2000025210A1 (fr) 2000-05-04
WO2000025210A9 true WO2000025210A9 (fr) 2000-09-28

Family

ID=22306725

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/025002 WO2000025210A1 (fr) 1998-10-26 1999-10-25 Environnement integre de developpement de logiciels et de debogage

Country Status (4)

Country Link
KR (1) KR20010015893A (fr)
AU (1) AU2143400A (fr)
DE (1) DE19982342T1 (fr)
WO (1) WO2000025210A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7539932B2 (en) * 2004-06-17 2009-05-26 International Business Machines Corporation Method and system for debugging Ethernet
KR100619960B1 (ko) * 2004-11-22 2006-09-08 엘지전자 주식회사 인터넷을 통한 디버깅 장치의 원격 제어 장치 및 방법
DE102006030607A1 (de) * 2006-07-03 2008-01-31 Segger Microcontroller Systeme Gmbh Vorrichtung und Verfahren zum Testen eines eingebetteten Systems
JP2008033849A (ja) * 2006-08-01 2008-02-14 Hitachi Ltd 障害解析システム
AU2009230679B2 (en) 2008-03-26 2013-07-18 Advinus Therapeutics Pvt. Ltd. Heterocyclic compounds as adenosine receptor antagonist
US8796290B2 (en) 2009-11-09 2014-08-05 Advinus Therapeutics Limited Substituted fused pyrimidine compounds, its preparation and uses thereof

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5329471A (en) * 1987-06-02 1994-07-12 Texas Instruments Incorporated Emulation devices, systems and methods utilizing state machines
IL100370A (en) * 1990-12-24 1994-11-11 Ball Corp Method for analyzing integrated computer systems
US5425036A (en) * 1992-09-18 1995-06-13 Quickturn Design Systems, Inc. Method and apparatus for debugging reconfigurable emulation systems
US5537536A (en) * 1994-06-21 1996-07-16 Intel Corporation Apparatus and method for debugging electronic components through an in-circuit emulator
US5706297A (en) * 1995-08-24 1998-01-06 Unisys Corporation System for adapting maintenance operations to JTAG and non-JTAG modules
US5812145A (en) * 1995-11-16 1998-09-22 Lucent Technologies Inc. Message sequence chart analyzer
US5724505A (en) * 1996-05-15 1998-03-03 Lucent Technologies Inc. Apparatus and method for real-time program monitoring via a serial interface
US5768152A (en) * 1996-08-28 1998-06-16 International Business Machines Corp. Performance monitoring through JTAG 1149.1 interface

Also Published As

Publication number Publication date
AU2143400A (en) 2000-05-15
DE19982342T1 (de) 2001-03-22
WO2000025210A1 (fr) 2000-05-04
KR20010015893A (ko) 2001-02-26

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