WO2000024048A1 - Procede de gravure de couches structurees utilisees en tant que masque pendant la gravure subsequente ou pour former des structures damasquinees - Google Patents

Procede de gravure de couches structurees utilisees en tant que masque pendant la gravure subsequente ou pour former des structures damasquinees Download PDF

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Publication number
WO2000024048A1
WO2000024048A1 PCT/US1999/023597 US9923597W WO0024048A1 WO 2000024048 A1 WO2000024048 A1 WO 2000024048A1 US 9923597 W US9923597 W US 9923597W WO 0024048 A1 WO0024048 A1 WO 0024048A1
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WO
WIPO (PCT)
Prior art keywords
layer
plasma
pattern
etching
organic
Prior art date
Application number
PCT/US1999/023597
Other languages
English (en)
Inventor
Yan Ye
Pavel Ionov
Allen Zhao
Peter Chang-Lin Hsieh
Diana Xiaobing Ma
Chun Yan
Jie Yuan
Original Assignee
Applied Materials, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/174,763 external-priority patent/US6080529A/en
Application filed by Applied Materials, Inc. filed Critical Applied Materials, Inc.
Priority to JP2000577705A priority Critical patent/JP2003526897A/ja
Priority to KR1020017004916A priority patent/KR20010085939A/ko
Publication of WO2000024048A1 publication Critical patent/WO2000024048A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • ing And Chemical Polishing (AREA)

Abstract

Une première forme de réalisation de la présente invention concerne un procédé qui permet de façonner un motif conducteur de dispositif à semi-conducteur tout en facilitant l'élimination aisée de la couche de masquage résiduelle qui reste après la fin du processus de gravure. On utilise une structure de masquage à plusieurs couches qui comprend une couche de matériau (220) de masquage à base organique haute température qui est recouverte par une couche structurée de matériau (222) de masquage inorganique ou par une couche de matériau de masquage organique haute température structurée formant des images. Le matériau de masquage inorganique est utilisé pour transférer un motif sur le matériau de masquage à base organique haute température puis on l'enlève. Le matériau de masquage à base organique haute température est utilisé pour transférer le motif et peut ensuite être éliminé si besoin. Ce procédé est également utile pour graver des motifs sur de l'aluminium, même si l'aluminium peut être gravé à des températures plus basses. Une deuxième forme de réalisation de l'invention concerne une chimie de gravure spécialisée utile pour structurer des couches polymères organiques telles que des diélectriques à faible k, ou d'autres couches interfaciales organiques polymères. Cette chimie de gravure est utile pour effectuer l'ouverture du masque pendant la gravure d'une couche conductrice ou pour graver des structures damasquinées dans lesquelles une couche de remplissage métallique est appliquée sur la surface d'une couche diélectrique à base organique structurée. La chimie de gravure prévoit l'utilisation d'une espèce de plasma d'agent de gravure qui réduit au maximum la teneur en oxygène, fluor, chlore et brome.
PCT/US1999/023597 1997-12-12 1999-10-08 Procede de gravure de couches structurees utilisees en tant que masque pendant la gravure subsequente ou pour former des structures damasquinees WO2000024048A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000577705A JP2003526897A (ja) 1998-10-19 1999-10-08 後続のエッチング中のマスキングとして有用な、またはダマシン構造に有用な、パターニングされた層のエッチング方法
KR1020017004916A KR20010085939A (ko) 1997-12-12 1999-10-08 에칭 처리 단계에서 마스킹으로서 사용될 수 있는패턴화된 층을 에칭하는 방법 또는 다마신 구조

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/174,763 US6080529A (en) 1997-12-12 1998-10-19 Method of etching patterned layers useful as masking during subsequent etching or for damascene structures
US09/174,763 1998-10-19
PCT/US1998/025699 WO1999031718A1 (fr) 1997-12-12 1998-12-04 Procede de gravure a haute temperature de couches a motifs a l'aide d'un empilement de couches organiques de masquage
USPCT/US98/25699 1998-12-04

Publications (1)

Publication Number Publication Date
WO2000024048A1 true WO2000024048A1 (fr) 2000-04-27

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Application Number Title Priority Date Filing Date
PCT/US1999/023597 WO2000024048A1 (fr) 1997-12-12 1999-10-08 Procede de gravure de couches structurees utilisees en tant que masque pendant la gravure subsequente ou pour former des structures damasquinees

Country Status (2)

Country Link
JP (1) JP2003526897A (fr)
WO (1) WO2000024048A1 (fr)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002065530A2 (fr) * 2001-02-12 2002-08-22 Lam Research Corporation Utilisation d'additifs d'hydrocarbures pour eliminer les micromasquages lors de l'attaque de dielectriques organiques a faible k
WO2004068155A1 (fr) * 2003-01-27 2004-08-12 Agilent Technologies, Inc. Dispositif de sonde et appareil d'essai d'un substrat d'affichage utilisant ladite sonde
US6777344B2 (en) 2001-02-12 2004-08-17 Lam Research Corporation Post-etch photoresist strip with O2 and NH3 for organosilicate glass low-K dielectric etch applications
DE10330795A1 (de) * 2003-07-08 2005-02-17 Infineon Technologies Ag Kohlenstoff-Hartmaske mit haftfähiger Schicht zur Haftung auf Metall
JP2006512783A (ja) * 2002-12-23 2006-04-13 東京エレクトロン株式会社 ２層フォトレジストのドライ現像方法及び装置
US7141508B2 (en) 2001-08-08 2006-11-28 Tdk Corporation Magnetoresistive effect thin-film magnetic head and manufacturing method of magnetoresistive effect thin-film magnetic head
US7785484B2 (en) 2007-08-20 2010-08-31 Lam Research Corporation Mask trimming with ARL etch
WO2010119263A1 (fr) * 2009-04-17 2010-10-21 Surrey Nanosystems Limited Matériau ayant une faible constante diélectrique et son procédé de fabrication
US8101025B2 (en) 2003-05-27 2012-01-24 Applied Materials, Inc. Method for controlling corrosion of a substrate
JP2014150268A (ja) * 2002-10-31 2014-08-21 Applied Materials Inc シリコン含有ハードマスクをエッチングする方法
TWI745789B (zh) 2018-11-30 2021-11-11 台灣積體電路製造股份有限公司 半導體裝置及其製造方法
US11177177B2 (en) 2018-11-30 2021-11-16 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and method of manufacture

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4800077B2 (ja) * 2006-03-17 2011-10-26 東京エレクトロン株式会社 プラズマエッチング方法
JP4745273B2 (ja) * 2006-09-25 2011-08-10 株式会社東芝 半導体装置の製造方法及び半導体製造装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4528066A (en) * 1984-07-06 1985-07-09 Ibm Corporation Selective anisotropic reactive ion etching process for polysilicide composite structures
EP0296707A1 (fr) * 1987-06-12 1988-12-28 Hewlett-Packard Company Incorporation d'une couche diélectrique dans une structure semi-conductrice
US5230772A (en) * 1990-07-27 1993-07-27 Sony Corporation Dry etching method
US5346586A (en) * 1992-12-23 1994-09-13 Micron Semiconductor, Inc. Method for selectively etching polysilicon to gate oxide using an insitu ozone photoresist strip

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4528066A (en) * 1984-07-06 1985-07-09 Ibm Corporation Selective anisotropic reactive ion etching process for polysilicide composite structures
EP0296707A1 (fr) * 1987-06-12 1988-12-28 Hewlett-Packard Company Incorporation d'une couche diélectrique dans une structure semi-conductrice
US5230772A (en) * 1990-07-27 1993-07-27 Sony Corporation Dry etching method
US5346586A (en) * 1992-12-23 1994-09-13 Micron Semiconductor, Inc. Method for selectively etching polysilicon to gate oxide using an insitu ozone photoresist strip

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BAKLANOV M R, VANHAELEMEERSCH S, ALAERTS C, MAEX K: "Plasma etching of organic low-dielectric- constant polymers: comparative analysis", MATER. RES. SOC. SYMP. PROC., vol. 511, 1998, pages 247 - 252, XP000874697 *

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002065530A3 (fr) * 2001-02-12 2003-05-15 Lam Res Corp Utilisation d'additifs d'hydrocarbures pour eliminer les micromasquages lors de l'attaque de dielectriques organiques a faible k
US6620733B2 (en) 2001-02-12 2003-09-16 Lam Research Corporation Use of hydrocarbon addition for the elimination of micromasking during etching of organic low-k dielectrics
US6777344B2 (en) 2001-02-12 2004-08-17 Lam Research Corporation Post-etch photoresist strip with O2 and NH3 for organosilicate glass low-K dielectric etch applications
WO2002065530A2 (fr) * 2001-02-12 2002-08-22 Lam Research Corporation Utilisation d'additifs d'hydrocarbures pour eliminer les micromasquages lors de l'attaque de dielectriques organiques a faible k
US7141508B2 (en) 2001-08-08 2006-11-28 Tdk Corporation Magnetoresistive effect thin-film magnetic head and manufacturing method of magnetoresistive effect thin-film magnetic head
JP2014150268A (ja) * 2002-10-31 2014-08-21 Applied Materials Inc シリコン含有ハードマスクをエッチングする方法
JP2006512783A (ja) * 2002-12-23 2006-04-13 東京エレクトロン株式会社 ２層フォトレジストのドライ現像方法及び装置
US7151384B2 (en) 2003-01-27 2006-12-19 Agilent Technologies, Inc. Probe device and display substrate testing apparatus using same
WO2004068155A1 (fr) * 2003-01-27 2004-08-12 Agilent Technologies, Inc. Dispositif de sonde et appareil d'essai d'un substrat d'affichage utilisant ladite sonde
US8101025B2 (en) 2003-05-27 2012-01-24 Applied Materials, Inc. Method for controlling corrosion of a substrate
DE10330795A1 (de) * 2003-07-08 2005-02-17 Infineon Technologies Ag Kohlenstoff-Hartmaske mit haftfähiger Schicht zur Haftung auf Metall
DE10330795B4 (de) * 2003-07-08 2008-01-24 Qimonda Ag Kohlenstoff-Hartmaske mit einer Stickstoff-dotierten Kohlenstoffschicht als haftfähiger Schicht zur Haftung auf Metall oder metallhaltigen anorganischen Materialien und Verfahren zu deren Herstellung
US7785484B2 (en) 2007-08-20 2010-08-31 Lam Research Corporation Mask trimming with ARL etch
WO2010119263A1 (fr) * 2009-04-17 2010-10-21 Surrey Nanosystems Limited Matériau ayant une faible constante diélectrique et son procédé de fabrication
CN102448996A (zh) * 2009-04-17 2012-05-09 萨里纳米系统有限公司 具有低介电常数的材料及其制造方法
TWI745789B (zh) 2018-11-30 2021-11-11 台灣積體電路製造股份有限公司 半導體裝置及其製造方法
US11177177B2 (en) 2018-11-30 2021-11-16 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and method of manufacture

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Publication number Publication date
JP2003526897A (ja) 2003-09-09

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