WO1999059047A3 - Method and apparatus for low jitter clock recovery - Google Patents

Method and apparatus for low jitter clock recovery Download PDF

Info

Publication number
WO1999059047A3
WO1999059047A3 PCT/US1999/010226 US9910226W WO9959047A3 WO 1999059047 A3 WO1999059047 A3 WO 1999059047A3 US 9910226 W US9910226 W US 9910226W WO 9959047 A3 WO9959047 A3 WO 9959047A3
Authority
WO
WIPO (PCT)
Prior art keywords
cycle
jitter
reduced
noise
phy
Prior art date
Application number
PCT/US1999/010226
Other languages
French (fr)
Other versions
WO1999059047A2 (en
Inventor
Robert W Moses
Allen R Goldstein
Original Assignee
Digital Harmony Technologies L
Robert W Moses
Allen R Goldstein
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Harmony Technologies L, Robert W Moses, Allen R Goldstein filed Critical Digital Harmony Technologies L
Priority to EP99921837A priority Critical patent/EP1076846A2/en
Priority to CA002330970A priority patent/CA2330970A1/en
Priority to JP2000548791A priority patent/JP2002514876A/en
Priority to AU38946/99A priority patent/AU3894699A/en
Publication of WO1999059047A2 publication Critical patent/WO1999059047A2/en
Publication of WO1999059047A3 publication Critical patent/WO1999059047A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40052—High-speed IEEE 1394 serial bus
    • H04L12/40058—Isochronous transmission
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/24—Loading of the microprogram
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40052—High-speed IEEE 1394 serial bus
    • H04L12/40117—Interconnection of audio or video/imaging devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
    • H04N21/4363—Adapting the video stream to a specific local network, e.g. a Bluetooth® network
    • H04N21/43632—Adapting the video stream to a specific local network, e.g. a Bluetooth® network involving a wired protocol, e.g. IEEE 1394

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Software Systems (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stored Programmes (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Picture Signal Circuits (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)
  • Digital Computer Display Output (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

A method and apparatus is described for reducing jitter in data sample clock rates recovered from isochronous streams of data packets having associated time stamp values, such as in an IEEE 1394 bus-interconnected system. Jitter associated with variations in the free running quartz-driven PHY clocks is reduced by instead driving local PHY clocks with a phase-locked loop circuit referenced to the Link cycle-out pin, which toggles when the cycle time register cycle-offset field wraps and the cycle-count field increments. Because the cycle-out pin toggles at a frequency proportional to the cycle master's PHY clock, jitter associated with local PHY clock variations is reduced. Jitter associated with quatization noise from finite length time stamp generation is reduced by dithering and noise shape filtering conventional time stamps. This decorrelates the jitter and shifts the associated noise out of the expected frequency band of the sample clock signal to be recovered.
PCT/US1999/010226 1998-05-11 1999-05-11 Method and apparatus for low jitter clock recovery WO1999059047A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP99921837A EP1076846A2 (en) 1998-05-11 1999-05-11 Method and apparatus for low jitter clock recovery
CA002330970A CA2330970A1 (en) 1998-05-11 1999-05-11 Method and apparatus for low jitter clock recovery
JP2000548791A JP2002514876A (en) 1998-05-11 1999-05-11 Method and apparatus for low jitter clock recovery
AU38946/99A AU3894699A (en) 1998-05-11 1999-05-11 Method and apparatus for low jitter clock recovery

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US8502198P 1998-05-11 1998-05-11
US60/085,021 1998-05-11

Publications (2)

Publication Number Publication Date
WO1999059047A2 WO1999059047A2 (en) 1999-11-18
WO1999059047A3 true WO1999059047A3 (en) 2000-04-06

Family

ID=22188925

Family Applications (4)

Application Number Title Priority Date Filing Date
PCT/US1999/010255 WO1999059060A2 (en) 1998-05-11 1999-05-10 Method and system for distributing processing instructions with adata to be processed
PCT/US1999/010226 WO1999059047A2 (en) 1998-05-11 1999-05-11 Method and apparatus for low jitter clock recovery
PCT/US1999/010225 WO1999059391A2 (en) 1998-05-11 1999-05-11 Method and apparatus for data sample clock recovery
PCT/US1999/010224 WO1999059073A2 (en) 1998-05-11 1999-05-11 Method and system for providing an appliance user interface

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/US1999/010255 WO1999059060A2 (en) 1998-05-11 1999-05-10 Method and system for distributing processing instructions with adata to be processed

Family Applications After (2)

Application Number Title Priority Date Filing Date
PCT/US1999/010225 WO1999059391A2 (en) 1998-05-11 1999-05-11 Method and apparatus for data sample clock recovery
PCT/US1999/010224 WO1999059073A2 (en) 1998-05-11 1999-05-11 Method and system for providing an appliance user interface

Country Status (5)

Country Link
EP (4) EP1076850A2 (en)
JP (4) JP2002514810A (en)
AU (4) AU3897099A (en)
CA (4) CA2330739A1 (en)
WO (4) WO1999059060A2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3424620B2 (en) * 1999-09-24 2003-07-07 日本電気株式会社 Isochronous packet transfer method, recording medium for transfer control program, bridge, and packet transfer control LSI
US6895009B1 (en) 2000-04-07 2005-05-17 Omneon Video Networks Method of generating timestamps for isochronous data
EP1198085B1 (en) 2000-10-10 2011-06-08 Sony Deutschland GmbH Cycle synchronization between interconnected sub-networks
DE10104876A1 (en) * 2001-02-03 2002-08-08 Bosch Gmbh Robert Circuit arrangement and method for the synchronized transmission of audio data streams in a bus system
DE10229372A1 (en) * 2002-06-29 2004-01-15 Deutsche Thomson-Brandt Gmbh Data transmitter, especially for OSI/SO 7-layer model data security layer, has time marker allocation unit that allocates generated time marker to current data packet or data packet to be generated
TWI347092B (en) 2006-04-11 2011-08-11 Realtek Semiconductor Corp Methods for adjusting sampling clock of sampling circuit and related apparatuses
GB2449932A (en) 2007-06-08 2008-12-10 Tandberg Television Asa Timestamp conversion using samples
US7936794B2 (en) * 2007-08-07 2011-05-03 Avaya Inc. Clock management between two end points
GB2514572B (en) 2013-05-29 2020-05-27 Grass Valley Ltd Re-timing sampled data
CN106933212B (en) * 2017-04-21 2019-12-10 华南理工大学 reconfigurable industrial robot programming control method in distributed manufacturing environment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0695063A2 (en) * 1994-07-25 1996-01-31 Sony Corporation Packet transmission system
US5526362A (en) * 1994-03-31 1996-06-11 Telco Systems, Inc. Control of receiver station timing for time-stamped data
EP0838926A2 (en) * 1996-10-22 1998-04-29 Sony Corporation Apparatus and method for transmitting and receiving isochronous data

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2645989A1 (en) * 1989-04-17 1990-10-19 Bull Sa MULTIFUNCTION COUPLER BETWEEN A CENTRAL COMPUTER UNIT AND THE DIFFERENT PERIPHERAL ORGANS OF THE SAME
DE69021732T2 (en) * 1990-12-04 1996-01-18 Hewlett Packard Ltd Reprogrammable data storage system.
JP2937529B2 (en) * 1991-03-27 1999-08-23 日本電気株式会社 Clock recovery circuit
US5635979A (en) * 1994-05-27 1997-06-03 Bell Atlantic Dynamically programmable digital entertainment terminal using downloaded software to control broadband data operations
US5901149A (en) * 1994-11-09 1999-05-04 Sony Corporation Decode and encode system
US6067500A (en) * 1995-08-14 2000-05-23 Aisin Aw Co., Ltd. Navigation system
DE69735415T2 (en) * 1996-05-07 2006-09-28 Yamaha Corp., Hamamatsu Method and system for transmitting audio data with time stamp
US5922050A (en) * 1996-07-02 1999-07-13 Sun Microsystems, Inc. Method and apparatus for controlling a device on a network

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5526362A (en) * 1994-03-31 1996-06-11 Telco Systems, Inc. Control of receiver station timing for time-stamped data
EP0695063A2 (en) * 1994-07-25 1996-01-31 Sony Corporation Packet transmission system
EP0838926A2 (en) * 1996-10-22 1998-04-29 Sony Corporation Apparatus and method for transmitting and receiving isochronous data

Also Published As

Publication number Publication date
JP2002514876A (en) 2002-05-21
CA2330739A1 (en) 1999-11-18
WO1999059047A2 (en) 1999-11-18
JP2002515718A (en) 2002-05-28
CA2330970A1 (en) 1999-11-18
EP1076846A2 (en) 2001-02-21
WO1999059060A2 (en) 1999-11-18
CA2330740A1 (en) 1999-11-18
AU3792299A (en) 1999-11-29
AU3894699A (en) 1999-11-29
AU3792199A (en) 1999-11-29
WO1999059073A9 (en) 2001-05-31
EP1076858A2 (en) 2001-02-21
CA2330676A1 (en) 1999-11-18
WO1999059060A3 (en) 1999-12-29
AU3897099A (en) 1999-11-29
WO1999059073A2 (en) 1999-11-18
WO1999059391A3 (en) 2001-03-22
EP1076850A2 (en) 2001-02-21
EP1101303A2 (en) 2001-05-23
WO1999059391A2 (en) 1999-11-18
WO1999059073A3 (en) 1999-12-29
JP2002514810A (en) 2002-05-21
JP2002514820A (en) 2002-05-21

Similar Documents

Publication Publication Date Title
JP3895544B2 (en) System and method for high speed synchronous data communication
US7453958B2 (en) Method and device for extracting a clock frequency underlying a data stream
WO1999059047A3 (en) Method and apparatus for low jitter clock recovery
EP1553716A8 (en) Apparatus and method for synchronizing an SCDMA upstream or any other type upstream to an MCNS downstream or any other type downstream with a different clock rate than the upstream
WO2004025417A3 (en) Clock recovery method for bursty communications
JP2000099485A5 (en)
WO2001095552A3 (en) High frequency network receiver
CA2146801A1 (en) Timing Recovery for Variable Bit-Rate Video on Asynchronous Transfer Mode (ATM) Networks
US7639769B2 (en) Method and apparatus for providing synchronization in a communication system
JP2003526984A (en) Data clock recovery circuit
WO2001078275A3 (en) Clock recovery in a packet-based data network
GB2271492A (en) Apparatus for and method of synchronizing a clock signal
GB2353618A (en) Multiple synthesizer based timing signal generation scheme
WO2002014790A3 (en) Cmi signal timing recovery
WO2003032540A3 (en) Method and apparatus for digital data synchronization
EP0360691A3 (en) Apparatus for receiving digital signal
WO1998052284A3 (en) Phase detector arrangement
WO2002015449A3 (en) Method and system for transmitting isochronous voice in a wireless network
JP3087259B2 (en) Flash NRZI modulator and modulation method
US7486121B2 (en) System and method for generating two effective frequencies using a single clock
CA2181194A1 (en) Transmission of high rate isochronous data in mpeg-2 data streams
EP0720319A3 (en) Clock recovery extrapolation
AU2001290445A1 (en) An arrangement for capturing data
JPS5923496B2 (en) Timing extraction method
WO2003049292A3 (en) Single-chip digital phase frequency synthesiser

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW SD SL SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW SD SL SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
ENP Entry into the national phase

Ref document number: 2330970

Country of ref document: CA

WWE Wipo information: entry into national phase

Ref document number: 1999921837

Country of ref document: EP

Ref document number: IN/PCT/2000/00608/MU

Country of ref document: IN

NENP Non-entry into the national phase

Ref country code: KR

ENP Entry into the national phase

Ref document number: 2000 548791

Country of ref document: JP

Kind code of ref document: A

WWP Wipo information: published in national office

Ref document number: 1999921837

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

WWR Wipo information: refused in national office

Ref document number: 1999921837

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 1999921837

Country of ref document: EP