JP2002515718A - Method and apparatus for recovering a data sample clock - Google Patents

Abstract

SUMMARY A method and apparatus for recovering a data sample clock rate from an isochronous stream of data packets received and containing an associated time stamp value, such as in an IEEE 1394 bus interconnect system, is described. The difference between successive timestamp values is determined by successively latching the timestamp values and applying them to a subtractor circuit to generate a difference value. This difference value is then continuously decremented by the down counter, which then generates a signal pulse and loads the next difference value when the count is complete. The pulsed signal is applied to a phase locked loop to provide a frequency multiple to correspondingly generate a clock signal having a frequency proportional to the difference between successive time stamp values. It is also possible to monitor the data input buffer level and adjust the clock signal frequency accordingly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001] The present invention relates to US patent application Ser. No. 60/085021 filed May 11, 1998, the disclosure of which is incorporated herein by reference.

TECHNICAL FIELD [0002] The present invention relates generally to bus system architectures, and more particularly, to a method and apparatus for recovering a received data sample clock rate.

BACKGROUND [0003] Today's consumer electronic devices are increasingly being implemented as dedicated computer systems complete with processors, memory, and I / O functions. The various companies that design and manufacture these devices may have their own specific interconnect technologies and communication protocols. Thus, compatibility issues can arise when connecting devices made by different manufacturers. For example, in a home entertainment system, a DVD player manufactured by one company may not be compatible with an audio speaker subsystem manufactured by another company.

[0004] Various standards have been developed to facilitate today's increasingly complex communication between electronic devices. In particular, the IEEE 1394 standard for high performance serial buses (also known as "FireWire buses") has been established to facilitate the development of compatible consumer electronic devices. The FireWire bus architecture allows for standard connections in addition to defining a standard bus communication protocol so that each interconnected device does not require separate point-to-point connections between the various devices. , Can communicate with any such other device.
IEEE 1394 standards (IEEE 1394-1995 and IEEE 1394a
Supplement) is "Standard for High Performance"
Serial Bus "and" Information tec
hnology-Microprocessor systems-Contr
ol and Status Registers (CSR) Architectec
I for the name "ture for microcomputer buses"
Based on SO / IEC13213 (ANSI / IEEE1212) specification.

Referring to FIG. 1, a typical home entertainment system 100 is shown. The system includes a high-speed bus such as an IEEE 1394 bus 102 that interconnects various electronic devices. The particular arrangement shown is merely to illustrate the functional interconnection of representative devices. One skilled in the art will appreciate that the FireWire bus architecture supports tree and daisy chain configurations.

[0006] Included is a DVD player 104 for playing DVD discs and correspondingly outputting an audio / MPEG video data stream on a 1394 bus 102. Audio / isochronous channels on the 1394 bus 102
A video data stream is carried, a surround sound decoder 106 receives the audio data stream, and a video decoder / monitor 108 receives the MPEG video data stream. Cable or satellite set-top box 11
0 receives media from a cable or satellite television provider and transmits the corresponding audio and MPEG video data streams to the 1394 bus 102.
Output on the isochronous channel. Surround decoder 106 receives audio data, and video decoder / monitor 108 receives video data.

[0007] The surround sound decoder 106 receives a compressed audio signal from another device connected to the 1394 bus 102, and decodes the audio. Then
The decoded audio data is output to the amplifier / speaker subsystem 112 on the 1394 bus 102. Video decoder / monitor 108 is 1394 bus 1
02 decodes MPEG data streams received from various video source devices. After being decoded, the decompressed video signal is typically output to a video monitor for display.

[0008] Controller 114 provides a control point for all devices in system 100. The controller 114 may also provide a user interface for configuring the system as various devices are added or removed. The controller typically includes a user interface, such as on a set-top box 110, for adjusting audio volume, turning devices on and off, selecting channels, and the like. In fact, the controller may be the only device with which the user interacts (other than inserting a disc into the DVD player 104).

Each interconnected device shown in system 100 of FIG. 1 includes an interface circuit that connects 1394 bus 102 to specific application circuits included in the device. Such interface circuits include both physical electronic connections (known as the PHY layer) and data format conversion interfaces (known as the link layer). Such interface circuits are well known to those skilled in the art, and the general function of such a circuit need not be described herein.

[0010] For video / audio applications that require a constant data rate, it is especially important that the device receiving such data accurately recover the sample rate clock signal from the device sending such data. is important. This ensures that data buffers in the system do not overflow or underflow. The FireWire bus architecture is based on the Digital I
interface for Consumer Audio / Video Eq
Supports transmission of isochronous data packets containing timestamp information that can be used to recover the sample rate clock, such as in accordance with the IEC 61883 standard, named "upload" Since the different data streams need not be related in frequency (ie, the isochronous stream may have a free running sample rate), each receiver or node must have a separate 1394 bus for each receive isochronous channel. Separate clock recovery circuits must be implemented.

Referring to FIG. 2, a prior art approach to providing a time stamp and correspondingly recovering the sample rate clock is shown in a functional block diagram. The interface circuit included in the transmitter or node 200 is shown as part of the interface circuit included in the receiver or node 202. The transmission node 200 includes a latch 204 that latches a lower part of a value stored in a cycle time register 206 included in a link layer of the interface circuit. The latch 204 latches a cycle time value every predetermined number of cycles of a sample rate clock (such as a digital audio word clock in the case of audio data transmission). The transfer delay value is added to the latched cycle time register value, and the obtained time stamp is inserted into the header of the corresponding isochronous data packet 208. As known to those skilled in the art, the value of the transfer delay is determined at the time of system initialization or bus reset.

At the receiving device or node 202, the received time stamp is compared to the corresponding lower part of the value stored in the receiving node's cycle time register 210. Comparator 212 generates a pulse signal if equal, which then
Phase locked loop (PLL) circuit 2 to recover sample rate clock signal
14 is input.

The particular approach shown in FIG. 2 has several disadvantages. If the stream of timestamps is interrupted for any reason, such as during a bus reset, the pulse signal generated by comparator 212 will experience dropout and
L214 temporarily loses lock and glitches in the sample rate clock signal (
glitch). If the isochronous data packets are so late that their time stamps lead to the value stored in the local cycle time register 210 of the receiving node 214, the time stamp period completes before the comparator 212 can detect an equal match. One complete cycle (about 2 milliseconds) should have elapsed. This then causes an error when the audio data is presented. Further, many devices, such as personal computers, have difficulty maintaining the high accuracy required to generate and process timestamps in the manner described above with respect to FIG.

Overview According to the present invention, there is provided a method of recovering a data sample rate from a stream of data packets having a corresponding timestamp value. The method includes determining a difference between successive time stamp values, and then generating a clock signal having a frequency substantially proportional to the determined difference between successive time stamp values. Determining the difference between successive time stamp values latches the first and second time stamp values and then subtracts the first time stamp value from the second time stamp value to generate a difference value. Can be included. Here, generating the clock signal can include continuously decrementing the difference value until the decremented value reaches a predetermined minimum value, at which time the signal pulse is generated. Is generated. In this case, the frequency of the generated clock signal is made to be proportional to the frequency of the signal pulse.

According to another aspect of the present invention, there is provided a circuit for recovering a data sample rate from a stream of data packets having a corresponding timestamp value.
The circuit includes first and second latches for latching first and second timestamp values, respectively. A subtractor circuit generates a difference value corresponding to the difference between the first and second time stamp values. A down counter continuously decrements the value of the difference and generates a signal pulse when the decremented value is equal to a predetermined minimum value. A phase locked loop receives the signal pulse and generates a clock signal having a frequency proportional to the frequency of the signal pulse in response.

DETAILED DESCRIPTION The following is a description of a circuit and method for recovering a data sample clock from an isochronous data packet stream.

The circuit and method are based on the appropriate IEEE 1394, ISO / IEC 13213
, And IEC61883 standards. In this description, certain details are set forth in order to provide a thorough understanding of various embodiments of the invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these details. In other instances, well-known circuits, circuit components, control signals, timing protocols and communication protocols have not been shown in detail in order to avoid unnecessarily obscuring the description of various embodiments of the invention. Or not explained. The subject to be described is "Method
and Apparatus for Low Jitter Clock
This disclosure is hereby incorporated by reference with respect to technology similar to that disclosed in the co-pending patent application entitled "Recovery."

FIG. 3 illustrates certain circuits included in the link layer 300 of the interface circuit that couples the 1394 bus 102 to the application host 302. This figure also shows the physical / electronic interface or PHY layer 304. The specific circuit shown in link layer 300 is a simplified representation of the data path for the received isochronous data, along with some associated control / monitoring circuits. A wide variety of circuits are not shown in FIG. 3, including bus management layer circuits, transaction layer circuits, data path / control circuits for transmitted isochronous data, and other link layer circuits associated with asynchronous data protocols. Will be understood by those skilled in the art. Such well-known circuits are not shown to avoid unnecessarily obscuring embodiments of the present invention.

The link layer circuit 300 includes a FIFO 306 for receiving an arriving isochronous data packet, such as an audio data packet. These data packets are passed to a packet parser 308, which separates the audio data from the header of the packet including the time stamp. The audio data is then passed to another FIFO 310 and then to the digital audio interface 3
12 to the application host 302.

The packet parser 308 provides a timestamp value from the isochronous data packet to the sample clock recovery circuit 314. A fill level monitoring circuit 316 monitors the fill level of the packet FIFO 306 and, in response, asserts a fill control signal applied to the sample clock recovery circuit 314. The sample clock recovery circuit 314 generates a sample rate clock signal and a fill control signal corresponding to the received time stamp. This clock signal is applied to a clock generator circuit 318, which provides various known clocking signals that are applied to digital audio interface 312.

With the exception of the clock recovery circuit 314 described further below, the circuits described with respect to FIG. 3 are of a type well known in the art. Those skilled in the art will be able to implement the invention by implementing such circuits or their equivalents in the described or equivalent configurations. Therefore, it is not necessary to provide details of the interior and operation of such a circuit.

FIG. 4 shows certain internal details of the sample clock recovery circuit 314 included in the link layer circuit 300 of FIG. The arrival time stamp passes through a series of two latches 404 and 406. The output of latch 404 and the output of latch 406 are applied to subtraction circuit 408. Subtraction circuit 408 includes latches 404 and 406
To provide the difference value for loading into the down counter 410. In this case, this difference value corresponds to the difference between successive timestamps received by the sample clock rate recovery circuit 314. One skilled in the art will recognize that a series of N latches or other circuits can also be adapted to determine the value of the average difference over the N isochronous cycles, thereby reducing the rounding error of the timestamp. You will understand.

The down counter 410 is clocked by the same 24.576 MHz clock signal that increments the cycle time registers 206, 210 of FIG. Down counter 410 generates a pulse when it reaches zero (or other predetermined minimum value) and loads the next difference value provided by subtraction circuit 308. Accordingly, the pulsed signal generated by down counter 410 has a frequency proportional to the difference between successive timestamps received by sample clock rate recovery circuit 314. This pulsed signal is then input to a phase locked loop 412 having substantially the same configuration as the phase locked loop 214 shown in FIG. 2, and the sample rate clock is correspondingly recovered. One skilled in the art will appreciate that an up counter or other circuit may be adapted and may substitute for the down counter 410 described. More generally, the down counter can be replaced by a suitably adapted circuit that continuously modifies the difference value until a predetermined value is reached, and generates a pulse when it is reached. .

In addition, a “nudge” control input provides an addition or subtraction to the value output by the subtraction circuit 408. The nudge control input can receive the aforementioned fill control signal or other signals derived therefrom. The resulting sample rate clock signal is then nudged up or down from that otherwise normal rate by adjusting the value of the difference generated by the subtraction circuit 408. The sample rate can then be adjusted up or down to maintain the proper fill level of the packet FIFO 306 (see FIG. 3). In this case, this will accommodate any errors due to missing or incorrect time stamps and will help alleviate prior art problems associated with poorly generated timestamps from devices such as personal computers.

FIG. 5 shows an alternative circuit configuration of the circuit configuration shown in FIG. In this configuration, the subtraction circuit 502 calculates the difference between successive timestamps. The difference value generated by the subtraction circuit 502 is stored in a difference register 504 and a difference accumulator.
ator) 506. Difference register 504 stores the initial difference between successive timestamps and provides this constant input to down counter 508, which pulses PLL 412 in a manner similar to that described above with respect to FIG. Signal. By loading the down counter 508 with a constant value,
The PLL 412 removes jitter based on a fixed frequency signal.

To compensate for variations in received timestamp differences, accumulator 506
Keeps the running total of the differences (ie, the difference sum of the timestamp differences). When the sum exceeds a first predetermined threshold or falls below a second predetermined threshold, accumulator 506 sends a corresponding nudge signal to down counter 508. Add. The down counter 508 then raises or lowers the value of the next loaded difference by one and adjusts accordingly, and correspondingly, the PLL4
12 modifies the frequency of the pulsed signal applied. As discussed above with respect to FIG. 3, input buffer monitoring may still be employed, and the circuit of FIG. 5 is adapted to allow such additional nudge functions.

The foregoing embodiments of the present invention provide several advantages over the prior art. If the time stamp is interrupted for any reason, the difference of the last calculated time stamp is retained, so that a new pulse can be continuously calculated by the down counter 410. This results in a clock frequency very close to the actual rate, which avoids glitches on the sample rate clock until the arrival timestamp resumes. The nudge function can also be used to keep the phase locked loop 412 locked even when there is no arrival timestamp. By monitoring the FIFO fill level and adjusting the nudge control to maintain a constant fill level, a sample rate clock signal can be provided without a future arrival timestamp value. In fact, it is also possible to use the time stamp first as a coarse control value at the beginning of the data transfer, and then the nudge function drives the sample rate clock frequency to maintain a substantially constant FIFO fill level.

If the difference between the time stamps is constant (such as when the sample rate and the frequency of the 1394 bus clock (24.576 MHz) are an exact integer ratio), the time stamp difference is calculated once. It is then sufficient to use this difference successively. Thus, the receiving node does not need to continuously monitor the time stamp for more than the first few packets. In fact, the sending node may simply send two timestamps and then stop sending the timestamps with subsequent data packets.

Each of the circuits described above with respect to FIGS. 4 and 5 is of a type well known in the art. Those skilled in the art will be able to implement such circuits or their equivalents in the described or equivalent configurations to practice the invention. Therefore, it is not necessary to provide details of the interior and operation of such a circuit.

While specific embodiments of the present invention have been described above for purposes of illustration, it will be appreciated that various modifications can be made to these embodiments without departing from the spirit and scope of the present invention. It will be understood from this. Although the discussion is primarily directed to recovering the sample clock for audio data in systems based on the IEEE 1394 bus, the inventive teachings are also applicable to other isochronous communications. Those skilled in the art will appreciate that the data sample rate clock signal can be recovered by determining the difference between the timestamp values, regardless of the wide variety of circuit topologies employed. Also, many of the functions of the above-described circuit embodiments may alternatively be performed in software. Indeed, numerous modifications are properly within the scope of the invention, and the invention is not limited except as by the appended claims.

[Brief description of the drawings]

FIG. 1 is a functional block diagram illustrating a typical IEEE 1394 system.

FIG. 2 is a functional block diagram showing a circuit for generating a time stamp by a transmitting device in an IEEE 1394 system and a circuit for recovering a sample rate clock in a prior art receiving device.

FIG. 3 is a functional block diagram illustrating an isochronous data path received through an interface circuit according to one embodiment of the present invention.

FIG. 4 for recovering a sample rate clock signal according to one embodiment of the present invention;
FIG. 4 is a functional block diagram illustrating a circuit included in the interface of FIG. 3.

FIG. 5 is a functional block diagram illustrating circuits included in the interface of FIG. 3 for recovering a sample rate clock signal, according to another embodiment of the present invention.

[Procedural Amendment] Submission of translation of Article 34 Amendment of the Patent Cooperation Treaty

[Submission date] June 13, 2000 (2000.6.13)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

──────────────────────────────────────────────────続 き Continuation of front page (81) Designated country EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE ), OA (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, KE, LS, MW, SD, SL, SZ, UG, ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY , CA, CH, CN, CU, CZ, DE, DK, EE, ES, FI, GB, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE , KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, UA, UG, US, UZ, VN, YU, ZA, ZW (72) Inventor Goldstein Allen R. United States 98199 Seattle, Washington 39 Avenue West 2605 (72) Inventor Car Brian Dee. United States 98109 Seattle, Washington Seattle Garfield Street Number 502 766 F-term (reference) 5C021 PA26 PA28 PA66 PA78 PA87 RC06 SA08 YA02 5K028 AA01 EE03 EE08 KK01 KK03 NN32 SS26 SS28 5K047 AA01 CC11 DD01 DD02 GG07 MM46 MM46 MM26MM

Claims (22)

[Claims] 1. A method for recovering a data sample rate from a stream of data packets including an associated timestamp value, the method comprising: determining a difference between first and second timestamp values; Generating a clock signal having a frequency substantially proportional to a difference between the first and second timestamp values. 2. The method of claim 1, wherein the first and second time stamp values are associated with sequentially received first and second data packets. Determining a difference between the first and second time stamp values; latching the first time stamp value; latching the second time stamp value; The method of claim 1, comprising subtracting the first time stamp value from a second time stamp value. 4. The method of claim 1, wherein determining a difference between the first and second timestamp values includes generating a difference value corresponding to the difference between the first and second timestamp values. Generating the clock signal includes: continuously adjusting the difference value; and generating a signal pulse when the adjusted difference value reaches a predetermined value;
The method of claim 1, wherein the frequency of the clock signal is proportional to the frequency of successive signal pulses. 5. The method of claim 4, wherein adjusting the difference value comprises decrementing the difference value, and wherein the predetermined value is a predetermined minimum value. The method described in. 6. The method of claim 1, wherein determining a difference value between the first and second timestamp values comprises generating a difference value, and the method comprises modifying the difference value. The method of claim 1, further comprising, wherein the frequency of the generated clock signal is proportional to the value of the modified difference. 7. An audio source coupled to an audio receiver,
The audio source produces a stream of audio data packets having an associated timestamp value, and the audio receiver detects a data sample rate from the audio data packets in a home entertainment system that receives the audio data packets. A method for recovering, the method comprising: extracting first and second time stamp values from first and second audio data packets; determining a difference between the first and second time stamp values. Determining and generating a clock signal having a frequency substantially proportional to a value of the difference between the determined first and second timestamp values. 8. The method of claim 7, wherein said first and second audio data packets are received sequentially by said audio receiver. 9. The audio receiver receives the audio data packet in a buffer, the method comprising: monitoring a fill level of the buffer; if the fill level is less than a first predetermined level, Increasing the frequency of the generated clock signal; and reducing the frequency of the generated clock signal when the fill level exceeds a second predetermined level. The method according to claim 7. 10. The method of claim 1, wherein determining the difference between the first and second time stamp values comprises generating a difference value corresponding to the difference value between the first and second time stamp values. And generating the clock signal includes: continuously adjusting the difference value; and generating a signal pulse when the adjusted difference value reaches a predetermined value.
The method of claim 7, wherein the frequency of the clock signal is proportional to the frequency of successive signal pulses. 11. The audio receiver receives the audio data packet in a buffer, the method comprising: monitoring a fill level of the buffer; and adjusting the difference value before continuously adjusting the difference value. The method of claim 10, further comprising modifying a value, the modification corresponding to a monitored fill level of the buffer. 12. A circuit for receiving a stream of data packets including an associated timestamp value, wherein the buffer is operable to receive and temporarily store the data packet; and a buffer coupled to the buffer. A packet parser operable to separate the timestamp value from the data packet; and coupled to the packet parser and operable to receive the timestamp value and determine a difference therebetween. , A sample clock recovery circuit further operable to generate a clock signal having a frequency substantially proportional to the difference between the determined timestamp values. 13. A monitor coupled to the buffer and the clock recovery circuit, the monitor operable to detect a fill level of the buffer and generate a fill control signal in response thereto. 13. The circuit of claim 12, wherein the clock recovery circuit is operable to receive the fill control signal and adjust a frequency of the generated clock signal in response thereto. 14. The circuit of claim 12, wherein the clock recovery circuit determines a difference between the time stamp values associated with successively received data packets. 15. The clock recovery circuit receives first and second time stamp values and generates a difference value corresponding to a difference between the first and second time stamp values. A subtractor operable to receive the difference value, and operable to continuously decrement the difference value, wherein the decremented difference value is equal to a predetermined minimum value Operable to generate a signal pulse, said clock signal comprising: a down counter generated by a clock recovery circuit having a frequency proportional to the frequency of successive signal pulses. Item 13. The circuit according to Item 12. 16. A monitor coupled to the buffer and the clock recovery circuit, the monitor operable to detect a fill level of the buffer and generate a fill control signal in response thereto. 16. The circuit of claim 15, wherein the subtractor is operable to receive the fill control signal and adjust a generated difference value in response thereto. 17. A circuit for recovering a data sample clock from a stream of data packets including an associated timestamp value, the circuit being operable to latch first and second timestamp values, respectively. First and second latches, receiving the latched first and second time stamp values, and responsively generating a difference value corresponding to a difference between the first and second time stamp values A subtractor operable to receive the difference value, and operable to continuously decrement the difference value, wherein the decremented difference value is equal to a predetermined minimum value A down counter operable to generate a signal pulse; and receiving the signal pulse and correspondingly generating a clock signal. It is operable to generate a frequency of the clock signal circuit, characterized in that it includes a phase-locked group which is proportional to the frequency of the signal pulses consecutive. 18. The subtractor receives a control signal and, in response,
The circuit of claim 17, further operable to modify the generated difference value. 19. The circuit of claim 17, wherein the down counter is operable to receive a next difference value generated by the subtractor in response to the signal pulse. . 20. A home entertainment system comprising an audio / video source coupled to an audio / video receiver, each of said sources operable to generate a stream of data packets having an associated timestamp value. And each of the receivers is operable to receive a selected one of the streams of data packets, and at least one of the receivers receives the received data packets and A buffer operable to temporarily store, a monitor coupled to the buffer, operable to detect a fill level of the buffer, and to generate a fill control signal in response thereto; A time stamp value coupled to a buffer and from the data packet A packet parser operable to separate the timestamp values and operable to receive the timestamp values and determine a difference between them; and A sample clock recovery circuit operable to receive a signal, and further operable to generate a clock signal having a frequency corresponding to the difference between the determined timestamp values and the fill control signal. A home entertainment system characterized by the following. 21. The home entertainment system of claim 20, wherein the clock recovery circuit determines a difference between the time stamp values associated with successively received data packets. 22. The home entertainment system according to claim 20, wherein said audio / video source is coupled to said audio / video receiver by an IEEE 1394 bus.