WO1999057767A1 - Bipolar mos power transistor - Google Patents

Bipolar mos power transistor Download PDF

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Publication number
WO1999057767A1
WO1999057767A1 PCT/DE1999/000854 DE9900854W WO9957767A1 WO 1999057767 A1 WO1999057767 A1 WO 1999057767A1 DE 9900854 W DE9900854 W DE 9900854W WO 9957767 A1 WO9957767 A1 WO 9957767A1
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semiconductor body
type
power transistor
mos power
trough
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PCT/DE1999/000854
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German (de)
French (fr)
Inventor
Helmut Strack
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Infineon Technologies Ag
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT

Definitions

  • the present invention relates to a MOS power transistor having a semiconductor body of one conduction type, at least one trough-shaped region of the other embedded in a first surface of the semiconductor body, of the opposite conduction type for one conduction type, a source zone of the one conduction type provided in the trough-shaped region Source zone and metallization contacting the trough-shaped region and a drain metallization provided on a second surface of the semiconductor body opposite the first surface.
  • a highly conductive transistor switch is known, the collector zone of which is provided with a metal layer forming a Schottky contact, which injects minority charge carriers into the collector zone after the semiconductor switch has been switched on, in order to be able to carry out switching operations on relatively large currents with relatively small control currents. If the barrier of such a Schottky contact is sufficiently large, a corresponding injection of holes into an n-type drain zone of a MOS power transistor can be carried out, for example (cf. SM Sze, "Physics of Semiconductor Devices", pages 364 to 393 and US 5,262,668).
  • DE 196 04 044 A discloses a semiconductor component which can be controlled by a field effect and in which a plurality of floating doped regions of the other conductivity type are provided in a drain zone of the one conduction type, the doping concentrations of these floating regions and the region of the drain zone surrounding the regions are essentially equal to each other. The aim of this is to ensure that the semiconductor component which can be controlled by the field effect provides a low forward resistance despite a high reverse voltage.
  • a Schottky contact in the drain or anode region, a Schottky contact is provided, the barrier of which is set large enough so that a sufficiently high charge carrier injection into the drain zone can be done.
  • Parasitic npnp thyristor structures are hereby avoided in an advantageous manner, since the Schottky contact replaces a diffused or implanted area.
  • a modulation of an n-channel MOS power transistor by the minority charge carriers is possible without major problems, since by adjusting the barrier height of the Schottky contact the modulation size can be set almost arbitrarily, which is up to the limit case of a diffused pn-
  • the barrier height can be easily influenced by appropriate surface terms, such as:
  • the above explanations relate to the setting of the barrier height of the Schottky contact as a first aspect of the present invention, it is particularly important for this that at least one region of the second conductivity type is provided in the semiconductor body of the one conductivity type.
  • This area of the second conductivity type can be designed as described in US Pat. No. 4,754,310 or in DE 196 04 044 A: n- and p-doped areas are alternately provided in the semiconductor body between the Schottky contact and the trough-shaped area (US 4,754,310), or the semiconductor body contains a multiplicity of floating regions of the second conductivity type (DE 196 04 044 A).
  • the adjustable minority charge carrier injection can be used in addition to the increase in conductivity in the drain zone due to the increase in doping.
  • the at least one region of the second conductivity type in the semiconductor body therefore means that a relatively small injection of minority charge carriers from the Schottky contact is sufficient to deliver the charge required in the drain zone for a low on-resistance at high reverse voltage.
  • Aluminum or other suitable metals such as Pd, Pt, Ti, Ni, Cr, V etc. can be used for the final contact to the drain zone.
  • further metal layers can be arranged above it, which ensure, for example, the solderability on the drain side.
  • the one line type is preferably the n line type and the other line type is the p line type, so that the region of the other or second line type is p-doped and the plurality of floating regions are thus also p-doped. Overall, an n-channel power transistor is thus obtained.
  • the invention is also applicable to a p-channel power transistor.
  • the drain zone is p-doped, while the floating regions are n-doped. These floating areas are then reloaded by electron emission from the Schottky drain contact when the power transistor is switched on.
  • Fig. 1 is a sectional view through a first embodiment of the invention with alternating n- and p-doped vertical regions in the semiconductor body, and 6
  • Fig. 2 is a sectional view through a second embodiment of the present invention with p-doped spherical floating regions in an n-type semiconductor body.
  • p-type wells 2 are introduced in an n-type silicon semiconductor body 1, in which highly doped n-type source zones 3 are provided, which are doped with arsenic, for example.
  • the p-type wells 2 can be doped with boron, for example.
  • the p-type wells 2 and the source zones 3 are contacted with a metallization 4, which can be made of aluminum, for example.
  • This metallization 4 is located outside the contacts with the source zones 3 or the p-type wells 2 on an insulating layer 5, for example consisting of silicon dioxide and / or silicon nitride, into which in the area between the p-type wells 2 gate electrodes 6 made of doped polycrystalline silicon are embedded.
  • a metallization 7 is attached, to which a drain-source voltage U D s is present.
  • the metallization 4 may have ground potential applied to it.
  • p-type regions 8 are provided in the semiconductor body 1 essentially in the region below the p-type troughs 2, which extend vertically from the p-type troughs 2 to the metallization 7.
  • the metallization 7 forms a Schottky contact with the
  • Semiconductor body 1 or the p-type troughs 8 and consists, for example, of metals suitable for this purpose, such as Pd, Pt, Ti, Cr, V, Ni, etc. 7
  • Barrier height of the Schottky contact still surface terms in the semiconductor body 1 or in the p-type regions 8, such as boron, which is implanted in small doses below a few 10 12 cm "2 .
  • FIG. 2 shows a further exemplary embodiment of the invention, in which, instead of the vertical p-type regions 8, floating, for example spherical, p-type regions 18 are provided in the semiconductor body 1.
  • the hole injection (see arrow 10) from the metallization 7 provides sufficient positive charge carriers to obtain the necessary charge for the floating areas 18 in the drain area. The extent of this injection can be determined by adjusting the height of the barrier 9. If the injection is very low, a MOS transistor with a very small storage charge is practically formed in the forward mode, a low threshold value being present in the forward characteristic due to the Schottky contact between the metallization 7 and the semiconductor body 1.
  • the modulation height of the transistor can be set practically as desired, which is up to 8 the borderline case of a diffused pn junction instead of the Schottky contact and thus leads to an IGBT.
  • the area 8 or the areas 18 are p-conductive and the transistor is an n-channel transistor
  • the invention can also be applied in the same way to a p-channel transistor. Apply power transistor.
  • the semiconductor body 1 is p-doped, while the regions 8 and the regions 18 are n-doped and are charged by electron emission from the metallization 7 when the transistor is switched on.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention relates to an MOS power transistor with a semiconductor body (1) corresponding to one type of conductivity, at least one trough-shaped area (2) embedded in a first surface of the semiconductor body corresponding to another type of conductivity that is opposite to that of the first, a source zone provided in the trough-shaped area (2) corresponding to one type of conductivity, a metallic coating (4) contacting the trough-shaped area (2) and a drain-metallic coating (7) provided on a second surface of the semiconductor body (1) opposite the first surface of the semiconductor body (1). The drain-metallic coating forms a Schottky contact with the semiconductor body (1), whereby the barrier height of said Schottky contact can be adjusted. An area that corresponds to the second type of conductivity and consists of a plurality of floating areas (18) is provided in the semiconductor body.

Description

1 1
Beschreibungdescription
BIPOLARER MOS-LEISTUNGSTRANSISTORBIPOLAR MOS POWER TRANSISTOR
Die vorliegende Erfindung betrifft einen MOS-Leistungstran- sistor mit einem Halbleiterkorper des einen Leitungstyps, mindestens einem in eine erste Oberfläche des Halbleiterkörpers eingebetteten wannenformigen Gebiet des anderen, zum einen Leitungstyp entgegengesetzten Leitungstyps, einer in dem wannenformigen Gebiet vorgesehenen Sourcezone des einen Leitungstyps, einer die Sourcezone und das wannenförmige Gebiet kontaktierenden Metallisierung und einer auf einer zweiten, zur ersten Oberfläche gegenüberliegenden Oberfläche des Halbleiterkörpers vorgesehenen Drain-Metallisierung.The present invention relates to a MOS power transistor having a semiconductor body of one conduction type, at least one trough-shaped region of the other embedded in a first surface of the semiconductor body, of the opposite conduction type for one conduction type, a source zone of the one conduction type provided in the trough-shaped region Source zone and metallization contacting the trough-shaped region and a drain metallization provided on a second surface of the semiconductor body opposite the first surface.
Aus US 3 141 119 ist ein hochleitender Transistorschalter bekannt, dessen Kollektorzone mit einer einen Schottky-Kontakt bildenden Metallschicht versehen ist, die nach einem Einschalten des Halbleiterschalters Minoritätsladungsträger in die Kollektorzone injiziert, um mit relativ kleinen Steuerströmen Schaltoperationen an demgegenüber großen Strömen vornehmen zu können. Ist die Barriere eines solchen Schottky- Kontaktes ausreichend groß, so kann beispielsweise eine entsprechende Injektion von Löchern in eine n-leitende Drainzone eines MOS-Leistungstransistors vorgenommen werden (vgl. hierzu S.M. Sze, "Physics of Semiconductor Devices", Seiten 364 bis 393 und US 5 262 668) .From US 3 141 119 a highly conductive transistor switch is known, the collector zone of which is provided with a metal layer forming a Schottky contact, which injects minority charge carriers into the collector zone after the semiconductor switch has been switched on, in order to be able to carry out switching operations on relatively large currents with relatively small control currents. If the barrier of such a Schottky contact is sufficiently large, a corresponding injection of holes into an n-type drain zone of a MOS power transistor can be carried out, for example (cf. SM Sze, "Physics of Semiconductor Devices", pages 364 to 393 and US 5,262,668).
Die Verwendung von Schottky-Kontakten für Gleichrichterzwecke ist an sich seit langem bekannt (vgl. beispielsweise US 4 641 174, 5 241 195, 5 612 567) . Ebenso ist es üblich, Schottky-Kontakte zusammen mit MOS-Transistoren in den verschiedensten Gestaltungen einzusetzen (vgl. US 5 365 102, So- lid-State Electronics, Vol. 32, Nr. 4, Seiten 317-322, 1989 2 und IEEE Transactions on Electron Devices, Vol. Ed-33, Nr. 12, Dezember 1986, Seiten 1940 bis 1947) .The use of Schottky contacts for rectifier purposes has long been known per se (cf. for example US Pat. No. 4,641,174, 5,241,195, 5,612,567). It is also common to use Schottky contacts together with MOS transistors in a wide variety of designs (cf. US Pat. No. 5,365,102, Solid State Electronics, Vol. 32, No. 4, pages 317-322, 1989) 2 and IEEE Transactions on Electron Devices, Vol. Ed-33, No. 12, December 1986, pages 1940 to 1947).
Weiterhin ist aus US 4 754 310 eine Halbleiter-Leistungs- Vorrichtung bekannt, bei der eine Mehrzahl von Schichten in einem Halbleiterkorper zwischen einem Gate-Sourcebereich einerseits und einem Drainbereich andererseits aus Halbleiterzonen abwechselnd entgegengesetzten Leitungstyps besteht, um dort die Dotierungskonzentration wesentlich anzuheben, so daß der Einschaltwiderstand dieser Vorrichtung vermindert wird.Furthermore, from US 4,754,310 a semiconductor power device is known in which a plurality of layers in a semiconductor body between a gate-source region on the one hand and a drain region on the other hand consist of semiconductor zones of alternately opposite conductivity types in order to significantly increase the doping concentration there, so that the on-resistance of this device is reduced.
Schließlich ist aus DE 196 04 044 A ein durch Feldeffekt steuerbares Halbleiterbauelement bekannt, bei dem in einer Drainzone des einen Leitungstyps eine Vielzahl floatender do- tierter Bereiche des anderen Leitungstyps vorgesehen ist, wobei die Dotierungskonzentrationen dieser floatenden Bereiche und des die Bereiche umgebenden Gebietes der Drainzone im wesentlichen gleich zueinander sind. Damit soll erreicht werden, daß das durch Feldeffekt steuerbare Halbleiterbauelement trotz einer hohen Sperrspannung einen niedrigen Durchlaßwiderstand bereitstellt.Finally, DE 196 04 044 A discloses a semiconductor component which can be controlled by a field effect and in which a plurality of floating doped regions of the other conductivity type are provided in a drain zone of the one conduction type, the doping concentrations of these floating regions and the region of the drain zone surrounding the regions are essentially equal to each other. The aim of this is to ensure that the semiconductor component which can be controlled by the field effect provides a low forward resistance despite a high reverse voltage.
Es ist Aufgabe der vorliegenden Erfindung, einen MOS-Lei- stungstransistor zu schaffen, bei dem ohne weiteres eine aus- reichende Injektion von Minoritätsladungsträgern in die Drainzone sichergestellt ist, um so für einen niedrigen Durchlaßwiderstand bei hoher Sperrspannung zu sorgen.It is an object of the present invention to provide a MOS power transistor in which a sufficient injection of minority charge carriers into the drain zone is easily ensured, in order to ensure a low on resistance with a high reverse voltage.
Diese Aufgabe wird bei einem MOS-Leistungstransistor der ein- gangs genannten Art erfindungsgemäß dadurch gelöst, daß (a) die Drain-Metallisierung mit dem Halbleiterkorper einen Schottky-Kontakt mit einstellbarer Barrierenhöhe bildet, und (b) im Halbleiterkorper mindestens ein Bereich des zweiten Leitungstyps vorgesehen ist. 3This object is achieved according to the invention in a MOS power transistor of the type mentioned at the outset in that (a) the drain metallization forms a Schottky contact with an adjustable barrier height with the semiconductor body, and (b) at least one region of the second conductivity type in the semiconductor body is provided. 3
Mit der vorliegenden Erfindung werden somit erstmals verschiedene, an sich bekannte Maßnahmen in besonders vorteilhafter und synergetischer Weise gemeinsam angewandt: im Drain- bzw. Anodenbereich wird ein Schottky-Kontakt vorgesehen, dessen Barriere groß genug eingestellt ist, damit eine ausreichend hohe Ladungsträgerinjektion in die Drainzone erfolgen kann. Parasitäre npnp-Thyristorstrukturen werden hierdurch in vorteilhafter Weise vermieden, da der Schottky- Kontakt ein diffundiertes bzw. implantiertes Gebiet ersetzt.With the present invention, therefore, for the first time, various measures known per se are used together in a particularly advantageous and synergetic manner: in the drain or anode region, a Schottky contact is provided, the barrier of which is set large enough so that a sufficiently high charge carrier injection into the drain zone can be done. Parasitic npnp thyristor structures are hereby avoided in an advantageous manner, since the Schottky contact replaces a diffused or implanted area.
Eine Modulation eines n-Kanal-MOS-Leistungstransistors durch die Minoritätsladungsträger ist ohne größere Probleme möglich, da durch Einstellung der Barrierenhöhe des Schottky- Kontaktes die Modulationsgröße nahezu beliebig einstellbar ist, was bis zu dem Grenzfall eines diffundierten pn-A modulation of an n-channel MOS power transistor by the minority charge carriers is possible without major problems, since by adjusting the barrier height of the Schottky contact the modulation size can be set almost arbitrarily, which is up to the limit case of a diffused pn-
Überganges bei IGBT's (Bipolartransistor mit isoliertem Gate) führt. Die Barrierenhöhe läßt sich nämlich durch entsprechende Oberflächenterme ohne weiteres beeinflussen, wie beispielsweise durch:Transition in IGBTs (bipolar transistor with insulated gate) leads. The barrier height can be easily influenced by appropriate surface terms, such as:
(a) eine Beschichtung der Oberfläche mit Aluminium oder anderen hierfür üblichen Metallen, wie Pd, Pt, Ti, Cr oder V,(a) coating the surface with aluminum or other metals customary for this, such as Pd, Pt, Ti, Cr or V,
(b) Implantation von Fremdatomen, die nicht dotierend wirken, aber Grenzflächenterme erzeugen, wie beispielsweise Ar,(b) implantation of foreign atoms that do not have a doping effect, but generate interface terms, such as Ar,
(c) Implantation von Aluminium, Gallium, Indium oder Bor in geringen Dosen (unter einigen 1012 cm-2; bei p-Kanal-MOS- Leistungstransistoren Implantation von P, As, Sb usw.),(c) implantation of aluminum, gallium, indium or boron in small doses (below a few 10 12 cm -2 ; with p-channel MOS power transistors, implantation of P, As, Sb etc.),
(d) Implantation von Ionen, die beispielsweise bei einem n- leitenden Halbleiterkorper n-dotierend wirken und bei speziell niedrigen Dosen unter einigen 1012 cm-2 die Barriere erniedrigen, da hier die Bildung von Grenzflächen- termen überwiegt, und (e) gleichzeitige Implantation von n- und p-dotierenden Ionen.(d) implantation of ions which, for example, have an n-doping effect on an n-conducting semiconductor body and lower the barrier at particularly low doses below a few 10 12 cm -2 , since here the formation of interface terms predominates, and (e) simultaneous implantation of n- and p-doping ions.
Es sei angemerkt, daß die Maßnahme (c) bei höheren Dosen über 1013 cm"2 zu einem üblichen IGBT führt.It should be noted that measure (c) leads to a common IGBT at higher doses over 10 13 cm "2 .
Während sich die obigen Erläuterungen auf die Einstellung der Barrierenhöhe des Schottky-Kontaktes als einem ersten Ge- sichtspunkt der vorliegenden Erfindung beziehen, ist bei dieser von besonderer Bedeutung, daß im Halbleiterkorper des einen Leitungstyps mindestens ein Bereich des zweiten Leitungstyps vorgesehen ist. Dieser Bereich des zweiten Leitungstyps kann so gestaltet sein, wie dies in der US 4 754 310 oder in der DE 196 04 044 A beschrieben ist: im Halbleiterkorper sind abwechselnd n- und p-dotierte Gebiete zwischen dem Schottky- Kontakt und dem wannenformigen Gebiet vorgesehen (US 4 754 310) , oder der Halbleiterkorper enthält eine Vielzahl von floatenden Gebieten des zweiten Leitungstyps (DE 196 04 044 A) .While the above explanations relate to the setting of the barrier height of the Schottky contact as a first aspect of the present invention, it is particularly important for this that at least one region of the second conductivity type is provided in the semiconductor body of the one conductivity type. This area of the second conductivity type can be designed as described in US Pat. No. 4,754,310 or in DE 196 04 044 A: n- and p-doped areas are alternately provided in the semiconductor body between the Schottky contact and the trough-shaped area (US 4,754,310), or the semiconductor body contains a multiplicity of floating regions of the second conductivity type (DE 196 04 044 A).
Bei den abwechselnd n- und p-dotierten Gebieten kann zusätzlich zu der Leitfähigkeitserhöhung in der Drainzone durch die Dotierungserhöhung noch die einstellbare Minoritätsladungs- trägerinjektion ausgenutzt werden.In the alternating n- and p-doped regions, the adjustable minority charge carrier injection can be used in addition to the increase in conductivity in the drain zone due to the increase in doping.
Bei den floatenden Gebieten wird erreicht, daß bereits eine sehr geringe Injektion an Löchern ausreichend ist, um beim Einschalten des Transistors die notwendige Ladung zu liefern. Ist diese Injektion sehr gering, so entsteht im Durchlaßbetrieb praktisch ein MOS-Leistungstransistor mit einer verschwindenden Speicherladung, der allerdings einen kleinen Schwellenwert durch den Schottky-Kontakt in seiner Durchlaßcharakteristik aufweist. 5With the floating areas it is achieved that a very small injection of holes is sufficient to supply the necessary charge when the transistor is switched on. If this injection is very low, a MOS power transistor with a vanishing storage charge is practically created in the forward mode, which, however, has a low threshold value in its forward characteristic due to the Schottky contact. 5
Der mindestens eine Bereich des zweiten Leitungstyps im Halbleiterkorper bewirkt also, daß bereits eine relativ geringe Injektion von Minoritätsladungsträgern aus dem Schottky-Kontakt ausreichend ist, um die notwendige Ladung in der Drain- zone für einen niedrigen Einschaltwiderstand bei hoher Sperrspannung zu liefern.The at least one region of the second conductivity type in the semiconductor body therefore means that a relatively small injection of minority charge carriers from the Schottky contact is sufficient to deliver the charge required in the drain zone for a low on-resistance at high reverse voltage.
Für den abschließenden Kontakt zur Drainzone können Aluminium oder andere geeignete Metalle, wie beispielsweise Pd, Pt, Ti, Ni, Cr, V usw. verwendet werden. Außerdem können darüber noch weitere Metallschichten angeordnet werden, die beispielsweise die Lötfähigkeit auf der Drainseite sicherstellen.Aluminum or other suitable metals such as Pd, Pt, Ti, Ni, Cr, V etc. can be used for the final contact to the drain zone. In addition, further metal layers can be arranged above it, which ensure, for example, the solderability on the drain side.
In bevorzugter Weise ist der eine Leitungstyp der n-Leitungs- typ und der andere Leitungstyp der p-Leitungstyp, so daß der Bereich des anderen bzw. zweiten Leitungstyps p-dotiert ist und die Vielzahl von floatenden Gebieten damit ebenfalls p- dotiert sind. Insgesamt wird damit ein n-Kanal-Leistungs- transistor erhalten.The one line type is preferably the n line type and the other line type is the p line type, so that the region of the other or second line type is p-doped and the plurality of floating regions are thus also p-doped. Overall, an n-channel power transistor is thus obtained.
Selbstverständlich ist die Erfindung aber auch auf einen p- Kanal-Leistungstransistor anwendbar. In diesem Fall ist die Drainzone p-dotiert, während die floatenden Gebiete n-dotiert sind. Diese floatenden Gebiete werden dann durch Elektronen- emission vom Schottky-Drainkontakt beim Einschalten des Leistungstransistors umgeladen.Of course, the invention is also applicable to a p-channel power transistor. In this case, the drain zone is p-doped, while the floating regions are n-doped. These floating areas are then reloaded by electron emission from the Schottky drain contact when the power transistor is switched on.
Nachfolgend wird die Erfindung anhand der Zeichnungen näher erläutert. Es zeigen:The invention is explained in more detail below with reference to the drawings. Show it:
Fig. 1 ein Schnittbild durch ein erstes Ausführungsbeispiel der Erfindung mit abwechselnd n- und p-dotierten vertikalen Gebieten im Halbleiterkorper, und 6Fig. 1 is a sectional view through a first embodiment of the invention with alternating n- and p-doped vertical regions in the semiconductor body, and 6
Fig. 2 ein Schnittbild durch ein zweites Ausführungsbeispiel der vorliegenden Erfindung mit p-dotierten kugelförmigen floatenden Gebieten in einem n-leitenden Halbleiterkorper.Fig. 2 is a sectional view through a second embodiment of the present invention with p-doped spherical floating regions in an n-type semiconductor body.
Fig. 1 zeigt ein erstes Ausführungsbeispiel der Erfindung, bei dem in einem n-leitenden Silizium-Halbleiterkörper 1 p- leitende Wannen 2 eingebracht sind, in denen hochdotierte n- leitende Sourcezonen 3 vorgesehen sind, die beispielsweise mit Arsen dotiert sind. Die p-leitenden Wannen 2 können beispielsweise mit Bor dotiert sein.1 shows a first exemplary embodiment of the invention, in which p-type wells 2 are introduced in an n-type silicon semiconductor body 1, in which highly doped n-type source zones 3 are provided, which are doped with arsenic, for example. The p-type wells 2 can be doped with boron, for example.
Die p-leitenden Wannen 2 und die Sourcezonen 3 sind mit einer Metallisierung 4 kontaktiert, die beispielsweise aus Alumini- um bestehen kann. Diese Metallisierung 4 befindet sich außerhalb der Kontakte mit den Sourcezonen 3 bzw. den p-leitenden Wannen 2 auf einer beispielsweise aus Siliziumdioxid und/oder Siliziumnitrid bestehenden Isolierschicht 5, in die im Bereich zwischen den p-leitenden Wannen 2 Gateelektroden 6 aus dotiertem polykristallinen Silizium eingebettet sind.The p-type wells 2 and the source zones 3 are contacted with a metallization 4, which can be made of aluminum, for example. This metallization 4 is located outside the contacts with the source zones 3 or the p-type wells 2 on an insulating layer 5, for example consisting of silicon dioxide and / or silicon nitride, into which in the area between the p-type wells 2 gate electrodes 6 made of doped polycrystalline silicon are embedded.
Auf der zu der Metallisierung 4 gegenüberliegenden Oberseite des Halbleiterkörpers 1 ist eine Metallisierung 7 angebracht, an der eine Drain-Source-Spannung UDs anliegt. Die Metalli- sierung 4 ist gegebenenfalls mit Massepotential beaufschlagt.On the upper side of the semiconductor body 1 opposite the metallization 4, a metallization 7 is attached, to which a drain-source voltage U D s is present. The metallization 4 may have ground potential applied to it.
Außerdem sind im Halbleiterkorper 1 p-leitende Gebiete 8 im wesentlichen im Bereich unterhalb der p-leitenden Wannen 2 vorgesehen, die sich vertikal von den p-leitenden Wannen 2 bis zu der Metallisierung 7 erstrecken.In addition, p-type regions 8 are provided in the semiconductor body 1 essentially in the region below the p-type troughs 2, which extend vertically from the p-type troughs 2 to the metallization 7.
Die Metallisierung 7 bildet einen Schottky-Kontakt mit demThe metallization 7 forms a Schottky contact with the
Halbleiterkorper 1 bzw. den p-leitenden Wannen 8 und besteht beispielsweise aus hierfür geeigneten Metallen, wie Pd, Pt, Ti, Cr, V, Ni usw. Gegebenenfalls können zur Einstellung der 7Semiconductor body 1 or the p-type troughs 8 and consists, for example, of metals suitable for this purpose, such as Pd, Pt, Ti, Cr, V, Ni, etc. 7
Barrierenhöhe des Schottky-Kontaktes noch Oberflächenterme im Halbleiterkorper 1 bzw. den in p-leitenden Gebieten 8 vorhanden sein, wie beispielsweise Bor, das in geringen Dosen unter einigen 1012 cm"2 implantiert ist.Barrier height of the Schottky contact still surface terms in the semiconductor body 1 or in the p-type regions 8, such as boron, which is implanted in small doses below a few 10 12 cm "2 .
Nach Anlegen einer positiven Spannung UDs an die Metallisierung 7 und eines Massepotentials an die Metallisierung 4 werden durch die Barriere 9 des Schottky-Kontaktes zwischen der Metallisierung 7 und dem Halbleiterkorper 1 bzw. den p-lei- tenden Gebieten 8 Minoritätsladungsträger (positive Löcher) aus der Metallisierung 7 in den Halbleiterkorper 1 bzw. in die p-leitenden Gebiete 8 injiziert, wie dies durch einen Pfeil 10 angedeutet ist. Damit wird die Leitfähigkeit in der Drainzone des Transistors erhöht, so daß sich insgesamt ein niedriger Einschaltwiderstand ergibt.After a positive voltage U D s has been applied to the metallization 7 and a ground potential to the metallization 4, minority charge carriers (positive holes) are formed through the barrier 9 of the Schottky contact between the metallization 7 and the semiconductor body 1 or the p-conducting regions 8 ) injected from the metallization 7 into the semiconductor body 1 or into the p-type regions 8, as indicated by an arrow 10. This increases the conductivity in the drain zone of the transistor, so that the overall on-resistance is low.
Fig. 2 zeigt ein weiteres Ausführungsbeispiel der Erfindung, bei dem aber anstelle der vertikalen p-leitenden Gebiete 8 floatende, beispielsweise kugelförmige, p-leitende Gebiete 18 im Halbleiterkorper 1 vorgesehen sind. Durch die Löcherinjektion (vgl. die Pfeil 10) aus der Metallisierung 7 werden ausreichend positive Ladungsträger geliefert, um die notwendige Ladung für die floatende Gebiete 18 im Drainbereich zu erhalten. Durch Einstellung der Höhe der Barriere 9 läßt sich das Ausmaß dieser Injektion festlegen. Ist die Injektion sehr gering, entsteht im Durchlaßbetrieb praktisch ein MOS-Transistor mit sehr kleiner Speicherladung, wobei ein kleiner Schwellenwert durch den Schottky-Kontakt zwischen der Metallisierung 7 und dem Halbleiterkorper 1 in der Durchlaßcharak- teristik vorliegt.2 shows a further exemplary embodiment of the invention, in which, instead of the vertical p-type regions 8, floating, for example spherical, p-type regions 18 are provided in the semiconductor body 1. The hole injection (see arrow 10) from the metallization 7 provides sufficient positive charge carriers to obtain the necessary charge for the floating areas 18 in the drain area. The extent of this injection can be determined by adjusting the height of the barrier 9. If the injection is very low, a MOS transistor with a very small storage charge is practically formed in the forward mode, a low threshold value being present in the forward characteristic due to the Schottky contact between the metallization 7 and the semiconductor body 1.
Bei beiden Ausführungsbeispielen kann durch Einstellung der Barrierenhöhe des Schottky-Kontaktes die Modulationshöhe des Transistors praktisch beliebig eingestellt werden, was bis zu 8 dem Grenzfall eines diffundierten pn-Überganges anstelle des Schottky-Kontaktes und damit zu einem IGBT führt.In both exemplary embodiments, by adjusting the barrier height of the Schottky contact, the modulation height of the transistor can be set practically as desired, which is up to 8 the borderline case of a diffused pn junction instead of the Schottky contact and thus leads to an IGBT.
Während in den Ausführungsbeispielen der Fig. 1 und 2 das Ge- biet 8 bzw. die Gebiete 18 p-leitend sind und der Transistor insgesamt ein n-Kanal-Transistor ist, läßt sich die Erfindung in gleicher Weise auch auf einen p-Kanal-Leistungstransistor anwenden. In diesem Fall ist der Halbleiterkorper 1 p-dotiert, während die Gebiete 8 bzw. die Gebiete 18 n-dotiert sind und durch Elektronenemission von der Metallisierung 7 beim Einschalten des Transistors umgeladen werden. 1 and 2, the area 8 or the areas 18 are p-conductive and the transistor is an n-channel transistor, the invention can also be applied in the same way to a p-channel transistor. Apply power transistor. In this case, the semiconductor body 1 is p-doped, while the regions 8 and the regions 18 are n-doped and are charged by electron emission from the metallization 7 when the transistor is switched on.
9 Bezugszeichenliste9 List of reference symbols
1 Halbleiterkorper1 semiconductor body
2 wannenförmiges Gebiet 3 Sourcezone2 trough-shaped area 3 source zone
4 Metallisierung4 metallization
5 Isolierschicht5 insulating layer
6 Gateelektrode6 gate electrode
7 Drain-Metallisierung 8 Bereich des zweiten Leitungstyps7 drain metallization 8 area of the second conductivity type
9 Barriere9 barrier
10 Pfeil für Minoritätsladungsträger10 Arrow for minority charge carriers
18 p-leitende Gebiete 18 p-type areas

Claims

10Patentansprüche 10 patent claims
1. MOS-Leistungstransistor, mit:1. MOS power transistor, with:
- einem Halbleiterkorper (1) des einen Leitungstyps, - mindestens einem in eine erste Oberfläche des Halbleiterkörpers (1) eingebetteten wannenformigen Gebiet (2) des anderen, zum einen Leitungstyp entgegengesetzten Leitungstyps,- a semiconductor body (1) of one conduction type, - at least one trough-shaped region (2) of the other conduction type of opposite conduction type embedded in a first surface of the semiconductor body (1),
- einer in dem wannenformigen Gebiet (2) vorgesehenen Sourcezone (3) des einen Leitungstyps,a source zone (3) of one conduction type provided in the trough-shaped region (2),
- einer die Sourcezone (3) und das wannenför ige Gebiet- The source zone (3) and the tub-shaped area
(2) kontaktierenden Metallisierung (4) und(2) contacting metallization (4) and
- einer auf einer zweiten, zur ersten Oberfläche gegenüberliegenden Oberfläche des Halbleiterkörpers (1) vor- gesehenen Drain-Metallisierung (7), d a d u r c h g e k e n n z e i c h n e t , daß- A drain metallization (7) provided on a second surface of the semiconductor body (1) opposite to the first surface, that means that a
- die Drain-Metallisierung (7) mit dem Halbleiterkorper (1) einen Schottky-Kontakt mit einstellbarer Barrierenhöhe bildet, und - im Halbleiterkorper (1) mindestens ein Bereich (8; 18) des anderen Leitungstyps vorgesehen ist.- The drain metallization (7) with the semiconductor body (1) forms a Schottky contact with an adjustable barrier height, and - at least one area (8; 18) of the other conductivity type is provided in the semiconductor body (1).
2. MOS-Leistungstransistor nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t , daß der Bereich (8) des anderen Leitungstyps sich zwischen dem Schottky-Kontakt und dem wannenformigen Gebiet (2) erstreckt.2. MOS power transistor according to claim 1, so that the region (8) of the other conductivity type extends between the Schottky contact and the trough-shaped region (2).
3. MOS-Leistungstransistor nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t , daß der Bereich (18) des anderen Leitungstyps eine Vielzahl von floatenden Gebieten aufweist.3. MOS power transistor according to claim 1, so that the region (18) of the other conductivity type has a plurality of floating regions.
4. MOS-Leistungstransistor nach Anspruch 3, d a d u r c h g e k e n n z e i c h n e t , 11 daß die floatenden Gebiete (18) im wesentlichen kugelförmig gestaltet sind.4. MOS power transistor according to claim 3, characterized in 11 that the floating areas (18) are substantially spherical.
5. MOS-Leistungstransistor nach einem der Ansprüche 1 bis 4, d a d u r c h g e k e n n z e i c h n e t , daß die Barrierenhöhe durch Einbau von Oberflächentermen einstellbar ist. 5. MOS power transistor according to one of claims 1 to 4, d a d u r c h g e k e n n z e i c h n e t that the barrier height is adjustable by incorporating surface terms.
PCT/DE1999/000854 1998-04-30 1999-03-23 Bipolar mos power transistor WO1999057767A1 (en)

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