WO1999057754A1 - Wet processing methods for the manufacture of electronic components - Google Patents

Wet processing methods for the manufacture of electronic components Download PDF

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Publication number
WO1999057754A1
WO1999057754A1 PCT/US1999/009722 US9909722W WO9957754A1 WO 1999057754 A1 WO1999057754 A1 WO 1999057754A1 US 9909722 W US9909722 W US 9909722W WO 9957754 A1 WO9957754 A1 WO 9957754A1
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WO
WIPO (PCT)
Prior art keywords
flow
barrier
fluid
processing
vessel
Prior art date
Application number
PCT/US1999/009722
Other languages
French (fr)
Inventor
Steven Verhaverbeke
Christopher F. Mcconnell
Lawrence J. Myland
Original Assignee
Cfmt, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cfmt, Inc. filed Critical Cfmt, Inc.
Priority to EP99920316A priority Critical patent/EP1078394A1/en
Priority to AU37842/99A priority patent/AU3784299A/en
Priority to JP2000547648A priority patent/JP2002514828A/en
Publication of WO1999057754A1 publication Critical patent/WO1999057754A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67075—Apparatus for fluid treatment for etching for wet etching
    • H01L21/67086—Apparatus for fluid treatment for etching for wet etching with the semiconductor substrates being dipped in baths or vessels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
    • H01L21/6704—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
    • H01L21/67057—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing with the semiconductor substrates being dipped in baths or vessels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67075—Apparatus for fluid treatment for etching for wet etching
    • H01L21/6708—Apparatus for fluid treatment for etching for wet etching using mainly spraying means, e.g. nozzles

Definitions

  • the present invention is directed to wet processing methods for the manufacture of electronic components and electronic component precursors, such as semiconductor wafers used in integrated circuits. More specifically, the present invention relates to improved processes for the enclosed flow-line treatment of substrates with fluids, such as semiconductor wafers and flat panel display.
  • wet processing is used extensively during the manufacture of integrated circuits, which typically comprise electronic component precursors such as semiconductor wafers, flat panels, and other electronic component precursors.
  • the electronic component precursors are placed in a bath or a vessel and then contacted with a series of reactive chemical process fluids and rinsing fluids.
  • the process fluids may be used, without limitation, for etching, photo resist stripping, and prediffusion cleaning and other cleaning steps of the electronic component precursors.
  • An example of a treatment system for electronic component precursors is described in U.S. Patent No. 4,633,893 - McConnell et al., which is herein incorporated by reference as if set forth in its entirety.
  • the electronic component precursors are treated in either a full flow vessel (a vessel closed to the environment), single tank, a wet bench, or bath.
  • the electronic component precursors are exposed to reactive chemical process fluids to either remove (i.e., clean) contamination on the electronic component precursors or to etch some part of the surface. After this cleaning or etching is performed, the chemical will adhere to the surface or - 2 - surfaces of the electronic component precursors.
  • the adhered chemical must then be removed before treating the electronic component precursors with the next reactive chemical process fluid so that the chemical residue does not contaminate the next reactive chemical process.
  • the adhered chemical is removed using deionized (Dl) water.
  • the standard wafer pitch for 300 mm wafers is 10 mm in a full load.
  • Full-flow processors employing a single processing vessel have small vessel sizes such that the wafer pitch is one-half that of the pitch of wafers processed in an immersion tank. This processing at a reduced pitch in full-flow single processing vessels is desirable due to attendant reductions in water and chemical consumption. Moreover, since the flow velocity for an equivalent total flow volume within a single vessel will be increased for reduced pitch processing, rinsing of the wafers will improve accordingly.
  • single vessel processing of wafers at less than one half the standard pitch, such as at one-third and one-quarter pitch processing is even more desirable than the known one-half pitch processing systems.
  • the present invention presents, inter alia, wet processing methods for the manufacture of electronic components and electronic component precursors, such as semiconductor wafers used in integrated circuits. More specifically, this invention relates to methods of, for example, cleaning electronic component precursors using wet processing techniques where wafers having a pitch that is less than one-half the standard wafer pitch are effectively processed in a single processing vessels.
  • the wafer pitch is reduced from the standard pitch to distances such as of one-half pitch, one-third pitch, and one-quarter pitch.
  • a flow resistance barrier is secured within the wafer vessel housing, upstream of the wafer stack.
  • the wafer stack could be a cassette of 300 mm wafers arranged at one-half the standard pitch for such wafers, and the stack is more preferably a cassette of 300 mm wafers arranged at one-third pitch or one-quarter pitch.
  • the flow resistance barrier is designed such that fluid flowing upward through the barrier, prior to flow through the wafers, is distributed to push the flow toward the middle of the wafers, where the flow resistance is the highest.
  • the flow resistance barrier is a screen of any suitable porous material where the holes in the screen are larger in the center of the screen (where the pressure in the chamber is higher) than the holes at the sides of the screen (where the pressure is lower).
  • the holes in the screen can be spaced closer together in the center of the screen and spaced at a greater distance at the sides of the screen to allow more flow to enter the chamber where the pressure is higher and less flow to enter where the pressure is lower.
  • the hole size can be the same throughout the screen or can be variable to provide a desired flow pattern.
  • the hole pattern and the size of the holes are selected to provide the least resistance to the flow of fluid in the middle of the wafers and the most resistance to fluid flow at the sides of the wafers.
  • the flow resistance barrier be designed to impart plug flow conditions for the flow of fluid onto the wafer.
  • the number, shape, size - 5 - and arrangement of the holes within the screen can be selected by one skilled in the art based upon the flow parameters to accentuate the flow of fluids toward the center of the wafers. These parameters include the size and shape of the vessel, the chemical composition of the fluids in use, the flow velocity, and the flow pressure. It is preferred that the hole size be large enough to allow dissolved gas in the liquid to pass through the screen. Holes can be made in the barrier material using a laser or by known hole punching apparatus.
  • Preferred materials for the flow resistance barrier include woven fabric material, to minimize blockage of the flow of fluid at the barrier, and a fiber mesh material wherein the fibers are distributed throughout the flow resistance barrier in a random fiber mesh. Because manufacturing imperfections in the flow resistance barrier can become dislodged from the barrier over time, thus adding contaminants into the treatment vessel, and can also trap chemicals thereon, thus clogging the barrier, a woven fabric material, which will generally have relatively few manufacturing imperfections, is a most preferred material for the flow resistance barrier.
  • the flow resistance barrier is a chemical resistant polymeric screen material, with Teflon being the most preferred polymeric material. It is preferred that the flow resistance barrier be chemically resistant to the various chemicals used in the wafer treatment operations so as to avoid chemical degradation of the barrier material.
  • flow injection apparatus such as controlled injection nozzles positioned in the processing vessel provide for increased flow of fluids into the middle of the wafers.
  • the location and output parameters of the injection nozzles are determined based upon the known flow parameters described above with respect to the flow resistance barrier, and provide for a uniform distribution of the flow of fluid across the entire wafer surface in reduced pitch processing.
  • Controlled fluid injection nozzles can be used in conjunction with the flow resistance barrier described herein to provide for uniform flow distribution across the wafer surface, or the controlled fluid injection nozzles can be used alone to provide a desired flow distribution throughout the processing vessel. Baffles or other flow control devices could also be used.
  • the velocity profile of the cleaning or rinsing fluids entering the single bath must be - 6 - controlled in such a manner to overcome the high flow resistance found in sections of the bath.
  • the highest resistance is found in the middle of the wafers (i.e., largest cross section) and the middle of the stack.
  • Another step of the invention that can be used to provide for a uniform flow of wet processing fluids across a wafer stack arranged in less than one-half pitch spacing is to use megasonics during the chemical soaking of the wafers.
  • the acoustic streaming that is developed during processing by the use of megasonics assists in the distribution of chemicals between the wafers.
  • ultrasound around 500 KHz to 1 MHZ is distributed in a known manner through the cleaning fluid to dislodge particles on the wafer surface.
  • Other frequencies or mixing techniques could be used to overcome the large boundary layers found between the wafers when high flow resistance is present.
  • Another step of the invention that can be used to provide for a uniform flow of wet processing fluids across a wafer stack arranged in less than one-half pitch spacing is to use very high injection flow rates for the processing fluids.
  • very high chemical injection flow speeds because of the momentum of the flow the chemicals are forced between the wafers that are spaced closely together in a one-third or one-half pitch arrangement.
  • Preferred chemical injection flow rates to provide for efficient reduced pitch wet processing in a single vessel are 18 to 30 gpm in a wafer carrier with 100 - 300 mm wafers at pitch (i.e., .18-.30 gpm per wafer).
  • Another step of the invention that can be used to provide for a uniform flow of wet processing fluids across a wafer stack arranged in less than one-half pitch spacing is to inject chemicals in a time sufficient to achieve equilibrium conditions in the processing area of the vessel.
  • concentration of chemicals in the middle of the wafers will be about equal to the concentration of chemicals at the edge of the wafers.
  • Preferred chemical injection times to provide for efficient - 7 - reduced pitch wet processing in a single vessel are from 60 second injection times to 120 second injection times depending on the flow rate and vessel size.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

The present invention is directed to wet processing methods for the manufacture of electronic component precursors, such as semiconductor wafers used in integrated circuits. More specifically, this invention relates to methods of manufacturing electronic component precursors using wet processing techniques that provide for uniform flow distribution across wafers arranged in one-third and one-quarter pitch spacing.

Description

WET PROCESSING METHODS FOR THE MANUFACTURE OF ELECTRONIC COMPONENTS
Field Of The Invention
The present invention is directed to wet processing methods for the manufacture of electronic components and electronic component precursors, such as semiconductor wafers used in integrated circuits. More specifically, the present invention relates to improved processes for the enclosed flow-line treatment of substrates with fluids, such as semiconductor wafers and flat panel display.
Background Of The Invention
Wet processing is used extensively during the manufacture of integrated circuits, which typically comprise electronic component precursors such as semiconductor wafers, flat panels, and other electronic component precursors. Generally, the electronic component precursors are placed in a bath or a vessel and then contacted with a series of reactive chemical process fluids and rinsing fluids. The process fluids may be used, without limitation, for etching, photo resist stripping, and prediffusion cleaning and other cleaning steps of the electronic component precursors. An example of a treatment system for electronic component precursors is described in U.S. Patent No. 4,633,893 - McConnell et al., which is herein incorporated by reference as if set forth in its entirety.
In a typical wet processing technique, the electronic component precursors are treated in either a full flow vessel (a vessel closed to the environment), single tank, a wet bench, or bath. In typical wet processing techniques, the electronic component precursors are exposed to reactive chemical process fluids to either remove (i.e., clean) contamination on the electronic component precursors or to etch some part of the surface. After this cleaning or etching is performed, the chemical will adhere to the surface or - 2 - surfaces of the electronic component precursors. The adhered chemical must then be removed before treating the electronic component precursors with the next reactive chemical process fluid so that the chemical residue does not contaminate the next reactive chemical process. Traditionally, the adhered chemical is removed using deionized (Dl) water.
In the production of electronic components and electronic component precursors, there is a trend toward the development and use of more compact processing equipment, as well as the application of more compact processes. Advances in compact processing equipment are tempered, however, by the trend toward increased productivity in the use of larger (i.e., 300 mm) precursor wafers. Two generally known approaches toward compactness in equipment are spray processing and single bath immersion. With the advent of smaller chip geometry and larger wafer processing, the use of single bath processing has become beneficial from a manufacturability standpoint. Immersion benches for wet processing using multiple baths and rinsing tanks typically have relatively large tank volumes that can accommodate 200 mm wafers spaced at 6.25 mm in a full load. The standard wafer pitch for 300 mm wafers is 10 mm in a full load. Full-flow processors employing a single processing vessel have small vessel sizes such that the wafer pitch is one-half that of the pitch of wafers processed in an immersion tank. This processing at a reduced pitch in full-flow single processing vessels is desirable due to attendant reductions in water and chemical consumption. Moreover, since the flow velocity for an equivalent total flow volume within a single vessel will be increased for reduced pitch processing, rinsing of the wafers will improve accordingly. Thus, single vessel processing of wafers at less than one half the standard pitch, such as at one-third and one-quarter pitch processing, is even more desirable than the known one-half pitch processing systems. Reducing the pitch during wet processing to one-third or one-quarter of the standard wafer cassette pitch provides a reduction in water and chemical consumption by an equivalent factor of one-third and one-quarter, respectively. As discussed, the flow velocity will be increased by a factor of three for processing at one-third pitch and by a factor of four for one-quarter pitch processing. - 3 -
Single vessel processing of wafers at a pitch that is less than one- half the standard pitch, however, has not been shown to be acceptable in the past due to problems associated with such reduced pitch processing in the single vessel. During wet processing at one-third and one-quarter pitch, it has been found that there is an undesirable tendency for the flow to pass around the wafers. Non-uniformity of the flow of processing fluids around the wafers causes non-uniformity of etching and rinsing of the wafers. The non-uniform flow of processing fluids resulting from reduced pitch wet processing has made processing of 300 mm wafers in full-flow single processing vessels not achievable within desired levels of productivity and costs.
Thus, there is a need in the art for a processing method that permits the efficient treatment of electronic component precursors, such as 300 mm wafers, in a single processing vessel where the wafer pitch can be less than one- half the standard pitch for such wafers. The present invention addresses these as well as other needs.
Summary Of The Invention
The present invention presents, inter alia, wet processing methods for the manufacture of electronic components and electronic component precursors, such as semiconductor wafers used in integrated circuits. More specifically, this invention relates to methods of, for example, cleaning electronic component precursors using wet processing techniques where wafers having a pitch that is less than one-half the standard wafer pitch are effectively processed in a single processing vessels.
Detailed Description Of The Invention The apparatus and operation of a full-flow single processing vessel for the treatment of electronic component precursors such as semiconductor wafers is described in the McConnell patent identified above. The present invention, however, is not intended to be limited to the treatment vessel described in this patent. Apparatus are known in the art for transferring wafers from a standard cassette for processing in cassette carriers in the described processing . 4 .
vessel where the wafer pitch is reduced from the standard pitch to distances such as of one-half pitch, one-third pitch, and one-quarter pitch.
As described above regarding wet processing in single vessel processing systems, where the wafer pitch is less than one-half the standard wafer pitch there is an undesirable tendency for the flow to pass around the wafers stacked in the vessel. The reduced pitch of the wafers has been found to increase the resistivity of the flow path through the wafers, resulting in the flow of processing fluids around the wafers. It has been discovered that the increased flow resistance is highest in the middle of the wafers. In reduced pitch processing in accordance with the present invention, to provide a uniform flow of processing fluids across the wafers in a single vessel system, a flow resistance barrier is secured within the wafer vessel housing, upstream of the wafer stack. The wafer stack could be a cassette of 300 mm wafers arranged at one-half the standard pitch for such wafers, and the stack is more preferably a cassette of 300 mm wafers arranged at one-third pitch or one-quarter pitch. The flow resistance barrier is designed such that fluid flowing upward through the barrier, prior to flow through the wafers, is distributed to push the flow toward the middle of the wafers, where the flow resistance is the highest. In a most preferred embodiment, the flow resistance barrier is a screen of any suitable porous material where the holes in the screen are larger in the center of the screen (where the pressure in the chamber is higher) than the holes at the sides of the screen (where the pressure is lower). Also, the holes in the screen can be spaced closer together in the center of the screen and spaced at a greater distance at the sides of the screen to allow more flow to enter the chamber where the pressure is higher and less flow to enter where the pressure is lower. In this embodiment, the hole size can be the same throughout the screen or can be variable to provide a desired flow pattern. Preferably, the hole pattern and the size of the holes are selected to provide the least resistance to the flow of fluid in the middle of the wafers and the most resistance to fluid flow at the sides of the wafers. As described in the above-mentioned U.S. Patent No. 4,633,893, it is preferable that the flow resistance barrier be designed to impart plug flow conditions for the flow of fluid onto the wafer. The number, shape, size - 5 - and arrangement of the holes within the screen can be selected by one skilled in the art based upon the flow parameters to accentuate the flow of fluids toward the center of the wafers. These parameters include the size and shape of the vessel, the chemical composition of the fluids in use, the flow velocity, and the flow pressure. It is preferred that the hole size be large enough to allow dissolved gas in the liquid to pass through the screen. Holes can be made in the barrier material using a laser or by known hole punching apparatus.
Preferred materials for the flow resistance barrier include woven fabric material, to minimize blockage of the flow of fluid at the barrier, and a fiber mesh material wherein the fibers are distributed throughout the flow resistance barrier in a random fiber mesh. Because manufacturing imperfections in the flow resistance barrier can become dislodged from the barrier over time, thus adding contaminants into the treatment vessel, and can also trap chemicals thereon, thus clogging the barrier, a woven fabric material, which will generally have relatively few manufacturing imperfections, is a most preferred material for the flow resistance barrier. In another preferred embodiment, the flow resistance barrier is a chemical resistant polymeric screen material, with Teflon being the most preferred polymeric material. It is preferred that the flow resistance barrier be chemically resistant to the various chemicals used in the wafer treatment operations so as to avoid chemical degradation of the barrier material.
In another embodiment of the invention, flow injection apparatus such as controlled injection nozzles positioned in the processing vessel provide for increased flow of fluids into the middle of the wafers. The location and output parameters of the injection nozzles are determined based upon the known flow parameters described above with respect to the flow resistance barrier, and provide for a uniform distribution of the flow of fluid across the entire wafer surface in reduced pitch processing. Controlled fluid injection nozzles can be used in conjunction with the flow resistance barrier described herein to provide for uniform flow distribution across the wafer surface, or the controlled fluid injection nozzles can be used alone to provide a desired flow distribution throughout the processing vessel. Baffles or other flow control devices could also be used. In general the velocity profile of the cleaning or rinsing fluids entering the single bath must be - 6 - controlled in such a manner to overcome the high flow resistance found in sections of the bath. In the case of wafers, the highest resistance is found in the middle of the wafers (i.e., largest cross section) and the middle of the stack. Another step of the invention that can be used to provide for a uniform flow of wet processing fluids across a wafer stack arranged in less than one-half pitch spacing is to use megasonics during the chemical soaking of the wafers. The acoustic streaming that is developed during processing by the use of megasonics assists in the distribution of chemicals between the wafers. During this processing step, ultrasound around 500 KHz to 1 MHZ is distributed in a known manner through the cleaning fluid to dislodge particles on the wafer surface. Other frequencies or mixing techniques could be used to overcome the large boundary layers found between the wafers when high flow resistance is present.
Another step of the invention that can be used to provide for a uniform flow of wet processing fluids across a wafer stack arranged in less than one-half pitch spacing is to use very high injection flow rates for the processing fluids. By using very high chemical injection flow speeds, because of the momentum of the flow the chemicals are forced between the wafers that are spaced closely together in a one-third or one-half pitch arrangement. Preferred chemical injection flow rates to provide for efficient reduced pitch wet processing in a single vessel are 18 to 30 gpm in a wafer carrier with 100 - 300 mm wafers at pitch (i.e., .18-.30 gpm per wafer).
Another step of the invention that can be used to provide for a uniform flow of wet processing fluids across a wafer stack arranged in less than one-half pitch spacing is to inject chemicals in a time sufficient to achieve equilibrium conditions in the processing area of the vessel. By the use of relatively long chemical injection times, compared with standard injection times, even though the chemicals may at first flow in a non-uniform manner across the wafers, after equilibrium has been reached the concentration of chemicals in the middle of the wafers will be about equal to the concentration of chemicals at the edge of the wafers. Preferred chemical injection times to provide for efficient - 7 - reduced pitch wet processing in a single vessel are from 60 second injection times to 120 second injection times depending on the flow rate and vessel size.
The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof and, accordingly, reference should be made to the appended claims, rather than to the foregoing specification, as indicating the scope of the invention.

Claims

- 8 -What is claimed is:
1. A method for the manufacture of electronic component precursors, comprising: a) transferring the electronic component precursors from a carrying cassette where the precursors are separated by a predetermined pitch distance to a processing cassette where the precursors are separated by a pitch distance that is less than one-half the predetermined pitch distance; b) placing the electronic component precursors in the processing cassette in a vessel for wet processing; c) injecting the processing fluid through a screen positioned in the vessel upstream of the electronic component precursors wherein the screen has holes arranged in a pattern to provide a relatively high resistance to the flow of fluid through the sides of the screen and a relatively low resistance to the flow of fluid through the center of the screen, whereby processing fluid is distributed uniformly across the entire surface of the electronic component precursors.
2. The method of claim 1 , wherein the holes in the center of the screen are larger than the holes in the sides of the screen.
3. The method of claim 1 , wherein the holes in the center of the screen are spaced closer together than the holes in the sides of the screen.
4. The method of claim 1 , further comprising the step of exposing the electronic component precursors to energy having a frequency of about 1 MHZ for a selected period of time.
5. The method of claim 1 , wherein the processing fluid is injected into the vessel at a flow rate that is proportional to the number of wafers in the carrier.
6. The method of claim 1 , wherein the processing fluid is injected into the vessel until chemical equilibrium is substantially achieved within the processing area of the vessel containing the electronic component precursors.
7. An apparatus for treating a plurality of substantially planar substrates with a flow of fluid, said apparatus comprising: a) a fluid inlet; b) a vessel in flow communication with said fluid inlet for receiving said flow of fluid from said fluid inlet, said substrates disposed within said vessel; and c) a flow resistance barrier positioned in the vessel upstream of the substrates wherein the barrier has holes arranged in a pattern to provide a relatively high resistance to the flow of fluid through the sides of the barrier and a relatively low resistance to the flow of fluid through the center of the barrier, whereby processing fluid is distributed uniformly across the entire surface of the substrates.
8. The apparatus of claim 7, wherein the holes in the center of the barrier are larger than the holes in the sides of the barrier.
9. The apparatus of claim 7, wherein the holes in the center of the barrier are spaced closer together than the holes in the sides of the barrier.
10. The apparatus of claim 7, wherein the barrier is comprised of a woven fabric material.
11. The apparatus of claim 7, wherein the barrier is a chemical resistant polymeric screen material.
12. The apparatus of claim 7, wherein the barrier is comprised of Teflon.
PCT/US1999/009722 1998-05-04 1999-05-04 Wet processing methods for the manufacture of electronic components WO1999057754A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP99920316A EP1078394A1 (en) 1998-05-04 1999-05-04 Wet processing methods for the manufacture of electronic components
AU37842/99A AU3784299A (en) 1998-05-04 1999-05-04 Wet processing methods for the manufacture of electronic components
JP2000547648A JP2002514828A (en) 1998-05-04 1999-05-04 Wet treatment method for manufacturing electronic components

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US8409798P 1998-05-04 1998-05-04
US09/304,587 1998-05-04
US60/084,097 1998-05-04
US30458799A 1999-05-04 1999-05-04

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4633893A (en) * 1984-05-21 1987-01-06 Cfm Technologies Limited Partnership Apparatus for treating semiconductor wafers
US4838979A (en) * 1986-09-19 1989-06-13 Dainippon Screen Mfg. Co., Ltd. Apparatus for processing substrate surface
US4906328A (en) * 1987-07-16 1990-03-06 Texas Instruments Incorporated Method for wafer treating
US5227001A (en) * 1990-10-19 1993-07-13 Integrated Process Equipment Corporation Integrated dry-wet semiconductor layer removal apparatus and method
US5286657A (en) * 1990-10-16 1994-02-15 Verteq, Inc. Single wafer megasonic semiconductor wafer processing system
US5318632A (en) * 1992-05-25 1994-06-07 Kawasaki Steel Corporation Wafer process tube apparatus and method for vertical furnaces
US5702618A (en) * 1993-10-04 1997-12-30 Research International, Inc. Methods for manufacturing a flow switch
US5745946A (en) * 1994-07-15 1998-05-05 Ontrak Systems, Inc. Substrate processing system
US5868854A (en) * 1989-02-27 1999-02-09 Hitachi, Ltd. Method and apparatus for processing samples

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4633893A (en) * 1984-05-21 1987-01-06 Cfm Technologies Limited Partnership Apparatus for treating semiconductor wafers
US4838979A (en) * 1986-09-19 1989-06-13 Dainippon Screen Mfg. Co., Ltd. Apparatus for processing substrate surface
US4906328A (en) * 1987-07-16 1990-03-06 Texas Instruments Incorporated Method for wafer treating
US5868854A (en) * 1989-02-27 1999-02-09 Hitachi, Ltd. Method and apparatus for processing samples
US5286657A (en) * 1990-10-16 1994-02-15 Verteq, Inc. Single wafer megasonic semiconductor wafer processing system
US5227001A (en) * 1990-10-19 1993-07-13 Integrated Process Equipment Corporation Integrated dry-wet semiconductor layer removal apparatus and method
US5318632A (en) * 1992-05-25 1994-06-07 Kawasaki Steel Corporation Wafer process tube apparatus and method for vertical furnaces
US5702618A (en) * 1993-10-04 1997-12-30 Research International, Inc. Methods for manufacturing a flow switch
US5745946A (en) * 1994-07-15 1998-05-05 Ontrak Systems, Inc. Substrate processing system

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