WO1999054011A1 - Systeme reseau base sur des groupes et procede d'utilisation correspondant - Google Patents

Systeme reseau base sur des groupes et procede d'utilisation correspondant Download PDF

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Publication number
WO1999054011A1
WO1999054011A1 PCT/US1999/008316 US9908316W WO9954011A1 WO 1999054011 A1 WO1999054011 A1 WO 1999054011A1 US 9908316 W US9908316 W US 9908316W WO 9954011 A1 WO9954011 A1 WO 9954011A1
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WO
WIPO (PCT)
Prior art keywords
video gaming
group
bus network
computer
bus
Prior art date
Application number
PCT/US1999/008316
Other languages
English (en)
Inventor
Robert W. Clemens
Ronald Kingham
Original Assignee
Thunderwatch Partnership
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thunderwatch Partnership filed Critical Thunderwatch Partnership
Priority to AU35640/99A priority Critical patent/AU3564099A/en
Publication of WO1999054011A1 publication Critical patent/WO1999054011A1/fr

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Classifications

    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F17/00—Coin-freed apparatus for hiring articles; Coin-freed facilities or services
    • G07F17/32—Coin-freed apparatus for hiring articles; Coin-freed facilities or services for games, toys, sports, or amusements

Definitions

  • the present invention relates in general to a group based network system and a method of using it. It more particularly relates to a group based video gaming network system and method, which enables a large group of users to play a pari- mutuel and other games utilizing a large group of video gaming machines in a highly efficient and effective manner.
  • Background Art
  • Video gaming machines have become popular, and enable users to play a variety of different types of games, such as video poker.
  • the video game machines are challenging and interesting to the user, and enable the users to wager and win individual games as well as special jackpot pools.
  • video gaming machines have enabled users to play pari-mutuel games on a given machine.
  • video gaming machines have enabled users to play pari-mutuel games on a given machine.
  • U.S. patent application entitled "PARI-MUTUEL GAMING SYSTEM AND METHOD OF USING SAME,” Serial
  • Such a pari-mutuel game can also be played utilizing a large number of video gaming machines, at the same location or distributed amongst other locations.
  • a common jackpot pool for a large number of machines can accumulate more rapidly, and thus the larger size jackpot pool is more entertaining and rewarding to the users.
  • the principal object of the present invention is to provide a new and improved group based network system and a method of using it, wherein machines such as video gaming machines can be networked for pari-mutuel or other games so that a large group of video gaming machines can be played simultaneously and all of the games can be updated with current information in real time almost instantaneously without unwanted delays.
  • Another object of the present invention is to provide such a new and improved video gaming machine and method, wherein additional video gaming machines can be added to the system without degrading the overall performance of the system.
  • Still another object of the present invention is to provide a new and improved video gaming system and method of using it, wherein large amounts of data can be obtained remotely from selected video gaming machines, even during the playing of the pari-mutuel games.
  • the above and further objects of the present invention are realized by providing a new and improved group based network system and a method of using it, wherein an improved high-speed network arrangement facilitates the simultaneous playing of pari-mutuel and other games by a large group of video gaming machines.
  • Bulk information such as the video gaming machine book information, for each machine can be remotely accessed, even during the playing of the pari-mutuel game.
  • the novel network system provides an open architecture concept to permit the addition of new video gaming machines without degrading performance of the system.
  • a group based system and method of using it are disclosed, and relate to a group of video gaming machines enabling users to play pari-mutuel and other video games with all other users of the group simultaneously.
  • a bus converter interconnects each one of the video gaming machines to a bus network, and a concentrator controller connects a computer in communication with the bus network for enabling the video gaming machines to upload current game information continuously to the computer in real time for updating pari-mutuel jackpot information and for downloading current pari-mutuel jackpot information to each one of the video gaming machines in real time.
  • the bus converter provides for low speed messages from the video gaming machines and for re-formatting the messages in a high speed format for communication with the computer.
  • FIG. 1 is a block diagram of the group based network system, which is constructed in accordance with the present invention
  • FIG. 2 and 3 are flow chart diagrams of the method of controlling the system of FIG. 1;
  • FIGS. 4 and 5 when arranged as showing in FIG. 6, is a symbolic block diagram of a bus converter
  • FIGS. 7-11 when arranged as shown in FIG. 12, comprise a symbolic block diagram of a concentrator controller of the system of FIG. 1.
  • FIG. 1 a group based network system 110, which is constructed in accordance with the present invention, and which is used in the preferred form of the invention as a group based network video gaming system to enable a large number of users to play video games simultaneously.
  • the group based network system 110 generally comprises a series of concentrator groups, such as the concentrator groups 112 and 114, each including a group of video gaming machines, such as the video gaming machines 115, 117, 120 and 122 of the concentrator group 112.
  • the video gaming machines may be of the type as disclosed in the forementioned co-pending U.S. patent application, now U. S. patent .
  • a set of bus network converters such as converters 116, 118, 121 and 123 interconnect their respective video gaming machines, such as the respective machines 115, 117, 120 and 122, to a group bus network 125 in a daisy chain configuration.
  • a group concentrator computer 127 is connected via a group concentrator controller 129 to the group bus 125 in the daisy chain configuration with the other converters for the gaming machines.
  • the concentrator controller 129 supplies voltage and ground potential for the devices connected to the bus 125, and data SDA and clock SCL information are connected in parallel via each device connected to the bus 125 in accordance with I 2 C protocol.
  • the computer 127 is preferably a personal computer, and the controller 129 is a card mounted therein.
  • the group concentrator computer 127 services up to 32 video gaming machines within the same concentrator group 112 in the preferred form of the invention, but it is to be understood that a larger or smaller number of machines may be included in each group. Additional video gaming machines (not shown) can be added to the bus 125 in an open architecture configuration. Similarly, additional concentrator groups (not shown) can also be added.
  • the group concentrator computer 127 and its controller 129 can be connected at any point along the group bus network 125, and also if preferred, can be interconnected to the bus 125 at the end of the daisy chain of video gaming machine converters. In the preferred form of the invention as shown and described herein, the controller 129 is connected intermediate the ends of the bus network 125.
  • a host server computer 132 communicates via a high speed host bus 134 with the concentrator computers of each one of the concentrator groups.
  • a group of personal computers 136, 138, 141 and 143 are connected to the high speed host bus 134 to enable access to the host computer 132 for generating reports as required, and also to perform other administrative functions in connection with the system 110.
  • game information is uploaded from the video gaming machines via the concentrator computers of each concentrator group to the host computer.
  • the host computer includes software for utilizing the gaming information to update jackpot information and other information required by the video gaming machines.
  • jackpot information and other information can be updated in real time, and then supplied from the host computer via the concentrator computers to the individual ones of the video gaming machines.
  • the game information provided by the video gaming machines being played is supplied at a low speed, such as 9600 baud to its converter.
  • the converter is then operated together with the controller utilizing I C protocol to communicate at 90,000 baud via the I 2 C bus network 125.
  • the host bus 134 is a conventional computered network bus, such as Ethernet, which operates at a high rate of speed, such as 10 Meg baud. In this manner, a large number of slower speed video gaming machines can communicate with a single host computer, even though the individual video gaming machines are operating at a relatively low rate of speed.
  • the group I 2 C bus network serves as a bridge between the relatively low speed video gaming machines and the high speed host bus.
  • the host bus 134 together with the intermediate speed I 2 C bus network 125, enable large volumes of data to be communicated continuously between the host computer and the large number of slow speed video gaming machines interactively.
  • FIG. 2 there is shown the operation of the controller down loading a message originating from the host computer 134 via the concentrator computer 127 to a video gaming machine under the control of the I C protocol for the bus network 125.
  • a communication session is commenced by first determining whether the group bus network is ready to accept a message as indicated at 213. If the bus network 125 of the group 112 is not ready for a message to be sent due to the fact that a message is already being communicated via the bus network, then there is a loop back to the start position at 211 to allow for a re-try for sending the message. The operation is repeated until the bus network 125 is available to transmit a message.
  • the controller 129 has a computer message to be sent from its concentrator computer 127 which received it from the host computer 132 via the high speed bus 134, and that computer message is the next available message in the queue. As a result, that computer message is then prepared to be sent.
  • a header and checksum is added to the message to prepare a data packet for transmission over the bus network 125.
  • the header includes the address of a desired one of the video game machine converters, or alternatively, the header address can include a broadcast mode where every one of the video gaming machine converters will receive and utilize the message to be sent.
  • the computer message is thus transferred from the memory (not shown) in the concentrator computer to the controller, which in turn adds the header and checksum.
  • the packet is transmitted over the group bus network to the desired one or more of the video gaming machine converters.
  • acknowledgment messages are returned over the group bus network back to the controller 129 to indicate that the message has been received.
  • the data packet is parsed by deleting the header and the checksum from the computer message so that it can be utilized by the video gaming machine.
  • the message can be in the form of a serial RS 232 serial bit message.
  • the serial RS 232 message is then, in turn, sent to the video gaming machine.
  • the messages are arranged in a queue and once the video gaming machine is ready to receive the next message, the message is sent when the next available message in the queue is serviced as indicated at 224.
  • the operation starts at 312 and a decision is made whether or not a message is present from a video gaming machine such as the video gaming machine 117 via its converter 118.
  • a serial message is sent from the video gaming machine 117 to the converter 118, as indicated at 316
  • the message is formatted by adding a header and a checksum to assemble a packet for transmission via the group bus network 125. It is first determined whether the bus 125 is ready. If it is not ready, the determination is made repeatedly until the bus becomes available for the transmission of the next available message to be sent.
  • the first available packet in the queue is sent via the bus 125 to the group concentrator controller 129.
  • the received packet at the controller 129 is parsed by deleting the header and checksum.
  • the message is transferred to the group concentrator computer 127.
  • the message is then sent from the computer 127 via the host bus 134 to the host server computer 132.
  • all of the video gaming machines of the concentrator group 123 are continuously sending messages via the group concentrator computer 127 to the host server computer 132.
  • the host server computer 132 is similarly receiving messages from all of the video gaming machines of all the concentrator groups.
  • the computer 132 can, amongst other things, compute jack pot pool information currently in real time, and then down load the updated information in a reverse direction via the host bus 134 to each one of the bus concentrator groups via their individual group concentrator computers and controllers to each one of the bus converters and their individual video gaming machines. In this manner, each video gaming machine then is being updated continuously with current updated information based upon sessions occurring in each one of the video gaming machines as they are being played.
  • the converter 118 may have a pair of video gaming machine port 410 and 412 coupled to a micro-controller 514 which includes an imbedded programmable read-only-memory (not shown) for controlling the operation of the converter 118.
  • the port 410 is an RS 232 serial port
  • the port 412 is an RS 422 port.
  • An RS 232 interface 421 interconnects the port 410 with the micro-controller 514.
  • an interface 422 interconnect the port 412 with the micro- controller 514. Both interfaces are connected to the pins 11, 13 and 14 of the micro-controller 514.
  • a pair of ports 510 and 512 are connections to the group bus network 125.
  • the port 512 is connected via the bus network 125 to the converter 116, and the port 510 is connected to the group concentrator controller 129. It should be understood that the port 510 could also be connected to another converter.
  • a pair of bi-directional bus drivers 516 and 518 are connected between input/output pins 8 and 9 of the micro-controller 514 and the ports 510 and 512 to the group bus network 125. The bus drivers 516 and 518 provide a proper level of current for the 10 bus network 125.
  • a pair of current limiting resistors 521 and 523 are connected between the respective bus drivers 516 and 518 and a voltage source VCC in the form of a voltage regulator 432 having the regulated and capacitance filtered output VCC.
  • a reset circuit generally indicated at 423 includes a pair of transistors 525 and
  • the transistor 525 is reset from the bus 125 via pin 5 of either the port 510 or the port 512. When energized, the transistor 425 conducts to extend a signal to a reset pin 10 of the micro-controller 514 to reset it remotely via the bus 125.
  • a reset signal from the video gaming machine 117 via the port 412 and the interface 422 causes the transistor 427 to conduct for sending a signal to the reset pin 10 of the microcontroller 514 for resetting it from the video gaming machine 117.
  • a pair of external power supply jacks 434 provide an external source of power for the voltage regulator 432 to energize the converter 118.
  • the video gaming machine 117 and its converter 118 can be disconnected from the bus 125, and yet the bus 125 can remain functional.
  • a set of trouble indicators 125 are energized by the micro-controller 514.
  • a crystal 527 sets the baud rate for the micro-controller 514.
  • a jumper block 529 when suitably connected, determines the baud rate, and is connected to the pins 15 and 17 for the micro-controller 514.
  • the controller 129 includes a concentrator computer ISA port bus indicated at 710 and 810 for enabling the concentrator computer 127 to communicate in parallel form with an I 2 C UART unit 911 being programmed for the I 2 C protocol to help control the asynchronous serial transfer of information along the group bus network 125.
  • a pair of bus ports 1113 and 1115 are connected via the bus 125 to the respective converters 118 and 121.
  • a pair of bi-directional bus drivers 1110 and 1111 interconnect the data port SDA and the clock port SCL of the UART unit 911 with pins 1 and 3 of both the bus ports 1113 and 1115 for communication along the bus 125.
  • the pair of bi-directional bus drivers 1110 and 1111 are connected between the unit 911 and the pair of bus ports 1113 and 1115, which are connected via the bus network 125 to the respective converters 118 and 121.
  • a constant current source generally indicated at 1120 including transistors 1122 and 1124 provides a constant current at respective pins 1 and 3 for the group bus 125 for the respective bi-directional bus drivers 1110 and 1111.
  • the transistors 1122 and 1124 enable a fast rise time to be achieved by the transition of binary signals on the data lead SDA and the clock lead SCL respectively. In this regard, a one microsecond rise time can be realized, even when the converters are spaced widely apart from one another.
  • the controller 129 enables bi-directional communication of messages between the group concentrator computer 127 and the converters for the individual video gaming machines.
  • messages from the computer 127 are sent in a parallel manner to the UART unit 911, which in turn sends the messages in serial form via synchronous transmission via the bus 125 to either a selected one of the gaming 12 machines, or to all of them simultaneously.
  • the controller 129 is operating as a master, and one or more of the converters are acting as slaves.
  • the direction of communication can be reversed when one or more of the converters act as masters and send serial video gaming machine messages to the controller 129 via the bus 125, which in turn sends the message to the computer 127 in parallel format via the ISA bus ports 710 and 810 under the control of the I 2 C UART unit 911.
  • parallel message data D0-D7 is communicated between pins Al- A9 of the ISA port 710 and respective pins 7, 8, 9, 11, 12, 13, 14 and 15 of the unit 911 in a bi-directional manner.
  • the address information A2-A9 of the message is supplied from the ISA port to the respective inputs 2, 4, 6, 8, 11, 13, 15 and 17 of the matching decoder 712.
  • a NAND gate 913 is enabled to activate pin 17 of the UART unit 911 via the inverter 915 to enable the parallel data D0-D7 to be supplied to it.
  • the unit 911 includes WR pin 18 and RD pin 16 for write and read operations respectively.
  • Decode registers 812 comprising registers 814, and 816 receive address information from the computer port to a NDR gate 1000 and a NAND gate 1001.
  • the flip-flops 1003 and 1005 de-code the initiation of a reset.
  • a NAND gate 1007 responds to the flip-flop 1003 to reset the UART unit 911 at a reset pin 19.
  • a reset circuit generally indicated at 1117 is connected to the pins 5 for the bus ports 1113 and 1115 for generating a bus reset signal BUSRST for resetting the bus 125.
  • the circuit 1117 includes a transistor 1119 controlled by the flip-flop 1005, which responds to the reset signal from the computer 127 for resetting the bus 125.
  • An inverter gate 917 supplies an interrupt signal from an interrupt pin 5 of the
  • An external power connector 716 enables power to be connected to the controller 129 if needed.
  • a filter 1126 is employed for regulating the power supply to the constant current generator 1120.
  • I 2 C BUS NETWORK DETAILED DESCRIPTION The operation of the I C bus network 125 of the system 110 will now be described.
  • Bus network 125 is an 1 2 C bus network, which is a two wire, serial data (SDA) and serial clock (SCL) bus, to carry information between the devices connected to the bus.
  • SDA serial data
  • SCL serial clock
  • Each device is recognized by a unique address - whether its a micro-controller, LCD driver, memory or keyboard interface.
  • devices can also be considered as masters or slaves when performing data transfers.
  • a master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.
  • the 1 2 C bus network 125 is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it.
  • the master-slave and receiver-transmitter relationships will now be considered relative to the 1 2 C bus network 125. It should be noted that these relationships are not permanent, but only depend on the direction of data transfer at that time. The transfer of data proceeds as follows:
  • device A sends information to device B : device A (master), address device B (slave) - device A (master-transmitter), sends data to device B (slave- receiver) device A terminates the transfer.
  • device A desires to receive information from device B : device A (master) addresses device B (slave) 14 device A (master-receiver) receives data from device B (slave- transmitter) device A terminates the transfer. Even in this case, the master (device A) generates the timing and terminates the transfer.
  • the clock signals during arbitration are a synchronized combination of the clocks generated by the master's using the wired AND connection to the SCL line.
  • Generation of clock signals on the 1 2 C bus network 125 is always the responsibility of master devices; each master generates its own clock signals when transferring data on the bus.
  • Bus clock signals from a master can only be altered when they are stretched by a slow-slave device holding down the clock line, or by another master when arbitration occurs.
  • Both SDA and SCL lines are bi-directional lines, connected to a positive supply voltage via a pull-up resistor 1128 to ground (see FIG. 11) in the controller 129.
  • both lines are HIGH
  • the output stages of devices connected to the bus must have an open-drain or open-collector in order to perform the wired AND function.
  • the data on the SDA line must be stable during the HIGH period of the clock.
  • the HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW.
  • a LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition, START and STOP conditions are always generated by the master.
  • the bus is considered to be busy after the START condition.
  • the bus network 125 is considered to be free again a certain time after the STOP condition.
  • the SDA line is sampled at least twice per clock period in order to sense the transition.
  • Every byte provided to the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte must be followed by an acknowledged bit. Data is transferred with the most significant bit (MSB) first. If a receiver cannot receive another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the clock line SCL LOW to force the transmitter into a wait state. Data transfer then continues when the receiver is ready for another byte of data and releases clock line SCL. In some cases, a different format from the 1 2 C bus network format is permitted. A message which starts with such an address can be terminated by generation of a STOP condition, even during the transmission of a byte, in this case, no acknowledge is generated.
  • MSB most significant bit
  • the acknowledge-related clock pulse is generated by the master.
  • the transmitter releases the SDA line (HIGH) during the acknowledge clock pulse.
  • the receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. Setup and hold times must also be taken into account. Usually, a receiver which has been addressed is required to generate an acknowledge after each byte has been received except when the message starts with a CBUS address.
  • the 16 data line When a slave receiver fails to acknowledge the slave address (for example, when it is unable to receive because it is performing some real time function), the 16 data line must be left HIGH by the slave. The master can then generate a STOP condition to abort the transfer.
  • a master-receiver If a master-receiver is involved in a transfer, it must signal the end of the data to the slave transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. The slave transmitter must release the data line to allow the master to generate the STOP condition.
  • a synchronized SCL clock is generated with its LOW period determined by the device with the longest clock LOW period, and its HIGH period determined by the one with the shortest clock HIGH period.
  • a master may start a transfer only if the bus is free. Two or more masters may generate a START condition within the minimum hold TIME (t H os ⁇ A ) of the START condition which results in a defined START condition to the bus. Arbitration takes place on the SDA line, while the SCL line is at the HIGH level, in such a way that the master which transmits a HIGH level, while another master is transmitting a LOW level will switch off its DATA output stage because the level on the bus does not correspond to its own level.
  • Arbitration can continue for many bits, its first stage is comparison of the address bits. If the masters are each trying to address the same device, arbitration continues with comparison of the data. Because address and data information on the 1 2 C bus network 125 is used for arbitration, no information is lost during this process. A master which loses the arbitration can generate clock pulses until the end of the bytes in which it losses the arbitration.
  • a master also incorporates a slave function and it loses arbitration during the addressing stage, it's possible that the winning master is trying to address it. The losing master must therefore switch over immediately to its slave-receiver mode. There may be an arbitration between two or more masters involved in an arbitration procedure (depending on how many masters are connected to the bus). The moment there is a difference between the internal data level of the master generating DATA and the actual level on the SDA line, its data output is switched off, which means that a HIGH output level is then connected to the bus. This will not affect the data transfer initiated by the winning master.
  • control of the 1 2 C bus network 125 is decided solely on the address and data sent by competing masters, there is no control master, nor any order of priority on the bus 125. Special attention must be paid if, during a series transfer, the arbitration procedure is still in progress at the moment when a repeated START 18 condition or a STOP condition is transmitted to the 1 2 C bus network 125. It is possible for such a situation to occur.
  • the masters involved must send this repeated START condition or STOP condition at the same position in the format frame. In other words, arbitration is not allowed between: - A repeated START condition and a data bit
  • the clock synchronization mechanism can be used to enable receivers to cope with fast data transfers on other bytes level or a bit level.
  • a device may be able to receive bytes of data at a fast rate, but requires more time to store a received byte or prepare another byte to be transmitted. Slaves can then hold the SCL line LOW after reception and acknowledgment of a byte to force the master into a wait state until the slave is ready for the next byte transfer in a type of handshake procedure.
  • a device can slow down the bus clock by extending each clock LOW period. The speed of any master is thereby adapted to the internal operating rate of this device.

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Abstract

L'invention concerne un système (110) basé sur des groupes et un procédé de son utilisation. Elle se rapporte à un groupe d'appareils de jeux vidéo (115, 117, 120, 122) qui permet aux participants de jouer aux jeux vidéo sur la base du pari mutuel ou autre, et ce simultanément avec tous les participants du groupe. Un convertisseur à bus (116, 118, 121, 123) connecte chacun des appareils de jeux vidéo à un réseau en bus (125), et un contrôleur concentrateur (129) connecte un ordinateur en communication avec le réseau bus (125) pour permettre aux appareils de jeux vidéo de télécharger les informations actuelles sur le jeu à destination de l'ordinateur, en continu et en temps réel, et ce pour mettre à jour les informations concernant le gros lot au pari mutuel et pour télécharger en temps réel les informations actuelles sur gros lot au pari mutuel à destination de chacun des appareils de jeux vidéo. Le convertisseur à bus se charge des messages basse vitesse provenant des appareils de jeux vidéo et du reformatage des messages au format haute vitesse, destiné à la communication avec l'ordinateur.
PCT/US1999/008316 1998-04-17 1999-04-15 Systeme reseau base sur des groupes et procede d'utilisation correspondant WO1999054011A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU35640/99A AU3564099A (en) 1998-04-17 1999-04-15 Group based network system and method of using same

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Application Number Priority Date Filing Date Title
US6220098A 1998-04-17 1998-04-17
US09/062,200 1998-04-17

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9836918B2 (en) 2000-10-19 2017-12-05 Igt Remote configuration of gaming terminals

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5497479A (en) * 1989-04-28 1996-03-05 Softel, Inc. Method and apparatus for remotely controlling and monitoring the use of computer software
US5655961A (en) * 1994-10-12 1997-08-12 Acres Gaming, Inc. Method for operating networked gaming devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5497479A (en) * 1989-04-28 1996-03-05 Softel, Inc. Method and apparatus for remotely controlling and monitoring the use of computer software
US5655961A (en) * 1994-10-12 1997-08-12 Acres Gaming, Inc. Method for operating networked gaming devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9836918B2 (en) 2000-10-19 2017-12-05 Igt Remote configuration of gaming terminals

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