WO1999050889A2 - Isolants imprimes pour dispositifs electroniques actifs et passifs - Google Patents

Isolants imprimes pour dispositifs electroniques actifs et passifs Download PDF

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Publication number
WO1999050889A2
WO1999050889A2 PCT/US1999/006454 US9906454W WO9950889A2 WO 1999050889 A2 WO1999050889 A2 WO 1999050889A2 US 9906454 W US9906454 W US 9906454W WO 9950889 A2 WO9950889 A2 WO 9950889A2
Authority
WO
WIPO (PCT)
Prior art keywords
printing
insulators
printed
insulator
further including
Prior art date
Application number
PCT/US1999/006454
Other languages
English (en)
Other versions
WO1999050889A3 (fr
Inventor
Sigurd Wagner
Helena Gleskova
Dashen Shen
Original Assignee
Trustees Of Princeton University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Trustees Of Princeton University filed Critical Trustees Of Princeton University
Priority to AU32031/99A priority Critical patent/AU3203199A/en
Publication of WO1999050889A2 publication Critical patent/WO1999050889A2/fr
Publication of WO1999050889A3 publication Critical patent/WO1999050889A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H01L21/02288—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating printing, e.g. ink-jet printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to methods of manufacturing macroelectronic products for the mass market where low cost is essential. Low cost is achieved by (a) using simple fabrication steps, (b) using few steps, and
  • TFT thin-film transistor
  • Printing in many forms has been applied to electronic products. Examples include the printed conductors on wire boards and printed compound semiconductors such as cadmium telluride for solar cells. However, no insulator has yet been printed as part of a transistor.
  • Insulators perform key functions in electrical, electronic and optoelectronic products. In semi-conductor electronics and optoelectronics, insulators may serve in only a passive function to prevent the flow of current, or in an active function as part of field effect devices.
  • the best-known active insulator is the gate dielectric in metal-oxide-silicon (MOS) storage capacitors and in MOS field effect transistors (MOSFETS).
  • MOS metal-oxide-silicon
  • MOSFETS MOS field effect transistors
  • Integrated circuits owe much of their present dominance to the development of the high-quality gate dielectric, which is thermally grown, native, silicon dioxide, and has a high-quality interface with the semiconductor silicon. Alternatives to this thermal silicon oxide have been sought for a variety of reasons.
  • One alternative is deposited silicon dioxide which has been pursued because it requires a smaller thermal budget than thermal silicon dioxide. Another alternative is required as the chip area per bit in dynamic memories keeps shrinking, because the necessary capacitance will have to be achieved by using insulators with higher dielectric constant than that of silicon dioxide.
  • a third alternative is used in amorphous silicon thin-film transistor technology, where thermal oxide is not compatible with the low-temperature processes used. The need for new active and passive insulators is evident in the nascent field of macroelectronics, also called large-area electronics or giant electronics.
  • Macroelectronic products will find their markets by having very low cost per area, rather than per function as is the case for conventional microelectronics.
  • Typical examples of future macroelectronic products include disposable, intelligent shipping/shopping labels, digital wallpaper, and dial-your-pattern dresses. Clearly, all of these must be made at low cost per area.
  • These products still must be inexpensive even when they include transistor electronics, input/output devices such as antennae, optoelectronic functions including photodetectors and light-emitting diodes, and microelectromechanical devices.
  • An analysis of the sources of cost shows that circuit costs can be brought down orders of magnitude below present-day cost if simple, rapid manufacturing techniques are combined with techniques that minimize materials consumption.
  • a process for printing gate dielectrics in thin film transistors is provided.
  • the dielectrics are based on organic polymers, and can be printed by several techniques, including xerographic printing and inkjet printing.
  • the maximum process temperature is approximately 160°C. This is considered a relatively low temperature, i.e. less that 200°C. Of course, the process temperatures are limited by the materials used and could be increased if materials permit.
  • This printing technique is appropriate for thin film transistor electronics and other macroelectronic circuits made on low-temperature substrates.
  • FIG. 1 is a diagram of a pattern for measuring the resistance of printed toner insulator.
  • FIG. 2 is a plot of the current- voltage characteristic of one of the crossovers of FIG. 1.
  • FIG. 3 is a schematic cross section through an MIS capacitor that incorporates a printed gate insulator.
  • FIG. 4 is a plot of the capacitance- voltage curve of the MIS capacitor shown in FIG. 3.
  • FIG. 5 is a schematic cross section through an MIS field effect transistor that incorporates a printed gate dielectric.
  • FIG. 6 is a diagram showing the steps for fabrication of poly-Si thin film transistors with polystyrene gate insulator.
  • FIG. 7 is a plot of drain current against drain voltage for several gate voltages for the device of FIG. 6.
  • the present invention relates to a circuit manufacturing technique whereby materials consumption will be reduced by employing additive printing, i.e., by printing the circuit materials only where they are needed in the final product.
  • additive printing i.e., by printing the circuit materials only where they are needed in the final product.
  • a simple analogy is provided by a color print, which is made by printing ink only where needed in the final picture.
  • This additive printing is in contrast to conventional integrated-circuit (I.C.) fabrication. There, each circuit material is applied over the entire surface, and then the unwanted portions are removed selectively in a complicated photolithographic process. The origin of this costly I.C. fabrication procedure lies in the need to control the material properties and its pattern separately.
  • the present invention is a method for fabricating high-quality insulators which are additively printed over selected areas, and perform both active and the passive functions.
  • the electrical insulator materials have the following characteristics: (a) high volume resistivity and dielectric breakdown field strength; (b) printable and processable at the low temperatures of macroelectronic manufacture;
  • (c) interfaces to the device semiconductor with electrical performance similar to the ones of MOS capacitors and MOSFETS.
  • toner is printed in the configuration of an interlevel insulator and tested in its dielectric breakdown strength.
  • Metal-polystyrene Insulator- Silicon (MIS) capacitors have capacitance-voltage characteristics which are similar to those of the MOS capacitors used in the I.C. industry. The latter is key evidence for the functionality of the insulator as the gate dielectric in MIS field-effect transistors.
  • MIS Metal-polystyrene Insulator- Silicon
  • FIG. 1 shows a printed insulator in a specific pattern that is designed on a computer.
  • toner bars were selectively printed on the Cr lines placed at a 90° angle to the bottom lines.
  • One layer of yellow xerographic toner was printed in Area 1 and Area 2.
  • the top Cr lines also were thermally evaporated.
  • the area of overlap between the top and bottom Cr lines is 1 mm 2 .
  • the electrical resistance of the printed insulator was tested using a HP semiconductor parameter analyzer.
  • FIG. 2 shows the typical I-V characteristic for one crossover.
  • the maximum applied voltage was 100V at which the current was less than 1 pA.
  • the current corresponds to a resistivity of more than 10 14 ⁇ cm, and demonstrates an insulator of high quality.
  • a high-quality insulator can be printed in a desired pattern. It also shows that the insulator can be printed by applying a solid, fusible precursor form of the insulator, and using an electrophotographic technique.
  • an insulator was applied from a solution. Five weight percent polystyrene was dissolved in 95 wt.% toluene and the solution spun onto a pre-cleaned silicon wafer. The spin rate was varied from 1,500 to 4,500 rpm to adjust the thickness of the final film. Evaporation of the toluene solvent at 135°C left behind a film of polystyrene. An electrode of indium was deposited on top of the polystyrene film. The silicon wafer was p- type with a resistivity of 4 to 6 ⁇ cm, and the polystyrene film was 700 nm thick. The area of the indium electrode was 2.5 mm 2 .
  • FIG. 3 is a sketch of a piece of silicon wafer with a back contract, the polystyrene film and the top electrode.
  • the structure of FIG. 3 is that of an MIS capacitor.
  • the capacitance- voltage characteristic of this capacitor was tested with a measurement frequency of 1 MHz and a ramp rate of 1 V s "1 .
  • the resulting capacitance- voltage curve is shown in FIG. 4.
  • This C-V curve was evaluated for the dopant density of the silicon wafer using the well-known depletion approximation, with a relative dielectric constant of polystyrene, of 3.9.
  • An acceptor dopant density of 1.6x10 15 cm "3 was calculated.
  • the capacitance-voltage characteristic of the MIS capacitor is equivalent to that of a metal/silicon dioxide/silicon capacitor, and demonstrates that the polystyrene film can function as the gate dielectric in a MOSFET.
  • a printable insulator material makes device- quality MIS capacitors. It also shows that the insulator can be applied from solution, which suggests application using an inkjet printer.
  • FIG. 5 A schematic cross section through a field effect transistor is shown in FIG. 5.
  • This schematic is identical to that of a conventional MOSFET, except that the silicon dioxide gate insulator of the MOSFET has been replaced by a printed gate insulator, for example, polystyrene or polyethylene.
  • a printed gate insulator for example, polystyrene or polyethylene.
  • FIG. 5 shows a silicon wafer substrate, i.e., the configuration for comparing the quality of the printed insulator against the quality of conventional I.C. MOSFETSs.
  • the printed insulator's application will primarily be in thin film transistors, where the channel semiconductor material may be amorphous silicon, polycrystalline silicon, or organic semiconductors.
  • These thin film semiconductors are deposited on foreign substrates such as glass, steel, or plastic, either rigid plates or flexible foils.
  • substrates such as glass, steel, or plastic
  • rigid plates or flexible foils either rigid plates or flexible foils.
  • the remainder of the structure may be fabricated in many different ways, including printing. If the substrate is a thin foil, it can be run continuously through printing equipment at any process step. If the substrate is rigid, printing techniques appropriate for the printing of plates would be applied.
  • FIG. 6 is a diagram of the steps involved in fabricating poly-Si thin film transistors in accordance with the invention.
  • the poly-Si layer is deposited onto a glass substrate.
  • the n+ layer is deposited onto the poly-Si layer.
  • source/drain metallization a layer of Cr metal is deposited onto the n+ layer.
  • the Cr metal is patterned.
  • the n+ layer is patterned.
  • polystyrene is deposited onto the patterned source/drain by spinning.
  • the gate is formed by gate metallization by shadow mask.
  • polystyrene is the gate insulator. While this material is spun-on, the plot of FIG. 7 demonstrates that polystyrene insulation is effective.

Abstract

L'invention concerne un procédé d'impression de diélectriques de grille dans des transistors à couches minces. Les diélectriques sont à base de polymères organiques et peuvent être imprimés au moyen de plusieurs techniques, notamment par impression xérographique et par impression à jet d'encre. La température maximale de traitement est approximativement de 160 °C. Cette technique d'impression est appropriée pour des dispositifs électroniques de transistors à couches minces et pour d'autres circuits macro-électroniques fabriqués sur des substrats basse température.
PCT/US1999/006454 1998-03-27 1999-03-26 Isolants imprimes pour dispositifs electroniques actifs et passifs WO1999050889A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU32031/99A AU3203199A (en) 1998-03-27 1999-03-26 Printed insulators for active and passive electronic devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US7974698P 1998-03-27 1998-03-27
US60/079,746 1998-03-27

Publications (2)

Publication Number Publication Date
WO1999050889A2 true WO1999050889A2 (fr) 1999-10-07
WO1999050889A3 WO1999050889A3 (fr) 1999-12-23

Family

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Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/US1999/006453 WO1999050890A1 (fr) 1998-03-27 1999-03-26 Procede de fabrication de dispositifs electroniques multicouches a couches minces
PCT/US1999/006454 WO1999050889A2 (fr) 1998-03-27 1999-03-26 Isolants imprimes pour dispositifs electroniques actifs et passifs

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/US1999/006453 WO1999050890A1 (fr) 1998-03-27 1999-03-26 Procede de fabrication de dispositifs electroniques multicouches a couches minces

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WO (2) WO1999050890A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10151131A1 (de) * 2001-10-17 2003-05-08 Infineon Technologies Ag Verfahren zum Erzeugen einer strukturierten Schicht auf einem Substrat
WO2003098696A1 (fr) * 2002-05-17 2003-11-27 Seiko Epson Corporation Procede de fabrication de circuit
US6686229B2 (en) 2001-03-02 2004-02-03 Koninklijke Philips Electronics N.V. Thin film transistors and method of manufacture
US7906415B2 (en) 2006-07-28 2011-03-15 Xerox Corporation Device having zinc oxide semiconductor and indium/zinc electrode

Families Citing this family (5)

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Publication number Priority date Publication date Assignee Title
US8026565B2 (en) * 2003-01-30 2011-09-27 University Of Cape Town Thin film semiconductor device comprising nanocrystalline silicon powder
EP1684366A1 (fr) * 2005-01-25 2006-07-26 Nederlandse Organisatie voor toegepast-natuurwetenschappelijk Onderzoek TNO Dispositif électronique comprenant un dispositif électronique et un dispositif encapsulant
US7521340B2 (en) 2006-12-07 2009-04-21 Innovalight, Inc. Methods for creating a densified group IV semiconductor nanoparticle thin film
US7851336B2 (en) 2008-03-13 2010-12-14 Innovalight, Inc. Method of forming a passivated densified nanoparticle thin film on a substrate
US8247312B2 (en) 2008-04-24 2012-08-21 Innovalight, Inc. Methods for printing an ink on a textured wafer surface

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US5132248A (en) * 1988-05-31 1992-07-21 The United States Of America As Represented By The United States Department Of Energy Direct write with microelectronic circuit fabrication
US5385848A (en) * 1993-09-20 1995-01-31 Iowa Thin Film Technologies, Inc Method for fabricating an interconnected array of semiconductor devices
US5820932A (en) * 1995-11-30 1998-10-13 Sun Chemical Corporation Process for the production of lithographic printing plates
US5919532A (en) * 1996-03-25 1999-07-06 Sharp Kabushiki Kaisha Active matrix substrate, method for fabricating the same, and liquid crystal display device

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US5049527A (en) * 1985-06-25 1991-09-17 Hewlett-Packard Company Optical isolator
US4796975A (en) * 1987-05-14 1989-01-10 Amphenol Corporation Method of aligning and attaching optical fibers to substrate optical waveguides and substrate optical waveguide having fibers attached thereto
US5309003A (en) * 1992-02-28 1994-05-03 At&T Bell Laboratories Article comprising a real space transfer semiconductor device, and method of making the article
US5249245A (en) * 1992-08-31 1993-09-28 Motorola, Inc. Optoelectroinc mount including flexible substrate and method for making same
EP0680163A3 (fr) * 1994-04-25 1996-07-03 At & T Corp Détecteur/élément photo émissif intégré avec élément directeur sans réproduction par image.
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Publication number Priority date Publication date Assignee Title
US5132248A (en) * 1988-05-31 1992-07-21 The United States Of America As Represented By The United States Department Of Energy Direct write with microelectronic circuit fabrication
US5385848A (en) * 1993-09-20 1995-01-31 Iowa Thin Film Technologies, Inc Method for fabricating an interconnected array of semiconductor devices
US5820932A (en) * 1995-11-30 1998-10-13 Sun Chemical Corporation Process for the production of lithographic printing plates
US5919532A (en) * 1996-03-25 1999-07-06 Sharp Kabushiki Kaisha Active matrix substrate, method for fabricating the same, and liquid crystal display device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6686229B2 (en) 2001-03-02 2004-02-03 Koninklijke Philips Electronics N.V. Thin film transistors and method of manufacture
DE10151131A1 (de) * 2001-10-17 2003-05-08 Infineon Technologies Ag Verfahren zum Erzeugen einer strukturierten Schicht auf einem Substrat
WO2003098696A1 (fr) * 2002-05-17 2003-11-27 Seiko Epson Corporation Procede de fabrication de circuit
US7198885B2 (en) 2002-05-17 2007-04-03 Seiko Epson Corporation Circuit fabrication method
US7906415B2 (en) 2006-07-28 2011-03-15 Xerox Corporation Device having zinc oxide semiconductor and indium/zinc electrode

Also Published As

Publication number Publication date
WO1999050889A3 (fr) 1999-12-23
WO1999050890A1 (fr) 1999-10-07
AU3203199A (en) 1999-10-18
AU3203099A (en) 1999-10-18

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