WO1999050767A1 - Procede de conception de circuit integre a semi-conducteurs - Google Patents

Procede de conception de circuit integre a semi-conducteurs Download PDF

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Publication number
WO1999050767A1
WO1999050767A1 PCT/JP1998/001473 JP9801473W WO9950767A1 WO 1999050767 A1 WO1999050767 A1 WO 1999050767A1 JP 9801473 W JP9801473 W JP 9801473W WO 9950767 A1 WO9950767 A1 WO 9950767A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
parasitic
sensitivity
semiconductor integrated
elements
Prior art date
Application number
PCT/JP1998/001473
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English (en)
Japanese (ja)
Inventor
Hideyuki Osawa
Kunio Seki
Tetsuro Hino
Yukihiro Ota
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to JP2000541611A priority Critical patent/JP3971105B2/ja
Priority to PCT/JP1998/001473 priority patent/WO1999050767A1/fr
Publication of WO1999050767A1 publication Critical patent/WO1999050767A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Definitions

  • the present invention relates to a technique for avoiding malfunctions due to parasitic elements of a semiconductor integrated circuit from the circuit design stage, and is effective when applied to, for example, a method for designing an analog or a mixed analog / digital integrated circuit.
  • Technology. Background art
  • Undesired elements may become apparent in a semiconductor integrated circuit.
  • Such undesired parasitic elements become apparent depending on the circuit configuration, transistor layout, potential state of the operating node, and the like.
  • a pn junction formed between a semiconductor substrate and a device is electrically isolated by setting a reverse bias state to a pn junction.
  • a potential state is established, a current flows in that part, and the circuit is brought into a state equivalent to a parasitic element such as a parasitic bipolar transistor interposed between normal elements.
  • An object of the present invention is to provide a semiconductor integrated circuit design method capable of quantitatively grasping parasitic elements at a circuit design stage.
  • Another object of the present invention is to provide a technique capable of realizing a quantitative grasp of a parasitic element by a simulation processing within a practical time.
  • Another object of the present invention is to provide a method capable of shortening the development period of a semiconductor integrated circuit in terms of verification of a parasitic element.
  • a desired circuit state for example, a pn junction portion is sequentially determined by using a netlist including information on elements constituting a circuit to be designed as a circuit of a semiconductor integrated circuit and connection information of the circuit.
  • a first circuit simulation process for extracting a location on the circuit that can take a potential state as a bias; and a circuit configuration for a location extracted in the first circuit simulation process.
  • a second simulation process for obtaining a sensitivity as a degree at which a model of each parasitic element influences a point of interest in the circuit when a model of the parasitic element is assumed at a plurality of places on the circuit due to the state.
  • a method for designing a semiconductor integrated circuit including:
  • the portion pointed out in the first circuit simulation process corresponds to, for example, an emission (or collection) of a parasitic bipolar transistor.
  • the other terminal of the parasitic bipolar transistor that is, the collector (or emitter) is a semiconductor region of various other elements having a common semiconductor substrate, such as an emitter or collector of a normal bipolar transistor (analysis target node).
  • a model of a parasitic bipolar transistor for example, a current source is assumed to be connected to such an analysis target node, and this current source has an effect on a point of interest (for example, a required output terminal) of the circuit. The degree of influence is obtained as sensitivity.
  • the sensitivity is obtained as a ratio of a current, a voltage, a pulse width, or the like at a point of interest to a current of the current source.
  • the higher the sensitivity the higher the probability of malfunction at the point of interest due to the influence of the parasitic element.
  • parasitic elements can be quantitatively grasped at the stage of circuit design. Therefore, parasitic element countermeasures can be taken intensively for the analysis target node with high sensitivity.
  • Parasitic element countermeasures can be taken as circuit or rate countermeasures. For example, guard rings are provided or transistors are separated according to rules, which can be reliably reflected in the rate design.
  • the second simulation processing it is possible to output a result list in which the information indicating the sensitivity and the position of the corresponding parasitic element model or the element connected to the parasitic element model is sorted in descending order of the sensitivity. it can. Further, in the second simulation processing, the position of the parasitic element model or the element connected to the parasitic element model that responds to the predetermined sensitivity or more can be displayed on the display screen of the circuit so as to be identifiable.
  • the present invention also provides a computer-readable storage medium storing a program for causing a computer to execute the first circuit simulation process and the second simulation process.
  • the present invention provides a circuit design process for supporting circuit design of a semiconductor integrated circuit, a circuit evaluation process for evaluating a circuit designed in the circuit design process, and a rate design for a circuit that has gone through the circuit evaluation process.
  • the present invention provides a semiconductor integrated circuit manufacturing method that includes a late design process that supports the above, and a trial production evaluation process that evaluates a sample produced in accordance with the late design.
  • the circuit evaluation processing includes the first circuit simulation processing and the second simulation processing.
  • the rate design process limits a rate of a bipolar transistor connected to a current source model corresponding to a sensitivity higher than a predetermined value so that a current amplification factor becomes smaller than a predetermined value. / 50767 P
  • FIG. 1 is a flowchart showing the overall design flow to which the negative potential node extraction processing and the parasitic sensitivity analysis processing are applied.
  • Fig. 2 is an explanatory diagram of kickback voltage in motor drive IC.
  • FIG. 3 is a vertical cross-sectional view of the device where a parasitic bipolar transistor is formed.
  • FIG. 4 is a drive signal waveform diagram of the linear drive system and the PWM drive system.
  • FIG. 5 is a circuit diagram of a countermeasure against a negative voltage node by an external voltage clamp circuit.
  • FIG. 6 is a circuit diagram showing a state of an actual negative potential parasitic defect generated in the driver IC, which was studied by the present inventors.
  • FIG. 7 is an explanatory diagram showing the position of the process of extracting the negative potential node and analyzing the parasitic sensitivity in the method of designing a semiconductor integrated circuit.
  • FIG. 8 is a flowchart of the negative potential node extracting process.
  • FIG. 9 is an explanatory diagram showing an example of a result obtained by the negative potential node extracting process.
  • FIG. 10 is an explanatory diagram in the case of extracting a saturated bipolar transistor instead of extracting a negative potential node.
  • FIG. 11 is an explanatory diagram in the case of extracting a bipolar transistor to which a withstand voltage excess voltage is applied instead of extracting a negative potential node.
  • FIG. 12 is a conceptual diagram of the parasitic sensitivity analysis.
  • FIG. 13 is a flowchart of the parasitic sensitivity analysis process.
  • Fig. 14 shows an example of a part of a netlist with a parasitic current source added.
  • FIG. 15 is an explanatory diagram showing an example of the results of the parasitic sensitivity analysis.
  • FIG. 16 is an explanatory diagram of the sensitivity when a current, a voltage, a pulse width, or the like is used as the variation d E when evaluating the parasitic sensitivity.
  • FIG. 17 is a block diagram of a computer that executes a negative potential node extracting program, a parasitic sensitivity analyzing program, and the like.
  • FIG. 18 is an overall flowchart when a semiconductor integrated circuit is manufactured by employing the process of extracting the negative potential node and analyzing the parasitic sensitivity.
  • FIG. 19 is a flowchart of a process focusing on the warning display.
  • the present invention will be described in detail with an example of a countermeasure against a negative potential parasitic defect in the driver IC.
  • the driver which is the load of the driver IC, can be electrically treated as inductance. Therefore, if the terminal voltage is V, the current flowing through the inductance is I, and the
  • V dl / dt
  • the differential value of the current flowing through the inductance appears as a voltage.
  • a beard-like voltage (kickback) proportional to the slope is generated at the output terminal PU when the current rises and falls. . Since this occurs regardless of the power supply voltage of the IC, a voltage higher than the power supply voltage or a so-called negative potential lower than the ground may occur.
  • the npn bipolar transistors Q1 and Q2 are push-pull circuits that constitute the output stage.
  • the npn bipolar transistor Q 4 is a representative example of a transistor included in the previous circuit for controlling the output stage. Things.
  • the semiconductor substrate P-SUB is normally set to the lowest potential (for example, ground voltage V ss) in the IC, and the pn junction formed between the semiconductor substrate and the device is reversed.
  • the device is electrically isolated by setting it to a bias state.
  • this condition is broken at the negative potential due to the kickback of the inductance, and the pn junction between the semiconductor substrate and the element becomes a forward bias state, and current flows.
  • a parasitic npn bipolar transistor Qpr with a node having a negative potential as an emitter, a semiconductor substrate as a base, and a collector as another n-type semiconductor region operates.
  • a node (collector of Q4 or base of Pnp bipolar transistor not shown) that can be a collector of parasitic npn bipolar transistor Qpr is connected to a semiconductor with respect to the position of the negative potential node PU.
  • Substrate P Subscribes to the entire transit area with a common SUB.
  • the energy-efficient PWM (Pulse Width Modulation) drive method is increasing from the linear drive method shown by the drive signal waveforms in Fig. 4 with the reduction in power consumption of IC, the PWM method is Since the inductance is driven in a pulsed manner, kickback is likely to occur, and in order to reduce the cost of the system, a voltage clamp such as an IC external shot diode D0 as shown in Fig. 5 is used. Can't add a circuit There are circumstances.
  • FIG. 6 shows the state of the actual negative potential parasitic defect caused by the mode driver IC examined by the present inventors.
  • Q 1 and Q 2 are output stage transistors. In a normal operation, the transistors Q2 and Q4 are off, and the transistor Q1 performs a switching operation by the PWM signal, so that a current flows through the coil through the transistor Q1 to generate a torque and rotate the motor.
  • the failure in the circuit of FIG. 6 occurs as follows. When the transistor Q1 changes from the on state to the off state, the output terminal PU becomes a negative potential due to the kickback of the inductor. The negative potential propagates to the emitter of transistor Q3.
  • the parasitic npn transistor Qpr between the collector of the transistor Q3 and the base of the transistor Q4 operates to draw the base current of the transistor Q4, and the transistor Q4, which should be in the off state, is turned on.
  • the collector current of the transistor Q4 is supplied to the base of the transistor Q2, and the transistor Q2 is turned on.
  • the negative potential node propagates not only to the output terminal but also to the internal node of IC.
  • the processing for extracting the negative potential node is performed by executing a program (negative potential node extracting program) for extracting all negative potential nodes using a circuit simulator. Also, despite the fact that parasitic transistors are everywhere, only a few actually cause failures.
  • the processing of the parasitic sensitivity analysis is performed by executing a program (parasitic sensitivity analysis program) for determining the sensitivity to the parasitic.
  • Figure 7 shows an example of the positioning of the negative potential node extraction (VCHECK) and parasitic sensitivity analysis (PSS) processing in the semiconductor integrated circuit design method. Is shown. In FIG. 7, the processing on the LSI manufacturer side and the processing on the LSI user side are shown separately.
  • the target LSI here is a mode dryino, an analog / digital mixed semiconductor integrated circuit such as an IC or an audio IC, and an ASIC (Application Specific Integrated Circuit). This is a format in which the LSI user mainly performs circuit design and layout design, such as a circuit design.
  • the LSI maker collectively provides the LSI user as a design kit with a library of circuit cells, design tools, design rules, and the like so that the LSI user can perform circuit design and layout design.
  • the LSI user performs circuit design, layout design, and the like of a desired semiconductor integrated circuit using the design kit.
  • the negative potential node extraction (VCHECCK) and the parasitic sensitivity analysis (PSS) are performed, and the results are fed back to the circuit design and reflected in the layout design.
  • FIG. 8 shows a flowchart of the negative potential node extracting process.
  • the negative potential node extraction program includes a pre-processing unit and a post-processing unit for the circuit simulation.
  • the input of the preprocessing unit is a simulation netlist (Sim netlist) L1 to which a transient analysis can be executed by adding an analysis designation statement and an input signal.
  • the simulation netlist has a SPIC format, and includes the names of the elements that make up the circuit, the names of the nodes to which the elements are connected, and the model names of the elements for each element.
  • the characteristic information of the elements included in the simulation netlist is acquired with reference to the library.
  • the check information is added to the simulation netlist 1 (S1), and the output of the preprocessing unit outputs check statements (waveform measurement function of a designated node included in the circuit simulation) for all nodes. Simulated added It is referred to as the session netlist L2.
  • the check information is a description indicating a negative potential if a negative potential node is extracted, and is given by a description such as VCHECK V ⁇ 0.
  • the check information is, although not particularly limited, expanded into a check text of each node and included in the netlist L2.
  • a circuit simulation is performed on the simulation netlist L2 (S2). Circuit simulation methods are well-known and will not be described in detail. However, simulation simulations (connection information, analysis time, analysis conditions such as output nodes, etc.) are input, and the transient response and frequency response are analyzed by numerical analysis. And the like.
  • the post-processing unit extracts, edits, and outputs information related to the check sentence from the execution result list R1 of the circuit simulation (S3). That is, the node measured as a negative potential node by the check statement is extracted, and the output result list R2 is, as exemplified in FIG. 9, the element name or the node name corresponding to the check item. And its time. As a result, the negative potential node is restored.
  • the essence of the negative potential node extraction program is to perform a transient waveform check on all elements or nodes. Not only the negative potential node extraction function but also saturation as illustrated in FIG. 10 is performed. It is also possible to extract a bipolar transistor or a node in which a voltage exceeding the withstand voltage as shown in FIG. 11 is applied. In order to extract the saturation of the bipolar transistor, the base-collector voltage V bc ⁇ 0 may be set as an appropriate condition. In addition, in the case where the excess voltage is exceeded during the bipolar transistor, the extraction condition should be the excess voltage between the collector and emitter, between the collector and the base, or between the emitter and the base.
  • Fig. 12 shows a conceptual diagram of the parasitic sensitivity analysis.
  • a small current source (Ip) of about 10 A is used as a simplified model of parasitic npn bipolar transistors. Add this current source to one of the nodes where parasitics may occur, and observe the electrical change (dE) of the node whose sensitivity you want to see, for example, the output terminal PU.
  • the node where the parasitic may occur is a node having the Epi layer as an element terminal, specifically, a collector of an npn bipolar transistor, a base of a pnp bipolar transistor, and the like.
  • FIG. 13 shows a flowchart of the parasitic sensitivity analysis process.
  • a simulation netlist L11 is input to which an analysis designation statement and an input signal are added and a transient analysis can be performed.
  • the simulation netlist has a SPICE format, and includes, for each element, a name of an element constituting a circuit, a name of a node connected to the element, a model name of the element, and the like.
  • the characteristic information of the elements included in the simulation netlist is acquired by referring to the library.
  • the simulation netlist L 11 may be the same as the simulation netlist 1.
  • a parasitic current source is added to the simulation netlist L11 (S11) to obtain a simulation netlist L12.
  • FIG. 1 A parasitic current source is added to the simulation netlist L11 (S11) to obtain a simulation netlist L12.
  • FIG. 14 shows an example of a description of a portion of the netlist L12 when a parasitic current source (10 ⁇ A) is added to the base of the transistor Q4, for example.
  • the same symbol in the description of the terminal name means that they are connected to each other.
  • the device name of the parasitic current source is shown as Ip. In fact, a description is added that connects a parasitic current source to all of the collector of the npn bipolar transistor and the base of the pnp bipolar transistor included in the netlist L11.
  • Circuit simulation is performed on the simulation netlist L12 (S12), the parasitic sensitivity of the analysis target node is obtained (R11), and the nodes are sorted in descending order of sensitivity (S11). 13 ) . This process is sequentially repeated for all nodes at which parasitics may occur, that is, for the collector of the npn bipolar transistor and the base of the pnp bipolar transistor included in the netlist L11.
  • a sensitivity analysis result list (R1 2) sorted in descending order of sensitivity is output.
  • Fig. 15 shows an example of the results of parasitic sensitivity analysis.
  • the current value of the parasitic current source is set to 10 e-6 (10 A), and the analysis target nodes are sorted in descending order of the absolute value of the sensitivity (Sensitivity).
  • the model of the parasitic element is a current source, but the current, voltage, pulse width, and the like may be used as the variation dE in evaluating the parasitic sensitivity as illustrated in FIG.
  • FIG. 1 shows an overall design flow to which the negative potential node extraction processing and the parasitic sensitivity analysis processing are applied.
  • Negative potential node extraction processing (S210) and parasitic sensitivity in circuit design verification (S21) after circuit design (S210) Perform analysis processing (S211).
  • Parasitic sensitivity analysis results are fed back to circuit design results, if possible, as circuit measures. For example, for elements or nodes with high parasitic sensitivity, take measures on the circuit such as lowering the impedance by lowering the impedance, or clipping the negative potential by adding a clamp circuit.
  • the negative potential node and the element with high parasitic sensitivity are laid out separately, or a dummy n-type semiconductor region or gap is placed between them.
  • Layout measures such as placing a drilling and drawing current from it.
  • Such countermeasures can be implemented using electronic design guides.
  • a high-sensitivity element or node will display an alarm display that can be distinguished from the others on the circuit design system screen.
  • an alarm that can also be distinguished from others on the screen of the rate design system Display.
  • FIG. 17 shows an example of a computer that executes the negative potential node extracting program and the parasitic sensitivity analyzing program.
  • the computer shown in FIG. 1 has a computer main unit 1 in which a processor (not shown), a RAM serving as a work area of the processor, various input / output controllers, a display controller, and the like are connected to a bus. Be composed.
  • the application program executed by the processor is stored in an auxiliary storage device (for example, a hard disk drive) 2 connected to the input / output controller.
  • the auxiliary storage device 2 stores various design support tools such as the negative potential node extracting program and the parasitic sensitivity analysis program, and the programs are loaded from the auxiliary storage device into the RAM and processed. Executed by Sessa.
  • the design support tools have a graphic user interface and can be operated while viewing the screen displayed on the display 3.
  • the alarm display of the parasitic sensitivity dog can also indicate its position with respect to the circuit diagram displayed on the circuit design operation screen.
  • FIG. 18 shows an overall flowchart when a semiconductor integrated circuit is manufactured by employing the negative potential node extraction and parasitic sensitivity analysis processing.
  • Circuit design and circuit verification processing (S30) are performed on the use of circuits such as the electrical characteristics of semiconductor integrated circuits, packages, and pins.
  • circuit design a circuit diagram is input by a circuit diagram editor, and the circuit is verified.
  • Circuit verification includes checking the circuit configuration (topology check) and circuit simulation.
  • transient analysis, extraction of the negative potential node, and parasitic sensitivity analysis are performed. Parasitic sensitivity analysis results are fed back to the circuit design.
  • Circuit design data (circuit topology), parasitic sensitivity analysis results, and layout constraints are used for layout design and layout verification processing (S31).
  • layout design circuit layout is performed by automatic placement and routing. At this time, a layout considering the result of the parasitic sensitivity analysis is performed. Verification such as pattern check and electrical check is performed on the layout result, and inconvenient points are fed to the layout design processing.
  • Mask data is obtained by the layout design.
  • a semiconductor integrated circuit is prototyped according to the mask pattern (S32), and the prototype device is evaluated using a test device (S33).
  • S33 a test device
  • S34 mass production of the semiconductor integrated circuit
  • the circuit simulation including the parasitic element cannot be performed.
  • the analysis target elements (elements with high parasitic sensitivity) that have a significant effect on the point of interest are listed, and the sensitivity is reduced by modifying the circuit in advance for such elements.
  • it is possible to easily take countermeasures such as lowering the hFE of the parasitic element by increasing the distance from the part that is set to a negative potential or the like during the layout (the part that is set to the forward bias state). Become.
  • the high-sensitivity element restore can be realized in practical computer processing time. Cut-and-try periods for prototype devices can also be reduced. Therefore, the development period of the semiconductor integrated circuit can be reduced in terms of verification of parasitic elements.
  • FIG. 19 shows a processing flow when paying attention to the warning display.
  • the circuit data is subjected to circuit verification such as the extraction of the negative potential node and the analysis of parasitic sensitivity (S40), and display data for warning display of a portion having high parasitic sensitivity is generated using the result. (S41).
  • a warning is displayed on the screen using the display data and the circuit data (S42).
  • the circuit modification for the high sensitivity part is reflected in the circuit design and also in the layout design. By using the verification results for the layout designed mask data, it is also possible to display a warning for a site with high parasitic sensitivity.
  • the parasitic element may be a bipolar transistor that is parasitic between two bipolar transistors, a transistor that is parasitic between a MOS transistor, and a capacitor that is parasitic on a transistor.
  • the parasitic defect is not limited to the example of FIG.
  • the present invention is not limited to the case where an LSI user performs circuit design and layout design as illustrated in FIG. 7, and it goes without saying that the present invention can be applied to design by an LSI maker.
  • the present invention can be applied not only to design verification of power system LSIs such as a driver IC and an audio power amplifier IC, but also to a wide variety of semiconductor integrated circuit designs and manufacturing methods.

Abstract

L'invention concerne un procédé de conception de circuit intégré à semi-conducteurs, qui comporte un premier procédé (S210) de simulation de circuit dans lequel on relève des points sur un circuit spécifié de circuit intégré à semi-conducteurs pouvant présenter un état de circuit voulu, par exemple un état de potentiel tel qu'une section de jonction pn soit alimentée dans le sens passant, au moyen d'une liste d'interconnexions qui comporte les données concernant les éléments constituant le circuit spécifié du circuit intégré à semi-conducteurs, cette liste étant utilisée comme objectif de conception, et de données concernant l'état de connexion du circuit; et un deuxième procédé (S211) de simulation dans lequel des modèles d'éléments parasites sont prévus à plusieurs points du circuit, la sensibilité étant obtenue comme degré d'influence de chaque modèle d'élément parasite sur les points considérés du circuit, résultant des états de circuit des points relevés au cours du premier procédé de simulation. Pendant l'étape de conception, les points et les caractéristiques de fonctionnement des éléments parasites sont inconnus, et pour cette raison, il n'est pas possible de mettre en oeuvre une simulation de circuit comprenant les éléments parasites. Cependant, en établissant une liste des éléments parasites (éléments ayant une grande sensibilité aux parasites) qui pourraient présenter une influence importante sur les points considérés du circuit et, de ce fait, devraient être analysés, et en apportant ensuite des corrections au circuit concernant ces éléments en vue de réduire à l'avance la sensibilité ou en éloignant ceux-ci des points qui sont à potentiel négatif dans le tracé (points alimentés dans le sens passant) pour réduire les hFE des éléments parasites, on peut facilement mettre en oeuvre une action correctrice d'avance sur ces éléments parasites. Les éléments présentant une forte sensibilité aux parasites peuvent être relevés par ordinateur au cours d'un temps de traitement pratique.
PCT/JP1998/001473 1998-03-31 1998-03-31 Procede de conception de circuit integre a semi-conducteurs WO1999050767A1 (fr)

Priority Applications (2)

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JP2000541611A JP3971105B2 (ja) 1998-03-31 1998-03-31 半導体集積回路の設計方法
PCT/JP1998/001473 WO1999050767A1 (fr) 1998-03-31 1998-03-31 Procede de conception de circuit integre a semi-conducteurs

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Application Number Priority Date Filing Date Title
PCT/JP1998/001473 WO1999050767A1 (fr) 1998-03-31 1998-03-31 Procede de conception de circuit integre a semi-conducteurs

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Cited By (2)

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US7383527B2 (en) 2004-09-27 2008-06-03 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit manufacturing method and semiconductor integrated circuit manufacturing apparatus
US7400937B2 (en) 1999-12-01 2008-07-15 Silverbrook Research Pty Ltd MP3 player with code sensor

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JP6860518B2 (ja) 2018-03-20 2021-04-14 株式会社東芝 回路設計支援装置および回路設計支援方法

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TSUJIMOTO H., ET AL.: "A STEPPING MOTOR DRIVER WITH NO EXTERNAL DIODES.", IEICE TECHNICAL REPORT, DENSHI JOUHOU TSUUSHIN GAKKAI, JP, vol. 93., no. 188., 1 August 1993 (1993-08-01), JP, pages 09 - 15., XP000866038, ISSN: 0913-5685 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7400937B2 (en) 1999-12-01 2008-07-15 Silverbrook Research Pty Ltd MP3 player with code sensor
US7383527B2 (en) 2004-09-27 2008-06-03 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit manufacturing method and semiconductor integrated circuit manufacturing apparatus

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