WO1999049511A1 - Composant a semi-conducteur, sa fabrication, plaquette de circuit et composant electronique - Google Patents

Composant a semi-conducteur, sa fabrication, plaquette de circuit et composant electronique Download PDF

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Publication number
WO1999049511A1
WO1999049511A1 PCT/JP1999/001409 JP9901409W WO9949511A1 WO 1999049511 A1 WO1999049511 A1 WO 1999049511A1 JP 9901409 W JP9901409 W JP 9901409W WO 9949511 A1 WO9949511 A1 WO 9949511A1
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WO
WIPO (PCT)
Prior art keywords
intermediate layer
semiconductor device
conductive foil
forming
hole
Prior art date
Application number
PCT/JP1999/001409
Other languages
English (en)
Japanese (ja)
Inventor
Nobuaki Hashimoto
Original Assignee
Seiko Epson Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corporation filed Critical Seiko Epson Corporation
Priority to KR1019997010795A priority Critical patent/KR100619568B1/ko
Priority to AU28541/99A priority patent/AU2854199A/en
Publication of WO1999049511A1 publication Critical patent/WO1999049511A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the same, a circuit board, and an electronic device.
  • CSP Chip Scale / Size Package
  • a gap is formed between the substrate having the external electrodes and the semiconductor chip, and the resin is injected into this gap.
  • This resin has elasticity when cured.
  • the elastic resin absorbs the stress (thermal stress) applied to the external electrodes. Note that this stress is caused by a difference in thermal expansion coefficient between the semiconductor device and a circuit board on which the semiconductor device is mounted.
  • An object of the present invention is to solve this problem, and an object of the present invention is to provide a semiconductor device capable of effectively absorbing heat stress, a method of manufacturing the same, a circuit board, and an electronic device. Disclosure of the invention
  • a semiconductor device includes: a semiconductor element having an electrode;
  • a passivation film Provided on the surface of the semiconductor element, avoiding at least a part of each electrode.
  • a conductive foil provided at a predetermined interval in a thickness direction above a surface on which the passivation film is formed;
  • a recess is formed in the intermediate layer below the region including the junction with the external electrode in the conductive foil, and the opening region becomes wider from the passivation film side toward the conductive foil side. ing.
  • the “semiconductor element” according to the present invention is not limited to a semiconductor chip, and may refer to a wafer-shaped element that is not an individual piece.
  • the semiconductor element referred to here only needs to be formed as a predetermined circuit that can be used even if it is separated into a base substrate made of silicon, for example. Whether it is separated into individual pieces or integrated with each other There is no particular limitation.
  • the external electrode is formed on the conductive foil, and the conductive foil is supported by the intermediate layer.
  • a recess is formed in the intermediate layer, and an external electrode is located above the recess. That is, the external electrodes are not directly supported by the intermediate layer, but float from the intermediate layer. This allows the external electrodes to move relatively freely, thus absorbing the stress (thermal stress) caused by the difference in the coefficient of thermal expansion from the circuit board.
  • the concave portion may be filled with a resin having a Young's modulus lower than that of the intermediate layer.
  • the space of the concave portion can be filled, so that cracks due to expansion of water vapor can be prevented during heating in a reflow step or the like.
  • the wiring is formed on the surface on which the passivation film is formed, and is located on the bottom surface of the concave portion of the intermediate layer;
  • the resin to which a conductive filler is added, wherein the wiring and the conductive foil And may be electrically connected.
  • the intermediate layer has an inclined surface between the electrode and the conductive foil
  • the wiring may electrically connect the electrode and the conductive foil through the inclined surface.
  • the intermediate layer may be formed of a material having flexibility.
  • the conductive foil may have a hole at a position inside the opening area of the concave portion and at a position avoiding a connection portion with the external electrode.
  • the conductive foil is easily deformed, and the conductive foil can absorb the stress.
  • the substrate on which the conductive foil is formed is provided with a surface on which the conductive foil is formed facing the intermediate layer,
  • the substrate has a through hole above the recess
  • the external electrode may be formed on the conductive foil through the through hole.
  • the conductive foil is covered and protected by the substrate.
  • a substrate formed of a flexible material is provided between the intermediate layer and the conductive foil,
  • the substrate has a through hole in an area except above the concave portion
  • the wiring and the conductive foil may be electrically connected via the through hole.
  • the conductive foil and the wiring may be formed integrally.
  • the conductive foil and the wiring may be separate bodies.
  • a method of manufacturing a semiconductor device comprising the steps of: preparing a semiconductor element having electrodes and having a passivation film provided on a surface thereof, avoiding at least a part of each of the electrodes;
  • a conductive foil is provided above the surface on which the passivation film is formed at predetermined intervals in the thickness direction, and an intermediate layer supporting the conductive foil between the passivation film and the conductive foil Forming a concave portion in the intermediate layer at a position avoiding the electrode; Forming a wiring for electrically connecting the electrode and the conductive foil,
  • the external electrode is formed on the conductive foil, and the conductive foil is supported by the intermediate layer.
  • a recess is formed in the intermediate layer, and an external electrode is located above the recess. That is, the external electrodes are not directly supported by the intermediate layer, but float from the intermediate layer. This allows the external electrodes to move relatively freely, thus absorbing the stress (thermal stress) caused by the difference in the coefficient of thermal expansion from the circuit board.
  • the through-hole is positioned above the recess, and the conductive foil is opposed to the recess, and the substrate is placed on the intermediate layer.
  • the external electrode may be formed on the conductive foil through the through hole.
  • the step of forming the conductive foil can be easily performed.
  • the step of forming the conductive foil can be easily performed.
  • the concave portion may be formed by forming the conductive foil in an intermediate layer, forming a hole in the conductive foil, and etching the intermediate layer through the hole.
  • the intermediate layer may be formed of a material that can be etched under the condition that the semiconductor element cannot be etched.
  • a hole may be formed in the conductive foil, and the recess may be formed by etching the intermediate layer through the hole.
  • the coating layer on the passivation film the etching of the passivation film can be prevented.
  • a first coating layer made of a material that is difficult to be etched under the etching conditions of the intermediate layer
  • the intermediate layer may be etched down to a position below the conductive foil through a hole in the conductive foil.
  • the external electrode is formed on the conductive foil, and the external electrode is difficult to be etched under the etching conditions of the intermediate layer.
  • the intermediate layer is etched to form the concave portions. Therefore, the etching can be performed after removing the residue generated by the formation of the external electrode, and the residue does not remain in the concave portion.
  • the present invention may include a step of filling the concave portion with a resin having a Young's modulus lower than that of the intermediate layer.
  • the semiconductor device is mounted on a circuit board according to the present invention.
  • An electronic device includes the circuit board described above. BRIEF DESCRIPTION OF THE FIGURES
  • FIG. 1 is a cross-sectional view illustrating a semiconductor device according to the first embodiment.
  • FIG. 2 is a plan view illustrating the semiconductor device according to the first embodiment.
  • FIGS. FIG. 4 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment
  • FIG. 4 is a diagram illustrating a semiconductor device according to a second embodiment
  • FIG. 5 is a diagram illustrating a semiconductor device according to a third embodiment.
  • FIG. 6 is a diagram illustrating a semiconductor device according to the fourth embodiment.
  • FIGS. 7A to 7D are diagrams illustrating a method of manufacturing the semiconductor device according to the fourth embodiment.
  • 8A to 8C are diagrams illustrating a method for manufacturing a semiconductor device according to the fourth embodiment.
  • FIGS. 7A to 7D are diagrams illustrating a method of manufacturing the semiconductor device according to the fourth embodiment.
  • FIGS. 9A to 9C are diagrams illustrating a method for manufacturing a semiconductor device according to the fifth embodiment.
  • 10A to 10C are diagrams showing a method for manufacturing a semiconductor device according to the sixth embodiment, and FIGS. 11A and 11B are related to the seventh embodiment.
  • FIG. 12 is a diagram illustrating a semiconductor device according to an eighth embodiment
  • FIGS. 13A to 13D are diagrams illustrating a method of manufacturing a semiconductor device according to a ninth embodiment.
  • FIGS. 14A and 14B are diagrams showing a method of manufacturing the semiconductor device according to the ninth embodiment.
  • FIG. 15 is a diagram showing a modification of the ninth embodiment. Is a diagram illustrating a circuit board on which the semiconductor device according to the present embodiment is mounted, and FIG.
  • FIG. 17 is a diagram illustrating an electronic apparatus including the circuit board on which the semiconductor device according to the present embodiment is mounted.
  • BEST MODE FOR CARRYING OUT THE INVENTION will be described with reference to the drawings. Each drawing is partially enlarged for easy understanding. In the following description, the description is made on the assumption that one semiconductor device is finally formed into individual pieces. Therefore, some terms and shapes used may be slightly different from actual ones. In the following description, it is described as a semiconductor chip, and as it means,
  • semiconductor element is not limited to a semiconductor chip
  • semiconductor element may refer to a wafer-shaped element which is not in individual pieces.
  • the semiconductor element referred to here only needs to form a predetermined circuit that can be used even if it is separated into a base substrate made of silicon, for example. Whether it is separated into individual pieces or integrated with each other There is no particular limitation.
  • semiconductor element since only representative portions necessary for description of wiring and the like are shown, similar portions and other structures are omitted in other drawings in each drawing.
  • FIG. 1 is a sectional view showing the semiconductor device according to the first embodiment.
  • the semiconductor device 10 shown in FIG. 1 is of the CSP type whose package size is almost the same as that of the semiconductor chip 12.
  • An electrode 14 is formed on the active surface 12a of the semiconductor chip 12 from, for example, aluminum (A1).
  • a passivation film 11 is formed on the semiconductor chip 12 so as to avoid at least a part of each electrode 14. Here, at least a part is avoided because it is necessary to derive an electric signal or the like from the electrode 14. Therefore, the passivation film 11 needs to avoid the electrode 14 to the extent that an electrical signal or the like can be derived from the electrode 14.
  • Passivation one Chillon film 1 if example embodiment, may be formed such as by S I_ ⁇ 2, S i N, polyimide resin.
  • An intermediate layer 16 is formed on the active surface 12a avoiding the electrode 14. More specifically, an intermediate layer 16 is formed on the passivation film 11.
  • a concave portion 16a is formed in the intermediate layer 16, and the active surface 12a is exposed in the concave portion 16a.
  • the intermediate layer 16 has an inclined surface 16 b inclined from the electrode 14.
  • the wiring 18 is formed from the electrode 14 to the intermediate layer 16 via the inclined surface 16b.
  • the opening end of the concave portion 16a shown in FIG. 1 is considerably larger than the size of the root portion of the external electrode 26, but is not limited thereto, and is substantially equal to the size of the root portion of the external electrode 26. Or more than that. Further, an opening of the concave portion 16a may be located at a part of the root of the external electrode 26.
  • the opening allows the deformation of the intermediate layer and exerts a stress relaxation effect.
  • the recess 16a may penetrate the intermediate layer 16 to expose the passivation film 11 thereunder, but the intermediate portion is provided at the bottom of the recess 16a so as not to penetrate the intermediate layer 16. A part of the layer 16 may be left.
  • the intermediate layer 16 is made of an insulating resin, for example, a polyimide resin, and when the semiconductor device 10 is mounted on a circuit board (not shown), the semiconductor chip 12 and the circuit board to be mounted are connected to each other. Can be alleviated due to a difference in thermal expansion coefficient between the two. It is not an essential requirement of the present invention that the intermediate layer 16 has a stress relaxation function. The stress relieving function is also achieved by forming the recess 16a (details will be described later).
  • the insulating resin has an insulating property with respect to the wiring 18, can protect the active surface 12 a of the semiconductor chip 12, and has heat resistance when melting the solder at the time of mounting.
  • polyimide resins and the like are generally used, and among them, those having a low Young's modulus (for example, a polyimide resin of an olefin type, and Dow Chemical Co., Ltd. except for polyimide resins) It is preferable to use a BCB manufactured by Nissan Co., Ltd., and it is particularly preferable that the Young's modulus is about 300 kg / mm 2 or less.
  • the thickness is preferably about 1 to 100 m in consideration of the size of the semiconductor device and the manufacturing cost.
  • a thickness of about 100 ⁇ m is sufficient.
  • the intermediate layer 16 for example, a silicone-modified polyimide resin, an epoxy resin, a silicone-modified epoxy resin, or the like may be used, and a material having a low Young's modulus and capable of acting as a stress relieving material may be used.
  • a material having a low Young's modulus and capable of acting as a stress relieving material may be used.
  • the intermediate layer 1 6 to form a raised to the power base one Chillon layer (S i N, such as S i 0 2, M g O ), the stress relaxation itself, This may be performed by forming the concave portion 16a as described later.
  • the wiring 18 is formed from, for example, copper (Cu), chromium (Cr), titanium (Ti), nickel (Ni), titanium tungsten (Ti-W), or a laminate of a plurality of these.
  • the conductive foil 22 is formed thereon.
  • the conductive foil 22 is formed on the substrate 20 in advance, and is adhered to the wiring 18 together with the substrate 20 via an adhesive 24.
  • the conductive foil 22 is also formed of, for example, copper (Cu).
  • the conductive foil 22 is formed to be larger than the opening end of the concave portion 16a formed in the intermediate layer 16, and is arranged so as to cover above the concave portion 16a. In addition, a part of the conductive foil 22 is in contact with and electrically connected to the wiring 18.
  • the conductive foil 22 and the wiring 18 are welded by applying heat and pressure.
  • the electrical connection between the conductive foil 22 and the wiring 18 may be made by mechanical pressure welding with the adhesive 24 as described above, or Au, Sn on the wiring 18 and the conductive foil 22.
  • the two may be brazed by soldering or the like, or may be connected by diffusion bonding using ultrasonic heat or the like.
  • a low-temperature solder is provided on at least one of the joining surfaces of both the conductive foil 22 and the wiring 18.
  • the substrate 20 is a film formed of a flexible resin or the like, and has a through hole 20a at a position above the concave portion 16a.
  • the conductive foil 22 is formed on the lower surface of the substrate 20 so as to cover the through hole 20a.
  • the external electrode 26 is formed on the conductive foil 22 via the through hole 20a.
  • the external electrode 26 may be formed by, for example, only solder, or may be formed by applying a solder or gold plating to the surface of copper (Cu) or nickel (Ni).
  • the substrate 20 with the conductive foil 22 a two-layer ((foil + polyimide substrate) or three-layer ( ⁇ 11 foil + adhesive + polyimide substrate) film carrier tape or FPC used in TAB technology (Flexible Printed Circuit)
  • the present embodiment is configured as described above, and its operation will be described below:
  • the external electrode 26 is formed.
  • the conductive foil 22 is supported by the intermediate layer 16.
  • the intermediate layer 16 has a concave portion 16a in a region including immediately below the external electrode 26. 6A, conductive foil 2 2 empty under 2 A gap is formed. That is, in the vicinity of the joint with the external electrode 26, the conductive foil 22 is in a floating state and is easily deformed.
  • FIG. 2 shows a plan view of the semiconductor device according to the present embodiment.
  • a wiring 18 is formed from the electrode 14 of the semiconductor chip 12 toward the center of the active surface 12a, and each wiring 18 is connected to the conductive foil 22.
  • External electrodes 26 are provided. The area excluding the external electrodes 26 is covered and protected by the substrate 20 ⁇
  • the electrode 14 is an example of a so-called peripheral electrode type located at the peripheral portion of the semiconductor chip 12, but an area array type semiconductor chip in which an electrode is formed in a region inside the peripheral region of the semiconductor chip is used. May be.
  • the external electrode 26 is provided not on the electrode 14 of the semiconductor chip 12 but in the active area of the semiconductor chip 12 (the area where the active elements are formed).
  • the external electrode 26 can be provided in the active area by providing the intermediate layer 16 in the active area and further arranging (pulling) the wiring 18 in the active area. That is, pitch conversion can be performed. Therefore, when arranging the external electrode 26, an active area, that is, an area as a fixed surface can be provided, and the degree of freedom of the setting position of the external electrode 26 is greatly increased.
  • the external electrodes 26 are provided so as to be arranged in a grid by bending the wiring 18 at a required position. Since this is not an essential configuration of the present invention, the external electrodes 26 do not necessarily have to be provided so as to be arranged in a lattice.
  • FIGS. 3A to 3E are diagrams illustrating the method for manufacturing the semiconductor device according to the present embodiment.
  • a semiconductor chip 12 having an electrode 14 made of, for example, aluminum (A 1) is prepared.
  • a passivation film (not shown) is formed on the semiconductor chip 12 so as to avoid the electrode 14.
  • a commercially available wafer may be prepared.
  • a polyimide resin (not shown) is provided on the active surface 12a of the semiconductor chip 12 by a method such as spin coating.
  • a polyimide resin or the like previously formed into a film may be attached to the active surface 12a.
  • an intermediate layer 16 having a concave portion 16a is formed as shown in FIG. 3B.
  • the recess 16a is formed by photolithography, it is preferable to select a material suitable for the photolithography as the material of the intermediate layer 16.
  • a wiring 18 extending from the electrode 14 to the intermediate layer 16 is formed.
  • T i-W titanium tungsten
  • C u copper
  • the substrate 20 is attached via an adhesive 24.
  • a through hole 20a is formed in advance on the substrate 20, and a conductive foil 22 is provided at a position covering the through hole 20a.
  • tin (Sn), gold (Au), solder, or the like may be applied to at least one of the joining surfaces of both the conductive foil 22 and the wiring 18 to provide a low-temperature solder. preferable.
  • the substrate 20 is placed so that the conductive foil 22 contacts the wiring 18, and heat and pressure are applied from above the substrate 20.
  • the low-temperature solder melts, and the conductive foil 22 and the wiring 18 are electrically connected.
  • This connection can be made by applying ultrasonic waves, etc.
  • an external electrode 26 is formed on the conductive foil 22 through the through hole 20a of the substrate 20.
  • a solder ball is placed, a solder plating is stacked, a solder paste is printed, and a copper (Cu) or nickel (Ni) or both plating is applied.
  • the external electrode 26 is formed by applying solder or gold (Au).
  • the semiconductor device 10 can be obtained.
  • the semiconductor chip 12 is in the shape of a wafer
  • the semiconductor device 10 can be obtained by dicing and cutting into individual pieces. After that, the semiconductor device 10 is subjected to quality inspection and packed in trays.
  • the wiring 18 is formed on the inclined surface 16b, but may be formed on the inclined surface on the concave portion 16a side. This is the same in the following embodiments. In this way, most of the wiring 18 passes through the intermediate layer 16 and is protected, so that device reliability is improved.
  • FIG. 4 is a diagram illustrating a semiconductor device according to the second embodiment.
  • the semiconductor device 30 shown in FIG. 10 is characterized in that the resin 16 is filled in the recess 16 a of the semiconductor device 10 shown in FIG. 1, and other configurations are the same as those of the semiconductor device 10. It is.
  • the open end of the recess 16 a shown in FIG. 4 is considerably larger than the size of the root of the external electrode 26. However, the size is not limited to this, and may be approximately equal to or larger than the size of the root of the external electrode 26.
  • an opening of the concave portion 16a may be located at a part of the root of the external electrode 26. In this case, the opening allows deformation of the intermediate layer, and can exert a stress relaxation effect.
  • the recess 16a may penetrate the intermediate layer 16 to expose a passivation film (not shown) thereunder. However, the recess 16a may be formed so as not to penetrate the intermediate layer 16. A part of the intermediate layer 16 may be left at the bottom.
  • the resin 32 it is preferable to use, for example, a polyimide resin, silicone gel, rubber, or the like used as a photosensitive resist, which has a lower Young's modulus than the intermediate layer 16 and is soft. By doing so, the space formed by the concave portion 16a can be filled, so that cracks due to expansion of air or water vapor during heating in a reflow step or the like can be prevented.
  • a polyimide resin, silicone gel, rubber, or the like used as a photosensitive resist, which has a lower Young's modulus than the intermediate layer 16 and is soft.
  • the resin 32 may be filled before the substrate 20 is attached, or a hole may be formed in the substrate 20 and the substrate 20 may be attached and then filled via the hole.
  • FIG. 5 is a diagram illustrating a semiconductor device according to the third embodiment.
  • the semiconductor device 40 shown in the figure has a semiconductor chip 12, an electrode 14, an intermediate layer 16 and a wiring 18, similarly to the semiconductor device 10 shown in FIG. 1, and the intermediate layer 16 has A recess 16a is formed.
  • the substrate 42 is attached on the intermediate layer 16 via an adhesive 24.
  • the substrate 42 is, for example, a film formed of a material having a low Young's modulus, such as polyimide resin, which is mentioned as the material of the intermediate layer 16 in the first embodiment.
  • a conductive foil 44 formed into a wiring pattern is formed on the substrate 42, and an external electrode 46 is formed on the conductive foil 44.
  • a through hole 42 a is formed on a portion of the wiring 18 located above the intermediate layer 16.
  • An electrical joint 48 is formed in the through hole 42 a, and the conductive foil 44 and the wiring 18 are electrically connected.
  • a solder resist layer 49 is provided on the conductive foil 44 so as to avoid the external electrode 46, and protects the conductive foil 44.
  • the substrate 42 is pasted on the intermediate layer 16 via an adhesive 24 to form a through hole 42 a in the substrate 42.
  • the through holes 42a may be formed in the substrate 42 in advance, and then may be attached.
  • a conductive foil 44 is formed on the substrate 42.
  • the conductive foil 44 can be formed by, for example, sputtering, electrolytic plating, electroless plating, or the like. Photolithography technology may be used for patterning the conductive foil 44. Alternatively, a patterned conductive foil 44 may be provided on the substrate 42 in advance, and this may be attached to the intermediate layer 16.
  • an electric connection portion 48 is provided in a region including the through hole 42 a of the substrate 42.
  • a solder resist layer 49 is provided on the conductive foil 44 so as to avoid a region where the external electrode 46 is formed, and then the external electrode 46 is formed.
  • the method for forming the external electrodes 46 is the same as the method for forming the external electrodes 26 in the first embodiment.
  • the recess 16a is formed in the intermediate layer 16, the stress applied to the external electrode 26 can be absorbed.
  • FIG. 6 is a diagram illustrating a semiconductor device according to the fourth embodiment.
  • an intermediate layer 56 is formed on a semiconductor chip 52 having electrodes 54, and a concave portion 56 is formed in the intermediate layer 56, similarly to the semiconductor device 10 shown in FIG. a is formed.
  • a wiring 58 is formed from the electrode 54 to the intermediate layer 56, and a conductive foil 60 is formed on the intermediate layer 56 integrally with the wiring 58.
  • At least one hole 60a is formed in conductive foil 60.
  • the external electrode 62 is formed in a region on the concave portion 56 a in the conductive foil 60.
  • a solder resist layer 64 is formed on the wiring 58 and the conductive foil 60 so as to avoid the external electrodes 62, and these are protected.
  • This embodiment is characterized by its manufacturing method.
  • 7A to 8C are diagrams illustrating the method for manufacturing the semiconductor device according to the embodiment.
  • the tape-shaped substrate can be attached to the individual semiconductor chip.
  • an intermediate layer 56 is formed on the active surface 52 a of the semiconductor chip 52 while avoiding the electrode 54.
  • the intermediate layer 56 is formed of the same material as the intermediate layer 16 shown in FIG.
  • the intermediate layer 56 also performs a stress relaxation function.
  • the intermediate layer 56 may be formed of a hard material (for example, an inorganic substance such as magnesium oxide (MgO)) that does not perform the stress relaxation function.
  • the intermediate layer 56 may be different in material from the semiconductor passivation film so that the active surface 52 a of the semiconductor chip 52 is not etched when the intermediate layer 56 is etched in a later step. Is preferred.
  • the intermediate layer 56 is preferably formed of a material that can be etched under the condition that the material exposed on the surface of the semiconductor chip 52 is not etched.
  • a metal film 66 is formed from the electrode 54 to the intermediate layer 56.
  • the manufacturing method is the same as the method of forming the metal film for forming the wiring 18 of the first embodiment. Step this case, it takes directly to the external terminal 6 2 of the stress wiring 5 8 to be described later, c metal film 6 6 thickness is preferably about 5 to 2 0 ⁇ M wiring 5 8, to be described later.
  • the wiring 58 and the conductive foil 60 are formed by etching.
  • a hole 60a is formed in a portion of the metal film 66 that will become the conductive foil 60, and the intermediate layer 56 is etched with an etching solution or Exposure to etching gas.
  • an etching solution or Exposure to etching gas for example, when the intermediate layer 5 6 formed of resin such as polyimide, as is Etsuchanto, and strong alkaline aqueous solution such as K 0 H, ⁇ 2 Alternatively, a dry etching gas such as CF 4 is preferable.
  • the intermediate layer 56 is formed of magnesium oxide (MgO) or the like, a hot phosphoric acid aqueous solution or the like is preferable. Then remove etchants as needed. In particular, in the case of a wet process, it is preferable to add a washing step and a rinsing step.
  • the intermediate layer 56 is etched to form the concave portion 56a.
  • the metal film 66 is patterned to form the wiring 58 and the conductive foil 60.
  • a solder resist layer 64 is formed as shown in FIG. 8B, and an external electrode 62 is formed as shown in FIG. 8C.
  • the solder resist a photosensitive polyimide resin or an epoxy resin dry film is often used.
  • the method of forming the external electrodes 62 is the same as in the first embodiment.
  • the semiconductor device 50 is obtained. Also in the present embodiment, the same effects as in the first embodiment can be achieved.
  • the hole 60a is formed in the conductive foil 60, the conductive foil 60 is easily deformed. Therefore, the effect of absorbing the stress by the conductive foil 60 floating on the concave portion 56a is further enhanced.
  • FIGS. 7B to 8A are views showing a method for manufacturing a semiconductor device according to the fifth embodiment.
  • an intermediate layer 76 is formed on a semiconductor chip 72 having electrodes 74.
  • a conductive foil 80 is formed on the intermediate layer 76, and a wiring 78 is formed from the conductive foil 80 to the electrode 74.
  • a solder resist layer 84 is formed on the wiring 78 and the conductive foil 80.
  • a hole 80a is formed in the conductive foil 80.
  • the method for forming the intermediate layer 76 is the same as the method shown in FIG. 7A, and the method for forming the wiring 78, the hole 80a, and the conductive foil 80 is the same as the method shown in FIGS. 7B to 8A. It is.
  • the solder resist layer 84 is formed in a region avoiding the external electrode 82 (see FIG. 9B).
  • an external electrode 82 is formed on the conductive foil 80, and a residue generated thereby is removed.
  • a coating layer 86 is formed on the external electrode 82 and the solder resist layer 84. (See Figure 9B).
  • the coating layer 86 is formed of a material that is not easily etched under the etching conditions of the intermediate layer 76.
  • a recess 76a is formed in the intermediate layer 76 through the hole 80a of the conductive foil 80 in the same manner as in the step of FIG. 7D, and the coating layer 86 is removed.
  • a semiconductor device 70 shown in C is obtained.
  • the concave portion 76a is formed in the intermediate layer 76, so that no residue remains in the concave portion 76a.
  • the features of the semiconductor device 70 manufactured according to the present embodiment are the same as those of the fourth embodiment.
  • FIGS. 10A to 10C are views showing a method for manufacturing a semiconductor device according to the sixth embodiment.
  • a semiconductor chip 102 having a passivation film 106 formed on an active surface 102 a avoiding the electrode 104 is used.
  • the passivation film 106 is formed of a material having the same properties as the intermediate layer 108 shown in FIG. 10C. That is, the passivation film 106 is formed of a material that is etched under the etching condition of the intermediate layer 108. For example, the case where both the intermediate layer 108 and the passivation film 106 are formed of polyimide resin is applicable.
  • a coating layer 118 is formed on the passivation film 106 at least at a position below the recess 108 a (see FIG. 10C).
  • the coating layer 118 is formed of a material that is not etched under the etching conditions of the intermediate layer 108 and the passivation film 106.
  • the coating layer 118 may be made of a metal thin film such as Cr, Ti-1W, Ti, or the like. I just need.
  • the conductive foil 111, the external electrode 114, and the solder resist layer 116 having the above are formed.
  • the passivation film 106 is covered with the covering layer 118, when the intermediate layer 108 is etched to form the recessed portion 108 a, it is difficult to form the recess 108 a. Etching can be prevented up to the film 106. Thus, it is possible to prevent the active element from being exposed in the concave portion 108a.
  • the features related to the stress relaxation function are the same as in the above-described embodiment.
  • FIGS. 11A and 11B are views showing a part of the semiconductor device according to the seventh embodiment.
  • FIG. 11B is a cross-sectional view taken along the line BB of FIG. 11A.
  • the semiconductor device 120 according to the present embodiment is obtained by forming holes 122, 124 in the substrate 20 and the conductive foil 22 of the semiconductor device 10 shown in FIG.
  • the substrate 20 and the conductive foil 22 are easily deformed, and the stress relaxation function is enhanced.
  • FIG. 12 is a diagram showing a semiconductor device according to the eighth embodiment.
  • a wiring 136 is formed from an electrode 134 on an active surface 132 a of a semiconductor chip 132.
  • An intermediate layer 1 38 is formed on the wiring 1 36.
  • the intermediate layer 1338 is provided with a concave portion 1338a such that the wiring 1336 is exposed at a position above the wiring 1336.
  • a substrate 146 is provided on the intermediate layer 138 via an adhesive 142.
  • a conductive foil 144 is formed on the substrate 146 at a position above the concave portion 138a and on a surface facing the concave portion 138a. Further, a through-hole 146a is formed in the substrate 146 above the recessed portion 138a, so that the conductive foil 144 is exposed from the opposite surface.
  • An external electrode 148 is formed through the through hole 146a.
  • the recesses 138 a are filled with the conductive paste 140.
  • the conductive paste 140 is made of a soft resin like silver (Ag), copper (Cu), silver plated copper, or gold (resin), like the resin 32 filled in the recess 16a shown in FIG. A u) and other conductive fillers are added.
  • the conductive base 144 electrically connects the wiring 136 to the conductive foil 144. Also in the present embodiment, since the recess 138a is formed in the intermediate layer 138, a stress relaxation function can be achieved.
  • FIG. 13A to 14B are views showing a method for manufacturing a semiconductor device according to the ninth embodiment.
  • a semiconductor chip 152 having a passivation film (not shown) formed on an active surface 152a is used, similarly to the semiconductor chip 102 shown in FIG. 1OA.
  • This passivation film is formed from a material to be etched under the etching conditions of the intermediate layer 158.
  • a coating layer 156 is formed on the passivation film on the active surface 152a.
  • the coating layer 156 is formed from a material that is not etched under the etching conditions of the intermediate layer 158 (eg, chrome (Cr), titanium (Ti), titanium tungsten (Ti-W), or copper (Cu)). You.
  • the coating layer 156 is formed, for example, by sputtering.
  • an intermediate layer 158 is formed including over the coating layer 156 and avoiding the electrode 154.
  • the material of the intermediate layer 158 is the same as in the first embodiment.
  • a wiring 160 is formed from the electrode 154 to the intermediate layer 158, and a conductive foil 162 is formed so as to be electrically connected to the wiring 160.
  • Cr chromium
  • Ti titanium
  • Ti-W titanium tungsten
  • Cu copper
  • a metal film in which a plurality of these are laminated is formed by sputtering. This is patterned by etching to form the wiring 160 and the conductive foil 162 integrally.
  • a hole 162a is formed in the conductive foil 162.
  • an external electrode 164 is formed on the conductive foil 162. Specifically, copper (Cu), nickel (Ni), gold (Au), or a bump in which a plurality of these are laminated is formed on the conductive foil 162 by electrolytic plating or electroless plating. An electrode 164 is formed.
  • a solder resist layer 166 is formed on the wiring 160, and a covering layer 168 is formed on the solder resist layer 166.
  • the coating layer 168 also The intermediate layer 158 is formed of a material that is not etched under the etching conditions (for example, chrome (Cr), titanium (Ti), titanium tungsten (Ti-W), or copper (Cu)).
  • a recess 158 a is formed in the intermediate layer 158.
  • the process is the same as the process shown in FIG. 7D. Further, the coating layer 168 is removed by etching. In this example, there is an opening at the center of the external electrode 164, but an opening design as in the seventh embodiment may be used.
  • the semiconductor device 150 also has a stress relief function because the recessed portion 158a is formed in the intermediate layer 158.
  • an end portion of the conductive foil 162 where the hole 162a is formed as shown in FIG. 14B an end portion of the conductive foil 162 where the hole 162a is formed as shown in FIG.
  • An external electrode 170 made of a solder ball may be formed thereon.
  • the present invention is not limited to a CSP type semiconductor device.
  • a deformed portion is directly laminated on an electrode of a semiconductor chip, a semiconductor device having the same size as a flip chip but having a stress relaxation function can be obtained.
  • FIG. 16 shows a circuit board 100 on which the semiconductor device 110 manufactured by the method according to the above-described embodiment is mounted.
  • an organic substrate such as a glass epoxy substrate is used as the circuit board 100.
  • a circuit pattern made of, for example, copper is formed on the circuit board 100 so as to form a desired circuit, and a solder ball is provided on the circuit board 100. Then, by electrically connecting the solder balls of the wiring pattern to the external electrodes of the semiconductor device 110, electrical continuity therebetween is achieved.
  • the semiconductor device 110 is provided with a structure for absorbing a distortion generated due to a difference in thermal expansion with the outside, the semiconductor device 110 is mounted on the circuit board 100. Can also improve the reliability at the time of connection and thereafter.
  • the mounting area can be reduced to the area mounted with bare chips. For this reason, if this circuit board 100 is used for electronic equipment, the size of the electronic equipment itself can be reduced. I can do it. In addition, more mounting space can be secured within the same area, and higher functionality can be achieved.
  • FIG. 17 shows a notebook personal computer 1200 as an electronic apparatus including the circuit board 100.
  • the present invention can be applied to various surface-mount electronic components regardless of whether they are active components or passive components.
  • electronic components include a resistor, a capacitor, a coil, an oscillator, a filter, a temperature sensor, a semiconductor device, a voltage sensor, a volume or a fuse.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Composant à semi-conducteur capable d'absorber efficacement des contraintes thermiques et composé d'un élément à semi-conducteur (12) possédant une électrode (14), une couche de passivation (11) placée au-dessus de la surface dudit élément (12) à l'exception d'au moins une partie de l'électrode (14), une couche conductrice (22) placée au-dessus de la couche de passivation (11) à une distance prédéterminée de cette dernière, une électrode extérieure (26) placée sur la couche conductrice (22), une couche intermédiaire (16) située entre la couche de passivation (11) et la couche conductrice (22) afin de supporter ladite couche conductrice (22), ainsi qu'une interconnexion (18) créant une liaison électrique entre l'électrode (14) et la couche conductrice (22). La couche intermédiaire (16) comporte un évidement (16a) situé sous une zone contenant une jonction avec l'électrode extérieure (26) sur la couche conductrice (22), ledit évidement s'évasant en direction de la couche conductrice (22) depuis la couche de passivation (11).
PCT/JP1999/001409 1998-03-23 1999-03-19 Composant a semi-conducteur, sa fabrication, plaquette de circuit et composant electronique WO1999049511A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019997010795A KR100619568B1 (ko) 1998-03-23 1999-03-19 반도체 장치 및 그 제조방법, 회로기판 및 전자기기
AU28541/99A AU2854199A (en) 1998-03-23 1999-03-19 Semiconductor device, manufacture of semiconductor device, circuit board and electronic device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10/94007 1998-03-23
JP9400798 1998-03-23

Publications (1)

Publication Number Publication Date
WO1999049511A1 true WO1999049511A1 (fr) 1999-09-30

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PCT/JP1999/001409 WO1999049511A1 (fr) 1998-03-23 1999-03-19 Composant a semi-conducteur, sa fabrication, plaquette de circuit et composant electronique

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KR (3) KR100619568B1 (fr)
AU (1) AU2854199A (fr)
WO (1) WO1999049511A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10250634B4 (de) * 2001-10-31 2013-09-05 Qimonda Ag Halbleiterstruktur mit nachgiebigem Zwischenverbindungselement und Verfahren zu deren Herstellung

Citations (2)

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Publication number Priority date Publication date Assignee Title
JPH0621601A (ja) * 1992-07-06 1994-01-28 Mitsui Mining & Smelting Co Ltd プリント配線基板並びにその製造方法及び接続方法
JPH09148475A (ja) * 1995-11-28 1997-06-06 Hitachi Chem Co Ltd 半導体パッケ−ジ

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Publication number Priority date Publication date Assignee Title
US4949148A (en) * 1989-01-11 1990-08-14 Bartelink Dirk J Self-aligning integrated circuit assembly
US5707881A (en) * 1996-09-03 1998-01-13 Motorola, Inc. Test structure and method for performing burn-in testing of a semiconductor product wafer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0621601A (ja) * 1992-07-06 1994-01-28 Mitsui Mining & Smelting Co Ltd プリント配線基板並びにその製造方法及び接続方法
JPH09148475A (ja) * 1995-11-28 1997-06-06 Hitachi Chem Co Ltd 半導体パッケ−ジ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10250634B4 (de) * 2001-10-31 2013-09-05 Qimonda Ag Halbleiterstruktur mit nachgiebigem Zwischenverbindungselement und Verfahren zu deren Herstellung

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KR20060003915A (ko) 2006-01-11
KR100619568B1 (ko) 2006-09-04
KR100583372B1 (ko) 2006-05-26
KR100619567B1 (ko) 2006-09-01
KR20010012830A (ko) 2001-02-26
KR20060069530A (ko) 2006-06-21
AU2854199A (en) 1999-10-18

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