WO1999043183A1 - Vorrichtung und verfahren zur umsetzung von datensequenzen zwischen fr-format und atm-format - Google Patents
Vorrichtung und verfahren zur umsetzung von datensequenzen zwischen fr-format und atm-format Download PDFInfo
- Publication number
- WO1999043183A1 WO1999043183A1 PCT/DE1999/000328 DE9900328W WO9943183A1 WO 1999043183 A1 WO1999043183 A1 WO 1999043183A1 DE 9900328 W DE9900328 W DE 9900328W WO 9943183 A1 WO9943183 A1 WO 9943183A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- atm
- communication module
- format
- connection
- buffer memory
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0478—Provisions for broadband connections
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
- H04L2012/5653—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL]
- H04L2012/5658—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL] using the AAL5
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5665—Interaction of ATM with other protocols
- H04L2012/567—Frame Relay over ATM
Definitions
- the asynchronous transfer mode serves as the basis for universal and international broadband communication, the configurations of which are standardized by the ATM forum founded in 1991.
- the asynchronous transfer mode is an asynchronous time-division multiplex method that enables integration of various communication services, such as voice communication, data communication, video telephone, video communication, etc., with any scalability of the transmission capacity.
- the structure of a typical ATM cell is found for example in Rathgeb, Wall Meier, page 79, is ⁇ .
- Frame Relay enables network access with transmission rates from 64 kbit / s up to 45 Mbit / s, whereby the data frames can have a variable length up to 8 kbyte.
- FR network access is particularly suitable for data communication (e.g. Internet).
- the specifications are standardized by the FR-Foru.
- the structure of an FR frame is described, for example, in Rathgeb, Wallmeier, p. 269 to p. 271.
- interworking can be carried out as so-called network interworking, with the FR frames being converted directly into corresponding ATM frames and vice versa, or through so-called service interworking, the content of which FR frames can be converted into an AAL5 (ATM adaptation layer 5) cell stream.
- AAL5 ATM adaptation layer 5
- Network interworking is in FR-Forum Document No. FRF. 5, the service interworking described in FR forum document No. FRF.8.
- the frames in their control data area often have to be converted, especially in service interworking.
- the frames of an FR- 2 connection stored in the main memory of the central computer (frame processor FP) of the conversion device.
- the central computer reads in the data from the associated interface (for example E1 / DS1 in the FR interface module) by means of read commands or by means of direct memory access (DMA).
- the frames are transferred to a further processing interface, for example an ATM communication module (segmentation and reassembly sublayer SAR) by means of write commands or by means of direct memory access.
- This method has the disadvantage that the central computer cannot continue to work while the data is being transferred to and from the main memory of the central computer, and the program running on it has to be interrupted. This significantly reduces the throughput rate of the conversion device. Long FR frames stop the central computer by waiting times as well as short FR frames put a heavy load on them during processing time.
- a conversion device which has an FR communication module for connection to an FR communication connection, an ATM communication module for connection to an ATM communication connection, a central computer for controlling the FR communication module and the ATM communication module and has a buffer memory which is connected to the central computer, the FR communication module and the ATM communication module via an internal communication connection.
- the data (user data and control data) are not stored in the central computer's memory, but in the buffer 3 S PEICHER stored, the ⁇ its own internal communi cations associated with the FR communication module and the ATM communications module is connected.
- the operation of the central computer does not have to be interrupted while the data is being read in and out.
- the data throughput rate increases since ⁇ through clearly.
- the flow of data transmission between the communication modules and the buffer memory is in this case just ⁇ if controlled by the central computer.
- this control function only contributes to a slight increase in the workload of the central computer.
- the communication modules, the buffer memory and the central computer are preferably connected by means of a bus connection, in particular by means of a powerful PCI bus.
- a separate bus connection can also be provided for each of the communication modules.
- the buffer memory In order to achieve a further increase in throughput, it is possible to divide the buffer memory into two units, one unit for storing the data for further processing in the FR communication module and the other unit for storing the data for further processing in the ATM communication module is. With such an arrangement, it is advantageous to use two separate central computers, one of which is responsible for a "communication direction".
- Figure 1 is a schematic representation of a first embodiment of the transfer device according to the invention.
- FIG. 2 shows a schematic illustration of a second exemplary embodiment of the transfer device according to the invention
- FIG. 4 Figure 3 is a schematic representation of a third exporting ⁇ approximately embodiment of the transfer according to the invention
- FIG. 4 is a schematic illustration of a fourth exemplary embodiment of the transfer device according to the invention.
- FIG. 5 is a schematic illustration of a fifth exemplary embodiment of the conversion device according to the invention.
- Fig. 1 shows a first embodiment of the erfindungsge ⁇ MAESSEN transfer device.
- eight communication connections of the type E1 / DS1 (transmission capacity 2.048 Mbit / s or 1.544 Mbit / s) are connected to the FR communication module.
- the FR-communication module PIM Physical Interface Module
- the FR communication module PIM is connected to the ATM communication module via a PCI (Peripheral Component Interconnect) bus, which in turn consists of the segmentation / concatenation unit SAR in which the AAL5 (ATM adaptation layer) functionality is implemented. and the ATM adaptation layer ALM, which are connected to one another via a Utopia (Universal Test and Operations Physical Interface for ATM) interface.
- PCI Peripheral Component Interconnect
- the PSSM (PIM SAR shared memory) buffer memory which has a dynamic random access memory (DRAM) and an associated memory controller, is also connected to the PCI bus.
- the central computer FP is connected to the PCI bus and can, for example, have a risk CPU, a system control, a memory, a clock control, etc.
- the second embodiment of the transfer device according to the invention differs from the first embodiment only in that between 5 FR communication module and buffer memory on the one hand and Zvi ⁇ rule ATM communications module and buffer memory on the other hand separate bus connections are provided. Both bus connections are connected to the central computer FP, which controls the data transmission processes on the bus connections.
- the buffer memory PSSM is divided into two units in order to further increase the performance, the first unit for the transmission from the FR side to the ATM side and the second unit for the transmission of the ATM side to the FR side.
- Module in the FR communication module PIM and the SAR module in the ATM communication module are formed in two parts, one part being responsible for a direction of transmission. --- As a result, a further increase in speed can be achieved, on the other hand also increasing the construction effort.
- the conversion device of the third exemplary embodiment which is shown in FIG. 5, additionally contains separate bus connections for the reading process into the buffer memory PSSM on the one hand and for the reading process from the buffer memory on the other hand.
- the read-in and read-out process can be carried out independently of one another for both transmission directions, which enables a further increase in the transmission power.
- FR data sequences are read from the physical interfaces by the FR communication module PIM and then stored under the control of the central computer FP in the buffer memory PSSM. Then the data, again under the control of the central computer, via the PCI bus 6 read the ATM communication module.
- the segmentation / concatenation unit SAR carries out the integration of the header data and concatenation of the data to be transferred in ATM cells supplied via the Utopia interface of the ATM Adaptions slaughter- processing unit ALM and there on Ricoan ⁇ circuits Y b, for example for Further processing can be made available in a switching matrix.
- the data sequences in ATM format pass from the ATM adaptation layer processing unit via the Utopia interface to the segmentation chaining unit SAR, where the ATM cells are linked and stored on the buffer memory PSSM via the bus connection. From there, the data are read in by the FR communication module PIM, converted into the FR format with frames of variable length and then fed to one of the physical interfaces.
- a prerequisite for high transmission performance is the PCI burst capability of all connected PCI bus users as well as the performance of the central computer FP. Although this does not access the PSSM buffer memory too often, it must have a high conversion speed for the service interworking functionality.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Communication Control (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99915462A EP1057362A1 (de) | 1998-02-20 | 1999-02-08 | Vorrichtung und verfahren zur umsetzung von datensequenzen zwischen fr-format und atm-format |
US09/622,564 US6870853B1 (en) | 1998-02-20 | 1999-02-08 | Device and method for converting data sequences between FR format and ATM format |
CA002321210A CA2321210A1 (en) | 1998-02-20 | 1999-02-08 | Device and method for converting data sequences between fr format and atm format |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19807251A DE19807251A1 (de) | 1998-02-20 | 1998-02-20 | Vorrichtung und Verfahren zur Umsetzung von Datensequenzen zwischen FR-Formaten und ATM-Formaten |
DE19807251.1 | 1998-02-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1999043183A1 true WO1999043183A1 (de) | 1999-08-26 |
Family
ID=7858461
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1999/000328 WO1999043183A1 (de) | 1998-02-20 | 1999-02-08 | Vorrichtung und verfahren zur umsetzung von datensequenzen zwischen fr-format und atm-format |
Country Status (5)
Country | Link |
---|---|
US (1) | US6870853B1 (de) |
EP (1) | EP1057362A1 (de) |
CA (1) | CA2321210A1 (de) |
DE (1) | DE19807251A1 (de) |
WO (1) | WO1999043183A1 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105187363B (zh) * | 2014-12-11 | 2018-08-24 | 中车青岛四方机车车辆股份有限公司 | 实现mvb数据与vme数据协议互通的方法和装置 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5315588A (en) * | 1993-03-19 | 1994-05-24 | Fujitsu Limited | Method of controlling frame-relay module, and high-speed switching system |
EP0775958A1 (de) * | 1995-11-06 | 1997-05-28 | Sun Microsystems, Inc. | Mechanismus zur Verminderung zusätzlichen Aufwands beim Kopieren von Daten in geschützten Speicher-Betriebssystemen |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997024842A2 (en) * | 1995-12-29 | 1997-07-10 | Mci Communications Corporation | Method and system for resilient frame relay network interconnection |
KR100243415B1 (ko) * | 1997-12-17 | 2000-02-01 | 이계철 | 프레임 릴레이 망 연동용 에이티엠 스위치 정합장치 |
US6205152B1 (en) * | 1997-12-31 | 2001-03-20 | Samsung Electronics Co., Ltd. | Frame relay-to-ATM interface circuit and method of operation |
US6252887B1 (en) * | 1998-01-28 | 2001-06-26 | Northern Telecom Limited | Cell to frame conversion management |
-
1998
- 1998-02-20 DE DE19807251A patent/DE19807251A1/de not_active Withdrawn
-
1999
- 1999-02-08 EP EP99915462A patent/EP1057362A1/de not_active Withdrawn
- 1999-02-08 US US09/622,564 patent/US6870853B1/en not_active Expired - Fee Related
- 1999-02-08 CA CA002321210A patent/CA2321210A1/en not_active Abandoned
- 1999-02-08 WO PCT/DE1999/000328 patent/WO1999043183A1/de not_active Application Discontinuation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5315588A (en) * | 1993-03-19 | 1994-05-24 | Fujitsu Limited | Method of controlling frame-relay module, and high-speed switching system |
EP0775958A1 (de) * | 1995-11-06 | 1997-05-28 | Sun Microsystems, Inc. | Mechanismus zur Verminderung zusätzlichen Aufwands beim Kopieren von Daten in geschützten Speicher-Betriebssystemen |
Non-Patent Citations (1)
Title |
---|
LEE B -H ET AL: "A PERFORMANCE STUDY ON FRAME RELAY AND ATM INTERWORKING UNIT AND ITS APPLICATIONS: CONNECTIONLESS DATA SERVICE AND VPN", IEICE TRANSACTIONS ON COMMUNICATIONS, vol. 80-B, no. 6, 1 June 1997 (1997-06-01), pages 948 - 962, XP000723073, ISSN: 0916-8516 * |
Also Published As
Publication number | Publication date |
---|---|
CA2321210A1 (en) | 1999-08-26 |
US6870853B1 (en) | 2005-03-22 |
EP1057362A1 (de) | 2000-12-06 |
DE19807251A1 (de) | 1999-09-02 |
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