WO1999043029A1

WO1999043029A1 - Trench-gate mos transistor, its use in an eeprom device and process for manufacturing the same

Info

Publication number: WO1999043029A1
Application number: PCT/DE1999/000215
Authority: WO
Inventors: Franz Hofmann; Josef Willer; Wolfgang Krautschneider
Original assignee: Infineon Technologies Ag
Priority date: 1998-02-20
Filing date: 1999-01-27
Publication date: 1999-08-26
Also published as: TW442949B; EP1060518A1

Abstract

A first source-drain zone (471), a second source/drain zone (472) and an intermediate channel (44) are arranged in a semiconductor substrate (41). The surface of the channel (44) is provided with a gate dielectric (45). A gate electrode (46) is arranged in the channel (44) and is at the most as long as the channel (44) is deep. Gate dielectric (45) and gate electrode (46) are thus buried in the channel (44) and the MOS transistor is suitable as embedded MOS transistor, in particular for EEPROM devices.

Description

description

TRENCH GATE MOS TRANSISTOR, THE USE THEREOF IN AN EEPROM ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF

The invention relates to a MOS transistor that is suitable for integration in a circuit arrangement with transistors of another technology, so-called embedded MOS transistor, and a method for its production.

In different circuit applications, transistors with very different properties are required at the same time, which can be produced in different technologies. An example of this are EEPROM applications in which MOS transistors with floating gate and control gate, which are operated with voltages of a maximum of 5 volts, are used as storage transistors and in which so-called high-voltage transistors, which have higher voltages, are used for programming the storage transistors , in particular 10 to 20 volts, switch. Smart power circuits are further examples of such applications.

It is known in the manufacture of an EEPROM arrangement to manufacture the required high-voltage transistors in the same process in which the memory transistors are also manufactured (see, for example, Seiichi Mori: "High Speed Sub-halfmicron Flash Memory Technology", 1994 Symposium on VLSI Technology , p 53) The disadvantageous effects of the process steps required for the manufacture of the high-voltage transistors on the properties of the memory transistors are accepted.

The invention is based on the object of specifying a MOS transistor which can be produced simultaneously with transistors of another technology without adversely affecting the properties of the transistors of the other technology. rivers. A method for producing such a MOS transistor is also to be specified.

This object is achieved by a MOS transistor according to claim 1 and by a method for its production according to claim 10. Further refinements of the invention emerge from the remaining claims.

The MOS transistor comprises a first source / dram device and a second source / dram device which are arranged in a semiconductor substrate. A monocrystalline silicon substrate or the monocrystalline silicon layer of an SOI substrate are particularly suitable as the semiconductor substrate. A trench is arranged between the first source / dram area and the second source / dram area, the depth of which is greater than the depth of the first source / dram area and the second source / dram area. The surface of the trench is provided with a gate dielectric. A gate electrode is arranged in the trench, the extent of which in the direction of the depth of the trench is at most equal to the depth of the trench. The MOS transistor has a channel region which is arranged between the first source / dram region and the second source / dram region and runs in the semiconductor substrate along the surface of the trench. When the transistor is switched, a current path along the surface of the trench is therefore closed or interrupted.

An isolation trench is provided which surrounds the MOS transistor. The isolation trench is provided with an insulating filling and has a depth which essentially corresponds to the depth of the trench. The isolation trench is preferably opened at the same time as the trench. No additional photo technology is therefore required for the trench etching.

Since in the MOS transistor the gate oxide and the gate electrode are arranged completely in the trench and the channel region arranged along the surface of the trench, this MOS transistor can be produced before the production of transistors of other technology. It is within the scope of the invention that the gate electrode completely fills the trench or that a planing structure fills the trench above the gate electrode. After the production of the MOS transistor, the semiconductor substrate has a flat surface and is suitable for the production of the other transistors in a different technology.

The MOS transistor is particularly suitable as a high-voltage transistor for an EEPROM arrangement. Since the channel area runs along the surface of the trench, the space requirement of the MOS transistor is reduced in comparison with a pianar MOS transistor. The higher thickness of the gate dielectric required for high-voltage transistors in comparison to the memory transistors has no effect on the memory transistors, since the gate dielectric is only arranged on the surface of the trench. The channel implantation for the high-voltage transistor also only affects the trench surface.

The MOS transistor can be designed both as an n-channel MOS transistor and as a p-channel MOS transistor. For use as a high-voltage MOS transistor of an EEPROM arrangement, it is advantageous if the MOS transistor as an n-channel MOS transistor is an n ⁺ -doped gate electrode and as a p-channel MOS transistor is a p ⁺ -dotιerte Has gate electrode. In this case it is ensured that both the n-channel MOS transistor and the p-channel MOS transistor are so-called surface-channel transistors, with which a conductive channel is formed on the interface of the substrate to the gate dielectric .

For the application of the MOS transistor as a high-voltage MOS transistor, it is advantageous to provide a first diffusion region which is arranged between the first source / dram device and the channel region and which is connected to the first source / Drain area and adjacent to the channel area. The first diffusion region is doped with the same conductivity type as the first source / drain region, it has a lower dopant concentration than the first source / drain region. In the circuit, the first source / drain

Area interconnected as a drain. A portion of the voltage present between the first source / drain region and the second source / drain region drops across the first diffusion region, so that only a lower voltage has to be switched across the channel region.

In view of the reduced space requirement of the MOS transistor, it is advantageous to arrange the first diffusion region at least partially below the first source / drain region. In this way, the space requirement parallel to the surface of the semiconductor substrate is reduced.

The MOS transistor is preferably designed such that the first source / drain region does not directly adjoin the surface of the trench. This increases the dielectric strength between the gate electrode and the first source / drain region. In particular, voltage peaks and a band-to-band tunnel at the edge of the gate electrode are avoided. This configuration of the MOS transistor can be realized in that the first diffusion region is arranged at least partially between the surface of the trench and the first source / drain region. In this way, since the first diffusion region acts as a resistance, over which part of the voltage drops, the voltage effective at the edge of the trench is reduced.

As an alternative, this embodiment is realized in that a first insulation structure is provided, which is arranged between the gate electrode and the first source / drain region. The first insulation structure thus adjoins the surface of the semiconductor substrate and has a depth that is greater than the depth of the first source / drain Area. In this way, the insulation between the gate electrode and the first source / dram device, to which high voltage is applied, is improved.

In view of a simplified circuit design, it is advantageous to provide a second diffusion region which is doped with the same conductivity type as the second source / drain region, but which has a lower dopant concentration than the second source / dram region, and that is arranged between the second source / dram Gebιet and the channel area. The second diffusion area borders both on the second source / dram area and on the channel area. The second diffusion area is constructed analogously to the first diffusion area. In this way, the MOS transistor has a symmetrical structure. Both the first source / dram device and the second source / dram device can be connected as a drain in a circuit. This facilitates the circuit design.

Exemplary embodiments of the invention are explained in more detail below with reference to figures.

FIG. 1 shows a section through a MOS transistor with a gate electrode arranged in a trench.

FIG. 2 shows a section through a MOS transistor with a gate electrode arranged in a trench and a first source / dram device and a second source / dram device, under each of which a first diffusion area or a second diffusion area is arranged.

FIG. 3 shows a section through a MOS transistor with a gate electrode arranged in a trench and a first source / dram device and a second one

Source / Dram Gebιet, each by a first Diffusion area or a second diffusion area are separated from the surface of the trench.

FIG. 4 shows a section through a MOS transistor with a gate electrode arranged in a trench, a first insulation structure being provided between the gate electrode and a first source / drain region and between the gate electrode and a second source / drain - Area is arranged.

5 to 8 show steps for producing a

MOS transistor with a first insulation structure, which is arranged between a first source / drain region or a second source / drain region and a gate electrode.

9 to 12 show steps for producing a

MOS transistor with a gate electrode arranged in a trench and a first source / drain region and a second source / drain region which are spaced apart from the surface of the trench.

FIGS. 13 to 16 show steps for producing a MOS transistor with a gate electrode arranged in the trench and a first source / drain region and a second source / drain region, each through a first diffusion region and a second diffusion region are spaced from the surface of the trench.

In a substrate 11 of monocrystalline p-doped silicon with a basic doping of 10 ^ 5 _cm -3 j_ _s -j- _e i _ne p-doped well 12 is disposed (see Figure 1). The p-doped well 12 has a dopant concentration of 10 ¹⁷ cm ^~ 3. The p-doped well 12 is surrounded by an isolation trench 13, which has an SiO 2 layer 131 and an SiO 2 layer Filling 132 is filled. The isolation structure 13 is produced using the shallow trench isolation technique.

A trench 14 is arranged within the area surrounded by the insulation structure 13 and extends to the p-doped well 12 up to m. The depth of the trench 14 is 400 nm. The depth of the isolation trench 13 is also 400 nm.

The surface of the trench 14 is provided with a gate dielectric 15. The gate dielectric 15 contains S1O2 and has a thickness of 20 n. The trench 14 is filled with a gate electrode 16 made of n ⁺ -doped polysilicon. The trench 14 filled with the gate dielectric 15 and the gate electrode 16 forms a flat surface with the substrate 11.

A first source / dram unit 171 and a second source / dram unit 172 are provided, each of which adjoins the isolation trench 13. The first source / dram unit 171 and the second source / dram unit 172 are n ⁺ -doped with a dopant concentration of 10 ^ 1 cm ^" ^. The first source / dram unit 171 and the second source / Dram area 172 has a depth of approximately 200 nm. A first diffusion region 181 is arranged between the first source / drain area 171 and the surface of the trench 14. Between the second source / drain area 172 and the surface of the A second diffusion region 182 is arranged in trench 14. The first diffusion region 181 and the second diffusion region 182 are each n ^~ -doped and have a dopant concentration of 2 × 10 ¹⁸ cm ^-3 . The channel region acts on the surface of the trench below part of the p-doped well 12 of the first diffusion region 181 and the second diffusion region 182.

There is an insulating layer on the surface of the structure

19 arranged, for example, of doped glass, in which contacts 120 to the first source / dram device 171, the second Source / Dram Gebιet 172 and the gate electrode 16 are provided. The contacts 120 contain aluminum and / or tungsten.

In a substrate 21 of silicon with a basic doping monokristallmem of lO ^ ¹ cm ^-3 boron is arranged a p-doped well 22 having a dopant concentration of 10 ¹⁷ cm ^-3 (see Figure 2). An active area for a MOS transistor is defined by an isolation trench 23, which is annular. The isolation trench 23 is filled with a layer 231 and a layer 232 232 in the sense of shallow trench insulation. The depth of the isolation trench 23 is 600 nm. A trench 24, the depth of which is also 600 nm, is arranged in the active region. The surface of the trench 24 is provided with a gate dielectric 25. The gate dielectric 25 contains S1O2 and has a thickness of 25 nm. The trench 24 is filled with a gate electrode 26. The gate electrode 26 contains n ⁺ -doped polysilicon with a dopant concentration of 10 ^ 1 cm ^-3

Between the isolation trench 23 and the surface of the trench 24, a first source / drain device 271 and a second source / dram device 272 are arranged, each of which adjoins the surface of the substrate. The first source / dram region 271 and the second source / dram region 272 are n ⁺ -doped with a dopant concentration of 10 ^ ° cm ^-3. The first source / dram region 272 and the second source / Dram-Gebιet 272 each have a depth of 200 nm.

A first diffusion region 281 is arranged below the first source / dram region 271, which is n ^~ -doped with a dopant concentration of 10 ^ - ⁸ cm ^-3 and which has a depth of 500 nm measured from the surface of the substrate 21 . A second diffusion region 282, which is n ^~ -doped and has a dopant concentration of 10 ¹⁸ cm ^-3, is arranged below the second source / dram region 272 and has a depth of 300 nm below the surface of the substrate 21.

The first source / dram device 271 is connected as a drain in the MOS transistor. A portion of the voltage applied to the first source / dram region 271 then drops across the first diffusion region 281. A lower voltage then drops across the channel region, which is formed by that part of the p-dot well 22 which adjoins the surface of the trench 24.

An insulation layer 29 made of doped glass is arranged on the surface of the structure, in which contacts 220 are provided to the first source / dram region 271, the second source / drain region 272 and the gate electrode 26 (see FIG. 2).

In a substrate 31 made of silicon monokristallmem with a basic doping of lO ^ ¹ cm ^-3 boron, a p-doped well 32 is disposed with a dopant concentration of 10 ¹⁷ cm ^-3 (see Figure 3). An active region for a MOS transistor is defined in the p-doped well 32 by an annular isolation trench 33. In the sense of shallow trench isolation, the isolation trench 33 is filled with a Si2 layer 331 and a Si2 filling 332. The depth of the isolation trench 31 is 800 nm.

A trench 34, the depth of which is also 800 nm, is arranged within the active region. The surface of the trench 34 is provided with a gate dielectric 35 which

Contains S1O2 and has a thickness of 25 nm. The trench 34 is filled with a gate electrode 36 made of n ⁺ -doped polysilicon with a dopant concentration of lθ21 _C m ^{~ 3} .

There are a first source / drain unit 371 and a second one

Source / Dram Gebιet 372 provided, each adjoining the surface of the isolation trench 33 and the 10

Adjacent the surface of the substrate 31. The source / drain regions 371, 372 are n ⁺ -doped and have a dopant concentration of 10 ^ 1 cm ^-3 . They have a depth of 200 nm. They are spaced from the surface of the trench 34 by a first diffusion region 381 or a second diffusion region 382. The first diffusion region 381 and the second diffusion region 382 also extend below the first source / dram region 371 and the second source / dram region 372. The first diffusion region 381 and the second diffusion region 382 are each n ^~ - dyes with a dopant concentration of 10 ^ cm ^{"" 3} . The diffusion regions 381, 382 have a depth of 400 nm measured from the surface of the semiconductor substrate. The part of the p-doped well 32 which adjoins the surface of the trench 34 acts as the channel region in the MOS transistor.

The structure is also provided with an insulation layer 39 made of doped glass, in which contacts 320 are provided to the first source / dram region 371, the second source / dram region 372 and the gate electrode 36.

A p-doped trough 42 with a dopant concentration of 10 ¹⁷ cm ^{-3 is} arranged in a substrate 41 with a basic doping of 10 ^ cm ^-3 boron (see FIG. 4). A πng-shaped isolation trench 43, which in the sense of a shallow

Trench insulation is filled with a Si2 layer 431 and a S1O2 filling 432, defines an active area for a MOS transistor. The depth of the isolation trench 43 is 800 nm.

In addition, a trench 44 is arranged in the active area, the depth of which is also 800 nm. In the area of the surface of the substrate 41, the trench 44 has an expansion which is provided with an insulation structure 441. Below the insulation structure 441, which contains S1O2, the surface of the trench 44 is provided with a gate dielectric 45. The gate dielectric 45 contains S1O2 and has one 11

Thickness of 25 nm. Within the insulation structure 441 and the gate dielectric 45, the trench 44 is filled with a gate electrode 46 made of n ⁺ -doped polysilicon with a dopant concentration of 10 ²¹ cm ^-3 . The gate electrode 46 terminates at the height with the substrate 41.

A first source / drain device 471 and a second source / drain device 472 are arranged between the insulation structure 441 and the Si2 filling 432 of the isolation trench 43. The source / dram units 471, 472 are n ⁺ -doped and have a dopant concentration of 10 ² 1 cm ^-3 . They have a depth of 200 nm.

A first diffusion region 481 and a second diffusion region 482 are arranged below the first source / drain region 471 and the second source / drain region 472. The first diffusion region 481 and the second diffusion region 482 are each n ^~ -doped and have a dopant concentration of 10 ^ ⁸ cm ^-3 . Measured from the surface of the substrate 41, they have a depth of 500 nm.

The isolation structure 441 has a depth of 300 nm. The width of the insulation structure 441 is dimensioned such that the distance of the first source / drain device 471 or the second source / dram device 472 from the gate electrode 46 is 100 nm parallel to the surface of the substrate 41. This improves the dielectric strength of the MOS transistor. The part of the p-doped well 42 adjacent to the surface of the trench 44 acts as the channel region.

The structure also has an insulation layer 49 made of doped glass, in which contacts 420 are provided to the first source / dram device 471, the second source / dram device 472 and the gate electrode 46.

In a substrate 51 made of monolithic silicon with a basic doping of 10 ^ _cm ^{~ 3} boron is replaced by a number of 12

Implantations with boron with 3 x 10 ^ cm ^-2 , 500 keV or 5 x 10 ¹² cm ^-2 , 200 keV formed a p-doped well 52 with a dopant concentration of 10 ^ - ⁷ cm ^-3 and a depth of 1000 nm (see Figure 5). A photolithographically generated resist mask (not shown) is used.

A diffusion region 53, which has a dopant concentration of 10 ¹⁸ cm ^-3 and a depth of 500 nm, is subsequently produced by implantations with phosphorus with an energy of 100 keV, 200 keV and a dose of 8 × 10 ^ ² cm ^-2 each having. After removal of the resist mask, a first layer 54 is applied with a thickness of 20 nm and a silicon nitride layer 55 m with a thickness of 100 nm. First trenches 56 are etched using a photolithographically generated mask (not shown). The first trenches 56 have a depth of 300 nm. The first trenches 56 have an annular part and a web that connects opposite sides of the annular part to one another. For etching the silicon nitride layer 55, CHF3, 02 of the first silicon layer 54 is used CHF3, O2 and the silicon HBr, He, O2, NF3 is used.

The first trenches 56 are filled with a first SiO 2 filling 57. For this purpose, a layer of SiO 2 is deposited and planed by chemical-mechanical polishing.

Subsequently, second trenches are etched using a photoresist mask (not shown). The second trenches comprise a trench 58 and an isolation trench 59 (see FIG. 6). Both the trench 58 and the isolation trench 59 are arranged parallel to the surface of the substrate 51 within the cross section of the first trench 56. The cross section of the trench 58 and the isolation trench 59 is in each case smaller than the cross section of the corresponding part of the first trench 56. The depth of the trench 58 and the isolation trench 59 is greater than that of the first trench 13

56. The depth of the trench 58 and the isolation trench 59 is approximately 800 nm.

The trench 58 structures the first fill 57, so that a first insulation structure 571 is formed, which is arranged in the upper region of the trench 58 on both sides of the trench 58 (see FIG. 6). The dimension of the first insulation structure 571 perpendicular to the wall of the trench 58 is 100 nm.

A gate dielectric 5101 made of S1O2 m with a layer thickness of 25 nm is formed on the surface of the trench 58 by thermal oxidation. At the same time, during the thermal oxidation, a second SiO 2 layer 5102 m with a layer thickness of likewise 25 nm is formed on the surface of the isolation trench 59.

By forming a doped polysilicon layer and then scratching the doped polysilicon layer back with CFg, O2, 2, a gate electrode 5111 is formed in the trench 58 and a polysilicon fill 5112 is formed in the isolation trench 59. The gate electrode 5111 is n ⁺ -doped with a dopant concentration of 10 ²¹ cm ^{"" 3} .

The doped polysilicon layer is formed by in situ doped deposition or by undoped deposition and subsequent implantation. The doped polysilicon layer is etched back to the extent that the gate electrode

5111 is flush with the surface of the substrate 51.

Using a resist mask 512 formed with photolithographic steps as an etching mask, which covers the area of the trench 58 and the first insulation structure 571, the polysilicon filling is made with the aid of He, HBr, CI2, C2Fg

5112 removed from the isolation trench 59. Using CHF3, O2, the one adjacent to the isolation trench 59 14

Part of the first SiO 2 filling 57 removed (see FIG. 7). After removal of the resist mask 512, the insulation trench 59 is filled with a second SiO 2 filling 513 by depositing an SiO 2 layer and chemical-mechanical polishing (see FIG. 8). The silicon nitride layer 55 and the first SiO 2 layer 54 are then removed. This creates a flat surface of the structure.

The MOS transistor is formed by forming a first source / drain region 5141 and a second source / drain region 5142 with the aid of a masked implantation of arsenic at an energy of 60 keV and a dose of 5 × 10 ^ - cm ^{- 2} completed. The depth of the source / drain regions 5141, 5142 is 200 nm. It is therefore less than the depth of the first insulation structure 571. The less doped diffusion regions 52 are arranged below the source / drain regions 5141, 5142. Parts of the p-doped well 52 adjacent to the surface of the trench 58 form the channel region.

If the MOS transistor is manufactured as part of the manufacture of an EEPROM arrangement, the process for manufacturing the memory transistors and peripheral transistors is carried out before the implantation to form the source / drain regions 5141, 5142. Since both the gate electrode 5111 and the gate dielectric 5101 are buried in the trench 58 and the structure has a flat surface, these structures do not influence the process flow for the memory transistors and the peripheral transistors.

A p-doped well 62 with a dopant concentration of 10 ^ ⁷ cm ^{-3 is} formed by masked implantation with boron in a substrate 61 made of monocrystalline silicon with a basic doping of lθl5 _C m ^-3 boron. The depth of the p-doped well 62 is 1000 nm (see FIG. 9). O 99/43029

15

A first S1O2 layer 63 m with a layer thickness of 20 nm and a silicon nitride layer 64 m with a layer thickness of 100 nm are applied to the surface of the substrate 61. Using a photolithographically produced resist mask (not shown), the silicon nitride layer 64, the first silicon layer 63 and the substrate 61 are structured such that a trench 65 and an isolation trench 66 with a depth of 600 nm are formed. In this case, CHF3, O2, S1O2, CHF3, O2 and S1I1- zium HBr, He, O2, NF3 are used for the etching of silicon nitride. The isolation trench 66 surrounds an active area in a ring shape. The trench 65 has a web-shaped cross section and extends from one side of the isolation trench 66 to the opposite side.

Through an oblique implantation of boron, in which the substrate 61 is rotated, the dopant concentration of the p-doped well 62 along the surface of the trench 65 is set to 10 1 ⁷ cm ^-3 . This determines the threshold voltage of the MOS transistor to be manufactured. The implantation is carried out with an energy of 50 keV and a dose of 2 x 10 ¹² cm ^-2 .

A gate dielectric 67 made of S1O2 m with a layer thickness of 25 nm is formed on the surface of the trench 65 by thermal oxidation. At the same time, a second layer 68 is formed on the surface of the isolation trench in a layer thickness of likewise 25 nm (see FIG. 10).

A gate electrode 691 and a polysilicon fill 692 are subsequently formed by forming a doped polysilicon layer and scratching the doped polysilicon layer with CF4, O2, N2. The doped polysilicon layer is formed by in situ doped deposition or by undoped deposition and subsequent implantation. The jerking is continued until the surface of the gate electrode 691 is flush with the surface of the substrate 61. O 99/43029

1 6

Using a resist mask covering the gate electrode 691, the polysilicon fill 692 is removed from the isolation trench 66 by etching with He, HBr, CI2, C2F. The isolation trench 66 is provided with an SiO 2 filling 610 by depositing an SiO 2 layer and chemical mechanical polishing (see FIG. 11). The silicon nitride layer 64 is subsequently removed. Using a photolithographically produced mask, a first diffusion region 6111 with a dopant concentration of 10 ¹⁸ cm ^{"" 3 is} formed by implantation with phosphorus with a dose of 4 × 10 ^ ² cm ^-2 and an energy of 45 keV. The first diffusion region 6111 has a depth of 300 nm. It is arranged on one side of the trench 65.

Using a further resist mask (not shown), which covers the first diffusion region 6111, a second diffusion region 6112 is created on the opposite side of the trench 65 by implantation of phosphorus with a dose of 4 × 10 ^ ² cm ^-2 and an energy formed by 90 keV (see Figure 12). The depth of the second diffusion region 6112 is 500 nm. The dopant concentration of the second diffusion region 6112 is 10 ^ ⁸ cm ^-3 .

With the aid of a further resist mask (not shown), a first source / drain region 6121 is formed within the first diffusion region 6111 and a second source / drain region 6122 is formed within the second diffusion region. For this purpose, an implantation with arsenic is carried out at an energy of 60 keV and a dose of 5 x 10 ^^ cm ^{"" 2} . The first

The source / drain region 6121 and the second source / drain region 6122 each adjoin the surface of the isolation trench 66. They do not adjoin the surface of the trench 65. The first source / drain region 6121 is spaced from the surface of the trench 65 by a part of the first diffusion region 6111 and the second source / drain region 6122 is spaced by a part of the second diffusion region 6112. The 17 part of the p-doped well 62 adjoining the surface of the trench 65 acts as a channel region.

When the MOS transistor is manufactured within an EEPROM arrangement, the processes for manufacturing memory transistors and peripheral transistors are carried out before the implantations to form the first diffusion region 6111. As a result, tempering steps which are necessary for activating implanted dopant can be carried out simultaneously for the buried MOS transistor as well as for memory transistors and peripheral transistors.

A first SiO 2 layer 72 and a silicon nitride layer 73 are applied to the surface of a substrate 71

(see Figure 13). The substrate 71 contains monocrystalline silicon with a basic doping of 10 ^ cm ^-3 boron. The first SiO 2 layer 72 is applied in a layer thickness of 20 nm and the silicon nitride layer 73 is applied in a layer thickness of 100 nm. Using a photolithographically produced mask (not shown), a trench 74 and an isolation trench 75 are produced by structuring the silicon nitride layer 73, the first SiO 2 layer 72 and the substrate 71. For this, anisotropic etching is used, HBr, He, O2, NF3 being used to etch the silicon nitride layer 73 CHF3, O2, the SiO2 layer 72 CHF3, O2 and the substrate 71. The depth of the trench 74 measured from the surface of the substrate 71 is 400 nm.

The isolation trench 75 surrounds an active area for a MOS transistor in a ring shape. The trench 74 is located within the active area. It has a web-shaped cross section and extends from one side of the isolation trench 75 to the opposite side.

Using a mask 76, which covers the isolation trench 75, as an implantation mask, by implantation of co co r>P> - ^y

Cπ o cπ o cn o cn

^• Q yQ Φ Φ 13 sv α HI a CΛ 3 Hl aa rt Ω P a Hl cn et o -l LP Z IV ⁾ N Φ CΛ PJ 2. Hl öd

Φ φ PP A- ^y Φ P Φ PP Φ Φ P φ PP tr P Φ O Ω P ao P Φ P cn z PPP PJ oo σ tr PP PJ rt P Φ O Ω P Φ Ω rt Φ φ CΛ P tr O Φ P ^J PJ PN φ et O Ω P ¹ PO

P P φ P. -. Φ P M tr P SV Φ P P a et P P P • tr a P P P cn t \ j a tr yQ V ©

A- φ Φ P rt PP rt CΛ 1 P> rt <v rt P cn Φ CΛ ^y Q Ω cn Φ Φ P 3 ft et Φ rt Φ V © a rt P PJ PP n P. o - • rt PJ PP Φ tr ^y Q rt ^J a PPP 3 φ Φ PPWP

Φ IA

CΛ w Ω <PPP <O tr tr CΛ rt Φ P cn - tr PP 3 PO rt -0 rt PP tr Φ P A- ^y ω σ ^■ PJ Φ Hi • tu CΛ Φ tr PP -JP Ω ω CΛ rt o rt P Φ.

P> Φ φ o rt PN Ω P ω P Hi o et rt Φ P Ω N cn 3 tr PP Φ tr H) et O. P- ¹ cn PP Ξ PP tr PP cn z V σ tr PNP 'tr PP φ o PJ P Φ Φ Ό

CΛ) vP a Φ PP Φ Ω A- ^y φ o P Φ PJ rt Hi ap Φ Ω Ω tr PPPP tv. 1

P σ P PJ P 3 ^y Q cn tr PPP Φ et o Φ P 3 PP tr Φ 1 Φ Hi P oa

Φ 3 P φ OP ap N rt a N 3 CΛ Z rt P ω PJ et CΛ a P Φ O o tr P Hl P t PP ^ J <x) e PNP Φ Ω PP ^y Q • ao Φ tr ^» n Ω Φ JP rt

Φ rt Hl <φ P rt P ¹ O p 3 PP PJ et - P rt o tr φ PP tr P CΛ Ω SV P

P o t. cn ιp P o P ^J CΛ PJ vp rt rt P ¹ a O rt P • X) PP ^y QPO tr

P a Φ φ ⁱ n Φ cn P tr rt P Ω Hl CΛ P Φ a 3 PJ P Ω oa P Ω o tr Φ <P

P P P o φ Φ a <! φ tr P SV φ J Φ Φ Φ P CΛ Φ tr -j P tr tr P P et

> PPO ► £ cn P ^J P ω Φ P Φ A- φ P rt PP tr et P rt • Ji> to rt Φ Ω a SV Φ

P Φ P cn Ό H- P Ω P φ P A- P P Φ et P tö et ω P P tr Φ S φ

PP CΛ t rt φ tr cn P a P z φ o SV o CΛ cn Ω P Φ ZP φ Ω j ^ -J Hl et CΛ J <s vP SV o PP φ Φ PPPP rt tr Ό ^ Ω P A- P SV - - - 00 a CΛ PJ

P ¹ D Φ Φ P Ω tr Ξ P yQ PP Φ P a Ob. t SPPP PJ •> JP Ω VPP

CTi O tr <. PJ TS tr φ P a s <O P P P ^ J a N φ rt Ω Ω P φ P P

- - rt P 3 P "tr rt PP Φ ^• ~ j J oa Hl Ω φ et CΛ PN ö P tr SV J a φ

. P φ s: P cn oa P CD a CΛ P φ P ^ tr ON Ω a P Ω Φ PP Φ Φ tr -J φ rt rt rt -J - - P) P? V PJ rt tu ho Φ tr P 3 PJ PP Φ σ co -

P P O co cn a φ P φ Ω • o P φ P Hl rt Ω Φ a <P -J

CΛ -J a Φ 3 A- 'P Φ P ⁾ Ω O CD tr tr P Ω P Φ a tr P Φ o CΛ s: X rt P ¹ Φ P Ό P a φ PP tr N> A- ^y Φ ü Φ ≥! aa tr H ¹ Φ Φ P cn PP φ

OP 'PP rt P tr CΛ CΛ a PM Φ P - ^y P öd φ -JPP ¹ • ~ i P ^

Hi P> Φ PJ tr P φ M P> P P a φ a • ». P P P P P P P M tv> a o N 00

Hl tr PPO Ω CΛ oa rt Φ Ω cn Φ Φ LP PPV a - ^y CΛ cn P ¹ Φ sv P Φ rt <P tr ^ O> Φ N 3 rt cn Ω P ≤ a vp et oa CΛ O Φ al \ JP o PP ö PJ PP 1 3 Φ a 1 JO o P CΛ P et P Ω A- ^y PPP yQ

P a a o rt PJ> yQ PJ cn P P co P CΛ et Ω tr et P P - O P P tr PJ 3 P P Ω rt

N Φ cn P ^• Ό rt P rt Ω PH Φ • + P Φ J Φ P a et CD a φ vP P rt Ω 3.

Φ Φ P P O tr N P P tr CΛ 3 1 tr CD et P φ P. φ P Ω P yQ Ω tr 1

PP CΛ ω PP Φ OPOP Ω a cn P- Φ PJ rt φ tr O Φ ⁾ Mört P Φ CΛ cn PP> P Ω A- rt JO et Φ Φ a et P a Φ - Φ P rt P tr rt et P

P P <3 Ω cn CΛ tr J rt et P SV P Φ cn o P CD P P a CΛ P Φ tr - Φ

PJ N rt o PJ tr 3 yQ rt rt t Φ P PJ et Φ Φ P Ω et NP "Φ P vP a Φ cn rt z CΛ P cn P • PP Φ Φ Φ rt P SV tr P Φ • X) P Ω P a PPP

P φ SV tr rt PJ PO _^ P CΛ o rt T. P "Φ PPOV PJ Φ φ 3 Φ 3

O P a ^> Φ Φ 2. tr P P Φ et a P rt o P P <Q P a Φ tr rt A- P tr Ό

P rt Φ P n PJ φ a cn tu SV ~ -j Φ o N Φ et rt a • <o Φ • φ CΛ Φ P ¹

Φ CΛ XP vp tu Ω P vp d rt 3 P ¹ a P ^ <tP Φ • cn rt <P SV Ω PJ

<CΛ P Φ ^ tr Ω PPPP --J Φ P CΛ φ PPP o CΛ Ω et tr ^ P o Ω P ¹ an co Hl -J tr JO et P CD ^y QPPSO 3 P- φ P P- ¹ P Φ P et

POP o rt ^ o Cπ φ tr a 3 P- ¹ -J - ^y a PPP -J Φ P cP PJ "Ö

P PJ p> a Φ 3 Φ Ω Φ Φ CD cn P Φ CΛ φ N rt Φ cn P SV O P et

P ¹ Hi tr tv> P h- ¹ O vP o

3 PPPZ CΛ P ¹ ON Ω CΛ P Φ tr Ω PXPPH o Hi Φ P K- Φ P CΛ (V ⁾ P φ Ω A- ^y P tr a O p P Φ Φ tr 3 P o

P ¹ PP Ω Ω rt P rt Ω ~ J ^ CD Φ cn tr a PJ p 3 φ o 3 PPN a P »P

00 CΛ cn 3 tr Φ φ a tr cπ P> P Φ Φ P 3 Ό P et PJ cn XI Pi P Φ --J PJ ω

P 1 PP Φ 1 n PPP> Q 1 a P ft Ω o PJ Φ P co rt ^• - - Φ v ©

Ω o - tv> Ai rt z P Φ N> PJ ö et φ Φ PJ P Φ P tr P ¹ P ¹ rt P ¹ P • P o

3 P -i 3 S 1 PPP n tr o P t PPP o P ^■ A- ^y PO lo

1 cn P 1 PJ P Φ rt CTi 1 1 P rt ot> P rt P Ω CΛ CΛ ^y Q PJ P ol P cn a P 1 1 tr Φ tr P in

a Φ rt

O co ivi tv) P ¹ P ¹ cn o cπ o Cπ o cπ rt tr • n * n Φ P Φ Φ PZ A-- tn rt P a et cP szao Hl tr N σ φ PJ -0 rt rt A- ^y > £ α

P Φ P PJ P + CΛ 1-1 1 φ Φ CΛ P CΛ Φ P Φ P P Φ P P Φ z Φ P P P 'P Φ O P PJ P

PP p PP ^J P 1 N t *. PP et PP ⁾ CΛ PP CΛ cn φ P φ P cn IV ⁾ O CΛ P ¹ CΛ cn et

P o H- ¹ φ aa φ J a CΛ SV P et a V ιP Hi CΛ P CΛ rt a P ^» P cπ Φ V Φ rt et äJ PO P> PP CΛ Φ PP Φ σ CΛ Φ et Ω Φ Φ rt Φ P CΛ P φ P

P p σ t tr yQ PJ P P 3 P P P P- 'a P tr -J Φ -1 P φ P <O Ω

CΛ ιP ≤ Φ T. P φ rt p ^> <! SV a P Hl CΛ 1— 'Φ J PJ P a .fe P, £> POP 3 σ J <&

Φ et Φ P + φ P 1 Φ σ -j Φ Hi rt rt P A- ^y tr Φ Φ CΛ oa PP 1 Φ 1— 'Φ

PP a 1 PZ s PP ⁾ <! 00 PO CΛ Φ rt PP CΛ PO tr Ω IV) P CΛ P s

PZ a Φ a rt <φ o ft PPP ¹ Φ CΛ PSP Φ CΛ O CΛ P Φ a P "Φ z

Φ P o Φ o P ω PJ • φ tr P Φ CΛ o *. CΛ CΛ et P et P P P> o 1 φ φ PH Φ

PP Hl et PP a 1 P A- P Φ OPO Λ PJ --J o P Ω Hi CΛ IV ⁾ \ PPMP av PP rt Φ Pl CΛ Φ PPP 1 P ~ JP ¹ P a Ω a Φ P ^J P ¹ ö PP Ό a

Φ Φ PJ φ Ω φ P P Ω P a Φ CΛ <£ H PJ 4 ^ P »P P> Φ PJ 1 PJ N P φ P

PPPP P> P • PJ tr ω < ^• QO Φ PP ¹ Ω CΛ 1 ω \ Ω z Ω P> φ P PJ P

^• »CΛ et rt P ¹ P rt σ PJ Ω o Φ PP PJ ^y Q PJ"_" Φ \ σ tr Φ 3 PPP yQ

P Φ Φ tr * n ω φ PP> tr tr N a P φ P 1 N ö φ P φ P 1 P CΛ in rt V tr CΛ P Φ JPPZ cn P et Φ PP Φ cn tr vP -J \ z PP PJ et CO 1 et P PJ φ o Φ rt P "l P ω Φ O PJ Φ P φ • QPPPPP ¹ σ φ J cn P a Φ Ω Φ Φ et P

PP o Ω Φ rt et PP rt Φ Hl rt CΛ cn φ φ P ¹ PPP et P Φ φ Φ CΛ PPP

PP P> SV "a O aa P P- ¹ Φ S a rt et P 1V> J et P Φ 1 CΛ CΛ P tr vP O φ

Φ a Φ et rt P P Φ Φ O Φ PJ Φ P O N P Φ 1 Ω O N P CΛ P P P

P Φ P Φ P a Φ P P P SV Ω -j P Φ P. -. Φ tr P Ω ö Φ P Φ Φ o Φ ω

P Φ O φ PJ • Φ Φ rt tr P ¹ CΛ CΛ P Φ 1 O φ P tr CΛ PP et P 3 za Φ CΛ A- a PP *

PP Φ φ g PP Φ A- ^y Φ CΛ PJ P a et Ω P tr Hi PO Ω ^y QP <PJ φ

P CΛ o SV O A- ^y T3 Φ Φ P Φ Hl PH Φ P- ¹ Φ rt -J Ω o CΛ P

Φ P SV P z φ o a a a <Φ CΛ tr PJ tr Hi Φ P et PJ 1 • P> φ P SV et

SV Hi et P 1 φ PJ P P Φ φ Φ o P Φ H * P P P rt cn et \ IV) 1 Φ Φ

Ω Φ PJ PP \ FPPPP CΛ ~ j P Ω Hl Φ et Φ CΛ P -JP σ σ tv) \ CTi PJP Ω O a PJ a Ω s Φ ~ o P ¹ tr Φ * P rt P - OP ¹ OPJ σ o Z Φ t P Φ a PP tr o P Φ CD CΛ A- ^y a Φ PP IV ⁾ Φ O P> P tv ⁾ PJ CΛ 3 P Φ P

Φ φ 1 Φ a PP CΛ P P> P iv ⁾ Φ P ^• Q o P t ⁾ ω A- ^y CΛ PP PJ SV P CD

Φ Ω Φ vP PJ 1 a A- ^y tr P et P ao -J CΛ tv ⁾ yQ yQ P φ et P φ a Ό Λ tr tr P 1 A- Hl P PJ CΛ CΛ φ P Φ P Φ P ¹ yQ φ PP 1 PP <Φ tr

Φ P P> Φ & PJ ω P Φ PP et P PH PJ PP pt ⁾ Φ P tr P PJ Ω CΛ Φ 1 PO

; v PPP "Ö o P- ¹ PJ ft PPN 3 PP 3 tr PP a tr Φ rt P Ω P et et Hi PN 1 CΛ CΛ T3 P tr ¹ φ a P ⁾ φ Ό CΛ φ CTl t. • ~> P a φ Φ tr Φ P φ P a O

P PJ Φ P ^ 1 1 ω φ P rt PPP 1 φ rt a PP Φ tr a P - ^y o Ω CΛ P> Hl tu ^ PP rt P cn • QJ CΛ. a σ - et a Φ cn φ CΛ PPPP a Φ 1 et PP o PJ cn rt Φ 3 et P et tn o Φ P> Φ -JP et O φ Φ Ω rt

Pl 1 Pl Φ PJ PJ Ω P et Hi P yQ • rt O in et P t ⁾ -JP A- ^y -j Pö t P tr tr

P Ω P A- ^y P tr P> OP ⁾ Ω Φ P ⁾ PT) P> P "A- ^y o Cπ -JP o PO tr J 1 CΛ <P tr> P yQ N rt Φ tö φ PJ tv ⁾ o A-> tr P ¹ Ω rt -J Φ PH ι

PJ PJ P Φ SP o 1 PP PJ Φ PPP o PPP N> tr Φ J tv ⁾ Φ PP ¹ P 3 P

PP CΛ PO CΛ A- "KV ^y Q CΛ tr tr os et P Φ PPP tv) 1 Φ tv ⁾ ^• n PJ

Ω PP CΛ et et o J SV Hl Φ Φ a PP 1 Φ aa PJ PP Hl • \ PP ¹ σ Ό tr Φ CΛ 1 o et ω P Φ PPPPPEPPP Hl a yQ ö CΛ o PJ tr rt a Pl p P 1 PP tr Φ N a Φ a ^y Q t- ^y PJ IN! PP and P ω PP

PJ 1 o PJ P PJ H et P -J CΛ P o S Φ Φ ⁾ N Ω z Φ PJ OPP rt CΛ

P Hl P PJ 3 PP cn CΛ P>&. Ω Φ P • X) P PJ o PO Ω z tr PPP Hi a cn J Ω a P Φ PPP cn P ⁾ O rt P P> 3 Φ a P tr P tr P Φ CΛ NPH, et tr

Φ PJ P P CΛ rt P P Z

P Λ ω o 3 ιP <i et Cd P P P Φ Ö a φ ω Ω Φ 1 S Φ <P o

CΛ Φ Φ INI P P P o O Φ H

P P P Φ P P P Ω a tr P Ω O

CΛ CΛ CΛ a CΛ φ et P tr Φ tr P a Φ XJ P Hl Hi φ a tr Φ Φ Φ P P P P P

PPP et P o CΛ P ¹ P φ yQ PP a tr vP -j A- ^> Hi rt Φ φ cn P l_l tr NNW v © a ω P Φ o PP et PP φ et P Φ -j P ⁾ P • CΛ P Φ P Φ N cn 3 φ v © o rt a CΛ P φ O PJ l_J CΛ PJ Ό PP tr Ω cn Ω az Φ P z PP o

1 O Φ P P P φ • ö tr φ P 'P Φ tr P σ Ω a P Φ φ et et φ X et yQ o

P 3 3 CΛ cn 1 P Φ V P Φ P φ 1 P P Φ J 3 P P P n

Φ P rt φ P 1 SV 1 1 Φ J 3 1 H ¹ ft ⁾ 1 Φ

P rt 1 • rt 1 CΛ 1 P

20th

The production of transistors in another technology, in particular of memory transistors of an EEPROM arrangement, can take place both before the formation of the source / drain regions and diffusion regions and after the formation of the source / drain regions and diffusion regions.

Instead of implantation, the threshold voltage of the MOS transistor can also be set by diffusion out of a doped layer, in particular a layer of appropriately doped glass, which is arranged on the surface of the trench.

Claims

21 claims

1. MOS transistor,

5 - in which a first source / drain region (171) and a second source / drain region (172) are provided in a semiconductor substrate (11),

- In which a trench (14) is arranged between the first source / drain region (171) and 10 the second source / drain region (172), the depth of which is greater than the depth of the first source / drain region (171) and the second source / drain region (172) and the surface of which is provided with a gate dielectric (15),

15

an isolation trench is provided which surrounds the MOS transistor,

- in which the isolation trench (13) is provided with an insulating ^'20 filling (131,132) and having a depth corresponding to the trench (14) is substantially the depth.

- In which a gate electrode (16) is arranged in the trench (14), the extent of which in the direction of the depth of the trench

25 (14) is at most equal to the depth of the trench (14).

2. MOS transistor according to claim 1,

a channel region is arranged between the first source / drain region (171) and the second source / drain region (172) and runs in the semiconductor substrate (11) along the surface of the trench (14),

- in which a first diffusion region (181) is provided, 35 which is of the same conductivity type as the first source

/ Drain region (171) is doped, but a lower dopant concentration than the first source / drain region 22

(171), which is arranged between the first source / drain region (171) and the channel region (12) and which adjoins the first source / drain region (171) and the channel region (12).

3. MOS transistor according to claim 2, in which the first diffusion region (281) is arranged at least partially below the first source / drain region (271).

4. MOS transistor according to claim 2 or 3, wherein the first diffusion region (181) is at least partially arranged between the surface of the trench (14) and the first source / drain region (171), so that the first Source / drain region (171) is not adjacent to the surface of the trench (14).

5. MOS transistor according to one of claims 2 to 4,

- In which a second diffusion region (182) is provided which is doped of the same conductivity type as the second source / drain region (172) but has a lower dopant concentration than the second source / drain region (172) is arranged between the second source / drain region (172) and the channel region (12) and adjoins the second source / drain region (172) and the channel region (12),

- In which the second diffusion area is constructed analogously to the first diffusion area (181).

6. MOS transistor according to one of claims 1 to 5,

- In which a first insulation structure (441) is provided which adjoins the surface of the gate electrode (46), the surface of the semiconductor substrate (41) and the first source / drain region (471), so that the first isolati- 23 structure (441) is arranged between the gate electrode (46) and the first source / drain region (471),

- in which the depth of the first insulation structure (441) is at least as large as the depth of the first source / drain

Area (471).

7. MOS transistor according to claim 6,

- In which the first insulation structure (441) also adjoins the surface of the second source / drain region (472), so that the first insulation structure (441) also between the second source / drain region (471) and the gate electrode (46) is arranged,

- in which the depth of the first insulation structure (441) is at least as great as the depth of the second source / drain region (472).

8. MOS transistor according to claim 1 to 7, wherein between the first source / drain region (171) and the second source / drain region (172) a channel region is arranged, which in the semiconductor substrate (11) along the Surface of the trench (14) runs.

9. Use of a MOS transistor according to one of claims 1 to 8 in an EEPROM arrangement.

10. Method for producing a MOS transistor,

- in which a trench (14) is formed in a surface of the semiconductor substrate (11),

- in which the surface of the trench (14) is provided with a gate dielectric (15), 24

- In which a gate electrode (16) is produced, the extent of which in the direction of the depth of the trench (14) is at most equal to the depth of the trench (14),

- In which a first source / drain region (171) and a second source / drain region (172) are produced such that the trench between the first source / drain region and the second source / drain Area is arranged and the depth of the first source / drain region (171) and the second source / drain region (172) is less than the depth of the trench (14),

- In the formation of the trench (14) an isolation trench (13) is produced which surrounds the MOS transistor,

- In which the isolation trench (13) is provided with an insulating filling (131, 132).

11. The method according to claim 10,

- In the first trenches (56) are etched in the surface of the semiconductor substrate, that with insulating material

(57) be filled in,

'- in which the trench (58) and the isolation trench (59) are each produced within one of the first trenches (56), the depth of the trench (58) and the isolation trench (59) being greater than the depth of the first trenches (56 ), so that a first insulation structure (5711) is formed which adjoins the trench (58) in the region of the surface of the substrate (51).