DD280851A1 - METHOD OF MAKING TRENCH MEMORY CELLS - Google Patents

Abstract

The invention relates to a method for the production of trench memory cells in CMOS technology for highly integrated memory circuits. The trench memory cell contains a preferably square stamp, which contains a storage capacitor at the lower parts of the walls and a selection transistor at the upper parts. Preferably, a memory cell is associated with a stamp. According to the invention, a first trench RIE is made using an oxide spacer on the surface of the stamp, which encloses a layer sequence. After introducing channel stoppers on the trench floors and a doping on the walls, a storage layer is implanted after removal of the oxide spacer, introducing a field oxide onto the trench bottom and insulated with storage oxide. After partially filling the trenches with a storage plate and insulating them with field oxide, the oxide spacers and an oxide layer on the upper parts of the wall are removed and a second trench RIE of the upper parts of the wall is made using a nitride layer previously enveloped by the oxide spacers. After setting the threshold voltage in the channel regions, gate oxide is formed and the selection transistor is completed. Fig. 7

Description

For this 3 pages drawings

Field of application of the invention

The invention is used to fabricate memory cells for least-integrated memory circuits. In this case, the matrix contains trenches intersecting a grid, between which stamps of about 3 pm in height can be found. Each stamp is assigned a memory cell with storage capacitor and selection transistor.

Characteristic of the known state of the art

Various trench memory cell fabrication methods are known.

In DE-OS 3525418 a method is described in which it is assumed that a p-rfotierten silicon substrate on which there is an η-doped layer. On top of this, there is a thin layer of oxide in this order, followed by a nitride layer and an oxide layer.

In a resist mask, islands with the layer sequence oxide, nitride and oxide are produced on the η-silicon and, after the paint removal, produced by means of PIE trenches of lesser depth. The width of the trenches is determined by the lateral dimensions of the resist mask or the islands.

After oxide deposition on the walls and RIE oxide removal from the trench bottoms, a second trench etching is performed in a second RIE using the oxide on the walls as an etch mask.

The trench is now filled with n-polysilicon, and by diffusion out of the ftestoxidos the substrate is umdofiert, so that a storage layer for the capacitor of the cell is formed.

Thereafter, the polysilicon is removed by RIE and removed by etching etch the η layer on the trench bottoms.

Subsequently, channel stopper, ground insulation, storage oxide and the storage plate are introduced up to the level of the residual oxide, which is covered at the surface with field oxide.

After introducing the channel stoppers and the insulation on the trench bottoms, the deposition of memory oxide on the walls of the stamp, the trench is partially filled with the η-doped memory polysilicon, which is padded at the surface with field oxide.

Nsch this process step oxide is eingeoracht and this removed in a resist mask using RIE from certain trenches.

After setting the threshold voltage and the formation of gate oxide in the exposed trench parts, the word line polysilicon is deposited and patterned and then completed in a known manner, the memory cell.

Disadvantages are the many trench etching steps in this process as well as the intermediate filling of the residual trenches with oxide.

In the EP-Anm. 198.sup.30 are introduced into a p-type substrate with a p-type epitaxial layer trenches, the walls of which are re-doped by diffusion after application of an .eta.-doped oxide layer.

After partial filling of the trenches and application of field oxide, the upper zone of the stamp is re-circulated by outdiffusion.

Subsequently, the introduced word line polysilicon is patterned and the memory cell completed in a known manner.

The disadvantage here is that the channel regions were only η doped and then unidoped, whereby the properties of the selection transistors deteriorate.

Object of the invention

The object of the invention is to provide a simple technology in the manufacture of trench cells without having to re-code the channel regions of the selection transistors.

Explanation of the essence of the invention

The object of the invention is to provide a method for the production of trench memory cells, which allows using a few RIE cycles for trench structuring setting the threshold voltage of the channel regions of the selection transistors without re-doping.

The method for producing trench memory cells is based on a semiconductor wafer having a p-type substrate on which a thermal oxide of approximately 10 nm is located. Under the oxide is an n-layer.

A nitride layer was deposited on the oxide.

This layer sequence is structured in a slip mask to paint islands. Thereafter, the layer sequence is patterned in a RIE to the η-layer, so that remain after Lackpaintung islands of Schichtfolgu.

Using the islands of the layer sequence as an etching mask for a further RIE, a system of intersecting trenches is created, between which square stamps stop, later the Spuicherkondensato: and don select transistor of the stamp associated memory cell.

Into the trench bottoms, channel stopper are introduced by a p-implant, and then oxidation is performed.

This produces on the walls of the stamp thinner and on the trench soils thicker field oxide as an insulating agent. Overetching removes the field oxide from the walls.

After forming a thin scattering oxide, an η-doped storage layer for the storage capacitor is formed on the walls by implantation, which is isolated after over-etching of the scattering oxide with a thin storage oxide.

Subsequently, the trenches are partially filled with a polysilicon storage plate for the Spoicherkondonsator on the surface > is generated by oxidation, a field oxide as an insulating agent.

After over-etching of the oxide present on the walls, leaving residual reld oxide on the storage plate, channel areas for the discharge transistors are produced on the walls of the stamps above the insulation means, which are covered with gate oxide after removal of technological layers.

After that, a conductive layer of η-doped polysilicon is deposited in the remaining trenches, wöbe! after planarization, the surface of the interconnect layer with the surface of the stamp substantially forms a plane.

In a further resist mask, the interconnect layer is now patterned into wordlines except for the iscentric agent at the top of the storage disk.

Thereafter, an insulating layer, which covers the remaining Leitbahnschicht and the top of the stamp, deposited, the remaining Giäben be filled with.

On this insulating layer after etching of contact holes, a second interconnect layer z. "V made of Silized abgescniodon and structured to bit lines.

According to the invention, a poly layer is deposited prior to the structuring of the layer sequence comprising the oxide and the nitride layer onto the nitride layer. After patterning the layer sequence down to the η layer, islands of oxide, the nitride layer and the n * -doped poly layer are obtained.

The poly layer of the islands is now oxidized to oxide spacers which completely cover the nitride layer both at the top and at the sides. Cover completely on the surface as well as on the sides. The oxide layer which likewise forms on the surface of the n-layer is, however, thinner due to lower doping, so that after overetching the oxide layer is removed, but the oxide savers continue to surround the nitrile layer after the over-etching. In the RIE trench etch the Late ^r serve almaße the remaining oxide spacer as Ätzmpske.

After partially filling the trenches with the storage plate, the oxide spacers are removed by oxide etching before the field oxide is deposited on the storage plate as an insulating means.

Thereafter, the oxide is removed from the walls of the stamp above the field oxide and then removed using the remaining nitride layer of the islands as an etching mask, the n-doticrio storage layer up to the level of the insulating agent on the disk through a RIE.

After removing the upper memory layer, the p-type substate is exposed at the upper parts of the walls between the η-layer and the n-type memory layer to form the channel regions of the select transistors. Without changing the conductivity type, the threshold voltage of the channel regions is now set.

It is advantageous to set the threshold voltage of the channel regions without re-doping of the n-type memory layer.

embodiment

The invention is explained in more detail in an embodiment and with reference to three drawings. Showing:

1: the starting material for the process for the production of trench storage cell

Fig. 2: the substrate with the islands of the layer sequence

FIG. 3: with the oxide spacers for the etching mask. FIG

Fig.4: with the trenches after the first RIE

Fig. 5: with the trench bottom insulation

Fig. 6: with the storage oxide and the storage disk

Fig. 7: after etching dai oxide spacer and insulation of the disk

Fig. 8: after the second RIE with the channel regions and the gate oxide

Fig. 9: with the structured word lines

Fig. 10: the complete trench memory cell.

In FIG. 1, a silicon wafer with a p-doped substrate 1 with a doping of 1... 5 × 10 ¹⁵ boron / cm ^{3 is} shown as the starting material. On the substrate 1 there is an n ⁺ -doped layer 2, a thermal oxide 3 of 10 nm, a nitride layer 4 of 100 nm and an η-doped poly layer 5 of 10 nm.

In a first resist mask a grid of square Lackinsaln 6 is generated with an edge length of 0.3μΓη at a mutual distance of 1.1 pm. By means of reactive ion etching (RIE), the layer 2 is exposed between the lacquer islands 6, so that square islands 7 of the layer system remain, as shown in FIG.

In the next step, the poly layer 5 remaining on the islands 7 is oxidized to an oxide spacer 8, the oxide spacer 8 comprising the nitride layer 4 and the oxide 3. The silicon of the layer 2 oxidized much slower, and an oxide layer 9 of about 40nm thickness with a thickness of the oxide spacer 8 of about 200nm is generated, as shown in Fi.3.

Subsequently, the oxide layer 9 is etched away, whereby the oxide spacer 8 is over-etched and still has a thickness of approximately 160 nm, with which it encloses the nitride layer 4 laterally and upwardly.

Between the oxide spacers 8, the silicon of the layer 2 is exposed. In a second RIE, a system of rectangular intersecting trenches 10 with a depth of 3μηι is etched using the Oxidspacer 8, wherein between the trenches 10 stamp 11 with oiner edge length of about 1.2pm at a width of the trenches 10 of about Remain 0.8pm, as shown in Figure 4 ii> t.

After forming a thermal scattering oxide of about 10 nm thickness, 12 p-channel stoppers 13 are formed by ion implantation on the trench bottoms, with the wound 14 of the punches 11 receiving a lower dose. In subsequent oxidation, on the trench bottom 12 thicker field oxide is accumulated as the insulation means 15 than on the walls 14, the insulation means 15 being deported from the walls 14 by a subsequent overetching

the overetching still remaining insulation means 15 stops, as shown in Fig. 5 is.

The implantation 6 takes place with an energy E = 60 keV in order not to re-circulate the n-doped layer 2 through the oxide spacers 8 and the nitride layer 4.

In the following Verfahrensschriit a thermal scattering oxide of about 10nm thickness is first formed and then there is an η-doping of the walls 14, whereby on the walls 14, a storage layer 16 is obtained. After one

Overetching is now on the walls 13, the silicon de. ' n storage layer 16 free, and it generates thermal storage oxide 17 of about 15nm thickness. Thereafter, η-doped polysilicon is deposited, planarized, and RIE etched until the polysilicon fills the trenches 10 as a memory plate 18 to Vj height, as shown in FIG.

In the following step, a Oxidiitzen is first performed, the oxide spacer 8 and the storage oxide 17 are removed in the upper third of the trenches 10. Thereafter, in an oxidation on top of the storage plate 18, thicker and thinner field oxide 14 is produced as an insulating means 19, and after overfilling, the insulating means 19 is removed from the walls 14 and remaining insulating material 19 remains on the storage plate 18, as in FIG Fig. 7 is shown.

With the use of the remaining nitride layer 4 and the remaining insulating means 19 as an etching mask, the wall 14d <3r punch 11 is now abgotragon in a thickness of about 160 nm up to the level of the insulation means 19.

On the now exposed p-type silicon of the substrate 1, lattice oxide is then produced with a thickness of 10 nm and then adjusted by a p-implantation, the threshold voltage of channel regions 20, which are arranged between the layer 2 and the storage layer 16.

As a result of overetching the scattering oxide, the surface of the channel regions 20 is coated with thermal green oxide 21, as shown in FIG. In the following method step, a further interconnect layer 22 is deposited and planarized until the trenches 10 are filled up to the level of the oxide 3 so as to avoid later capacitive couplings.

This Lbitbahnschicht 22 is now d6rar ». structured, that in each case a strip of the interconnect layer 22 from the middle of the stamp 11 to the middle trench 10 stops as a word line in each case a gap from the middle trench 10 to center punch 11, as shown in Fig. 9. The interconnect layer 22 consists of n ⁺ -doped polysilicon for the word lines.

This interconnect layer 22 is now structured so that in each case a strip of the interconnect layer 22 from the center of the stamp 11 to the middle trench 10 remains as a word line in each case a gap from the middle trench 10 to the center punch 11, as shown in Fig. 9. The interconnect layer 22 consists of n * -doped Polysü'zium for the word lines.

After oxidation of the exposed surfaces of the conductive layer 22, the remaining portions of the trenches 10 and the entire surface of the punches 11 are covered with an insulating layer 23 and planarized so that the insulating layer 23 covers the entire area of both the trenches 10 and the punch 11.

After etching of contact holes 24 through the insulating layer 23 and through the nitride layer 4 to the n-Schichl 2 at the top of the punch 11 eino further interconnect layer 25 is deposited from a silicide and patterned into bit lines, as shown in Fig. 10.

Cleaning steps and other obvious pi steps are not listed here.

Claims (3)

1. Verfaliren for the production of trench memory cells, in which on a p-substrate on the surface of an η-layer is generated and a Sohichtfolge of a thermal oxide and a nitride layer is deposited, wherein the layer sequence is structured to the η-layer, wherein thereafter using islands of the layer sequence as an etching mask by means of a RIE a Syrtem of intersecting trenches is generated, woiterhin the trench soils are subsequently isolated, further on the walls of the stamp, which are arranged between the trenches, an n-type memory layer is formed , which is then isolated with storage oxide, the trenches are then partially filled with a storage plate on the surface of an insulating agent is generated, further on the walls of the stamp above the Isoiationsmittels channel areas are generated, which are then covered with Gatooxid, wherein a Leitbahnschicht in the remaining Grä is deposited, which is structured to the insulating means on the surface of the disk, wherein an insulating layer covering the remaining poly layer and the top of the stamp is deposited, and wherein after etching of Kontaktlöchorn a further interconnect layer is deposited and patterned, characterized in that a poly layer (5) is deposited prior to structuring the layer sequence of the oxide (3) and the nitride layer (4) such that after structuring the islands (7) the remaining poly layer (5) oxidizes to oxide spacers (8) and the surface is over-etched, that after the partial filling of the trenches (10) with the storage plate (18) the oxide spacers (8) are removed, that after the application of the insulating means (19) on the storage plate (18) the oxide from the upper parts the walls (14) is removed and then using the remaining nitride layer (4) as an etching mask, the storage layer (16) up to the height d and that the threshold voltage of channel regions (20) disposed between the n-type layer (2) and the remaining memory layer (16) is adjusted without changing the conductivity type. 2. The method according to claim 1, characterized in that the threshold voltage is adjusted by an outdiffusion from a doped layer, which is subsequently removed. 3. The method according to claim 1, characterized in that a scattering oxide is applied, then the threshold voltage is adjusted by implantation and the litter oxide is removed.