WO1999028973A1 - Power/ground metallization routing in a semiconductor device - Google Patents
Power/ground metallization routing in a semiconductor device Download PDFInfo
- Publication number
- WO1999028973A1 WO1999028973A1 PCT/US1998/025638 US9825638W WO9928973A1 WO 1999028973 A1 WO1999028973 A1 WO 1999028973A1 US 9825638 W US9825638 W US 9825638W WO 9928973 A1 WO9928973 A1 WO 9928973A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- metal layer
- rows
- distributions
- ground
- conductivity device
- Prior art date
Links
- 238000001465 metallisation Methods 0.000 title abstract description 17
- 239000004065 semiconductor Substances 0.000 title abstract description 5
- 238000009826 distribution Methods 0.000 claims abstract description 86
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims description 107
- 229910052751 metal Inorganic materials 0.000 claims description 107
- 230000000153 supplemental effect Effects 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 32
- 239000010410 layer Substances 0.000 description 27
- 230000010354 integration Effects 0.000 description 8
- 239000012212 insulator Substances 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 5
- 230000001965 increasing effect Effects 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 230000002708 enhancing effect Effects 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 241000270295 Serpentes Species 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
Definitions
- the present invention relates to semiconductor integrated circuits, and more particularly, to power and ground metallization routing in a multi-metal layer semiconductor device having a plurality of basic cell circuits such as standard cells and gate array cells.
- Figure 1 illustrates a conventional integrated circuit having a number of rows 3 of cells 5.
- the cells can have various widths Wl, W2, W3, etc. and can be separated by small gaps (not shown).
- Power and ground are supplied to each cell from power and ground busses 7 and 9 via primary power and ground distributions 60 and 50, respectively.
- the primary power and ground distributions are typically laid out in the first metallization layer (i.e., "metal 1").
- metals in adjacent layers are laid out perpendicular to each other. That is, for example in a four-metal layer integrated circuit, wirings in the first and third metallization layers are laid out in one direction, and wirings on the substrate surface (e.g. polygate) and the second and fourth metallization layers are laid out in a direction perpendicular to the wirings in the first and third metallization layers.
- Figure 2 illustrates the layout of a basic cell 5 that can be included in such a conventional integrated circuit as is illustrated in Figure 1. It includes a PFET device region 10, a NFET device region 20, polygate 30, P-N device intraconnection 40, primary ground distribution 50, and primary power distribution 60. Contacts 70 connect power from primary power distribution 60 to the PFET device region, and contacts 80 connect ground from primary ground distribution 50 to the NFET device region. Input pins 85 are provided to connect devices in this cell with devices in other cells by contact to polygate 30 through contact 95. As can be seen, the primary power and ground distributions are laid out in metal 1 in an east-west direction. P-N intraconnection 40 and input pins 85 are also typically laid out in the first metallization layer.
- Figure 3 is a side plan view of the basic cell in Figure 2 taken along sectional line 3-3. It shows primary power distribution 60 formed as the first metal layer over PFET device region 10, with polygate 30 (i.e., a gate formed of a layer of doped polysilicon on the substrate) and first insulator layer 90 interposed therebetween.
- Device region 10 is formed in substrate 1 and is separated from other device regions by oxide 35.
- Gate oxide layer 25 is interpcsed between polygate 30 and device region 10.
- Input pin 85 is connected to polygate 30 by contact 95 through first insulator layer 90.
- Figure 4 illustrates the technique of laying out supplemental line 110 in an east-west direction in metal 3 in parallel with primary power distribution 60 in metal 1.
- the primary and supplemental lines are connected through second insulator 100 and third insulator layer 105 by periodically provided stacked via and contacts 120.
- This solution effectively increases the width of the primary power distribution line.
- this effective increase in width may not be sufficient in extreme circumstances where many cells in the same row require current at the same time.
- cells may have different dimensions, causing the primary distribution line to snake north and south and making it difficult to align the primary and supplemental lines.
- Figure 5 illustrates the technique of providing supplemental lines in metal 2.
- supplemental power lines 115 are laid out in metal 2 in a north-south direction forming a matrix with the underlying primary power distributions.
- Inter-layer contacts are periodically provided to connect the supplemental power lines 115 and primary power distribution lines 60.
- This technique permits the current in each of the primary power distributions 60 to be shared in parallel so that a "hot" row of devices can draw current from other primary power distributions 60 associated with other rows. It should be apparent from the foregoing that the same technique could be applied for ground as well as power.
- FIG. 6 is a side view of the cell in Figure 6 taken along sectional line 7- 7.
- An object of the present invention is to provide effective primary power and ground distributions in an integrated circuit having a plurality of cells. Another object of the invention is to provide sufficient current handling ability of power and ground distributions in an integrated circuit having a plurality of cells.
- Another object of the invention is to improve device interconnection routability in an integrated circuit having a plurality of cells.
- Another object of the invention is to improve cell integration. Another object of the invention is to improve the ability to provide supplemental lines to primary power and ground distributions.
- Another object of the invention is to improve P/N device balancing.
- Another object of the invention is to reduce average wire lengths.
- the invention includes primary power and ground distributions in the second metallization layer, rather than the first metallization as is conventionally done. This improves routability in the first metallization layer while providing sufficient current handling ability in the power and ground distributions.
- Figure 1 illustrates the layout of a conventional integrated circuit having rows of cells
- Figure 2 illustrates the layout of a basic cell in a conventional integrated circuit such as that illustrated in Figure 1 ;
- Figure 3 is a side view of the conventional cell in Figure 1 taken along sectional line 2-2;
- Figure 4 illustrates the conventional technique of providing supplemental power and ground distributions in metal 3 in the conventional integrated circuit
- Figure 5 illustrates the conventional technique of providing supplemental power and ground distributions in metal 2 in the conventional integrated circuit
- Figure 6 further illustrates the conventional technique of providing supplemental power and ground distributions in metal 2 in the conventional integrated circuit
- Figure 7 is a side view of the conventional cell in Figure 6 taken along sectional line 7-7;
- Figure 8 illustrates the layout of a basic cell with power and ground distribution routing in accordance with the present invention
- Figure 9 is a side view of the basic cell illustrated in Figure 8 taken along sectional line 9-9;
- Figure 10 illustrates providing supplemental lines in metal 3 and metal 4 in accordance with the principles of the present invention
- FIG. 11 illustrates inter-cell connections in metal 1 in accordance with the principles of the present invention
- Figure 12 illustrates providing substrate and well ties in an integrated circuit in accordance with the invention.
- Figure 13 illustrates a multi-height basic cell in accordance with the principles of the present invention.
- Figure 14 further illustrates providing multi-height basic cells in an integrated circuit in accordance with the invention.
- Figure 8 illustrates the layout of a basic cell layout using power and ground distribution routing in accordance with the present invention. It includes PFET device region 10, NFET device region 20, polygate 30, P-N device intraconnection 240, primary ground distribution 250, primary power distribution 260, cell output interconnection 242 and cell input interconnection 244. Stacked via and contact hole 270 connects power from primary power distribution 260 to the PFET device region, as will be described in more detail below.
- the primary power and ground distributions are formed as the second metallization layer in the basic cell, and are routed in an east-west direction.
- P-N device intraconnection 240, cell output interconnection 242, and cell input interconnection 244 are formed in the first metallization layer, and can be routed in both north- south and east-west directions.
- Other elements can be the same as in the conventional cell and their repeated detailed explanation here is not necessary for an understanding of the invention.
- the routability of inter-cell connections in metal 1 is enhanced due to the lack of primary power and ground distributions in metal 1.
- P-N device intraconnection 240 can be connected to cell output interconnection 242 so as to provide the output of this cell to a cell in a northern row in metal 1, while input pin can be connected to cell input interconnection 244 so as to supply the input of this cell from a cell in a southern row.
- Other examples and alternatives of connecting the inputs and outputs of cells in metal should be immediately apparent to those skilled in the art.
- FIG. 9 is a side plan view of the basic cell in Figure 8 taken along sectional line 8-8. It shows primary power distribution 260 formed as the second metallization layer over PFET device region 10, with first insulator layer 90 and second insulator layer 100 interposed therebetween. It also further graphically illustrates how cell output interconnection 242 can be freely routed in metal 1 to connect devices in the basic cell in Figure 8 via contact 210 with other cells north and south of the cell.
- the primary power and ground distributions can be connected to the respective device regions using many known techniques. However, in a preferred embodiment of the invention illustrated in Figure 8, primary power distribution 260 is connected to the PFET device region through stacked via and contact 270. By using a stacked via and contact such as that illustrated, the use of metal 1 is minimized, thus further improving the routability of other interconnections in metal 1.
- the power and ground distributions in metal 2 can be made as wide as necessary to handle the current required to supply the integrated circuit devices.
- metal 2 layers are trending toward being thicker than metal 1, further enhancing the current capacity of the power and ground distributions in metal 2.
- supplemental lines 215 can be provided in metal 3 in a matrix fashion with the primary distributions in metal 2, with periodic connections therebetween.
- second supplemental lines 217 in metal 4 can be further provided in a matrix fashion with the supplemental lines in metal 3, with periodic connections therebetween. It should be apparent that the pin blocking problem described with reference to Figure 6 is alleviated in the present invention by the ability to access pins in metals 1 and 2.
- FIG 11 illustrates how cells 5-A and 5-B in neighboring rows can be interconnected with each other and with other cells in metal 1 in accordance with the principles of the invention.
- This example shows the output of cell 5-A connected with the input of cell 5-B by cell interconnection 342, while other inputs of both cells are connected with cells in the same and other rows by cell interconnections 344, 346 and 348.
- Figure 12 illustrates providing substrate and well ties in a manner preferred by the present invention.
- substrate ties 303 and well ties 304 are provided at the corners of every cell, with adjacent cells in the same row sharing the same substrate and well ties, so as to connect ground and power respectively to substrate and N-wells in each cell.
- Figure 13 shows an example of a double-height cell 305 linked together by device intraconnection 440 in metal 1. Double-height cell 305 can be considered a stronger version of the basic cell illustrated in Figure 8, with more input and output pin locations, thus further enhancing the routability of interconnections in metal 1.
- Figure 14 further illustrates how a multi-height cell such as double-height cell 305 can be provided in an integrated circuit having a plurality of single-height cells 5. This advantage of the invention is particularly important for integrated circuit designs where complicated cell structures having many input and output pins are required.
- Figures 13 and 14 also illustrate another example of how substrate and well ties 303 and 304 are provided in accordance with the invention.
- routing techniques of the present invention have been described hereinabove with particular reference to integrated circuits having standard cells, the principles of the invention can also be applied to gate arrays having predetermined basic gate array cells.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-1999-7006862A KR100375753B1 (en) | 1997-12-02 | 1998-12-02 | Power/ground metallization routing in a semiconductor device |
JP53140499A JP2001506429A (en) | 1997-12-02 | 1998-12-02 | Power supply / ground metal wiring for semiconductor devices |
CA002279182A CA2279182A1 (en) | 1997-12-02 | 1998-12-02 | Power/ground metallization routing in a semiconductor device |
EP98960680A EP0963609A1 (en) | 1997-12-02 | 1998-12-02 | Power/ground metallization routing in a semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/984,029 US5981987A (en) | 1997-12-02 | 1997-12-02 | Power ground metallization routing in a semiconductor device |
US08/984,029 | 1997-12-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1999028973A1 true WO1999028973A1 (en) | 1999-06-10 |
Family
ID=25530251
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1998/025638 WO1999028973A1 (en) | 1997-12-02 | 1998-12-02 | Power/ground metallization routing in a semiconductor device |
Country Status (6)
Country | Link |
---|---|
US (3) | US5981987A (en) |
EP (1) | EP0963609A1 (en) |
JP (1) | JP2001506429A (en) |
KR (1) | KR100375753B1 (en) |
CA (1) | CA2279182A1 (en) |
WO (1) | WO1999028973A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002099884A2 (en) * | 2001-06-01 | 2002-12-12 | Virtual Silicon Technology, Inc. | Integrated circuit design with library cells |
US7076756B2 (en) | 2002-11-05 | 2006-07-11 | Ricoh Company, Ltd. | Layout design method of semiconductor integrated circuit, and semiconductor integrated circuit, with high integration level of multiple level metalization |
CN101499470B (en) * | 2008-02-01 | 2011-01-26 | 瑞昱半导体股份有限公司 | Power layout of integrated circuit and its design method |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5981987A (en) * | 1997-12-02 | 1999-11-09 | Nurlogic Design, Inc. | Power ground metallization routing in a semiconductor device |
JP3349989B2 (en) * | 1999-06-18 | 2002-11-25 | エヌイーシーマイクロシステム株式会社 | Semiconductor integrated circuit device and layout method and device therefor |
US6838713B1 (en) | 1999-07-12 | 2005-01-04 | Virage Logic Corporation | Dual-height cell with variable width power rail architecture |
US6483131B1 (en) * | 2000-01-11 | 2002-11-19 | Texas Instruments Incorporated | High density and high speed cell array architecture |
JP4521088B2 (en) * | 2000-03-27 | 2010-08-11 | 株式会社東芝 | Semiconductor device |
US6617621B1 (en) | 2000-06-06 | 2003-09-09 | Virage Logic Corporation | Gate array architecture using elevated metal levels for customization |
DE10104233B4 (en) * | 2001-01-31 | 2006-08-03 | Technische Universität München Lehrstuhl für integrierte Schaltungen | Method for assigning lines to wiring levels for semiconductor integrated circuit devices |
JP5028714B2 (en) * | 2001-03-30 | 2012-09-19 | 富士通セミコンダクター株式会社 | Semiconductor integrated circuit device and wiring method |
JP4156864B2 (en) * | 2002-05-17 | 2008-09-24 | Necエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
JP4036688B2 (en) * | 2002-06-18 | 2008-01-23 | 松下電器産業株式会社 | Standard cell library for automatic placement and routing and semiconductor integrated device |
JP2004221231A (en) * | 2003-01-14 | 2004-08-05 | Nec Electronics Corp | Apparatus and method for generating layout pattern and method for manufacturing semiconductor device using the same |
US7219324B1 (en) * | 2003-06-02 | 2007-05-15 | Virage Logic Corporation | Various methods and apparatuses to route multiple power rails to a cell |
US7069522B1 (en) | 2003-06-02 | 2006-06-27 | Virage Logic Corporation | Various methods and apparatuses to preserve a logic state for a volatile latch circuit |
US7149142B1 (en) | 2004-05-28 | 2006-12-12 | Virage Logic Corporation | Methods and apparatuses for memory array leakage reduction using internal voltage biasing circuitry |
CA2626467A1 (en) * | 2004-10-18 | 2006-04-27 | Foodcap International Limited | Apparatus and methods for processing and distribution of perishable food products |
US7616036B1 (en) | 2005-09-12 | 2009-11-10 | Virage Logic Corporation | Programmable strobe and clock generator |
JP2008078508A (en) * | 2006-09-22 | 2008-04-03 | Toshiba Corp | Semiconductor integrated circuit and manufacturing method of the semiconductor integrated circuit |
US7989849B2 (en) * | 2006-11-15 | 2011-08-02 | Synopsys, Inc. | Apparatuses and methods for efficient power rail structures for cell libraries |
KR101394145B1 (en) | 2008-02-26 | 2014-05-16 | 삼성전자주식회사 | standard cell library and integrated circuit |
JP5552775B2 (en) | 2009-08-28 | 2014-07-16 | ソニー株式会社 | Semiconductor integrated circuit |
JP5776802B2 (en) * | 2014-02-14 | 2015-09-09 | ソニー株式会社 | Semiconductor integrated circuit |
KR102161736B1 (en) | 2014-08-13 | 2020-10-05 | 삼성전자주식회사 | System on chip, electronic apparatus including system on chip and design method of system on chip |
JP6070731B2 (en) * | 2015-01-19 | 2017-02-01 | ソニー株式会社 | Semiconductor integrated circuit |
JP6146437B2 (en) * | 2015-04-27 | 2017-06-14 | ソニー株式会社 | Semiconductor integrated circuit |
KR102372001B1 (en) * | 2015-06-24 | 2022-03-08 | 르네사스 일렉트로닉스 가부시키가이샤 | semiconductor device |
US9825024B2 (en) | 2015-09-30 | 2017-11-21 | Samsung Electronics Co., Ltd. | Semiconductor device |
JP6524493B2 (en) * | 2017-05-11 | 2019-06-05 | ソニー株式会社 | Semiconductor integrated circuit |
DE102018124711B4 (en) | 2017-11-21 | 2024-01-11 | Taiwan Semiconductor Manufacturing Co. Ltd. | Layout procedures for standard cell structures |
US10733352B2 (en) * | 2017-11-21 | 2020-08-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit and layout method for standard cell structures |
WO2019132870A1 (en) * | 2017-12-27 | 2019-07-04 | Intel Corporation | Pin must-connects for improved performance |
US10878162B2 (en) * | 2018-10-31 | 2020-12-29 | Taiwan Semiconductor Manufacturing Company Ltd. | Metal with buried power for increased IC device density |
JP7004038B2 (en) * | 2020-07-28 | 2022-01-21 | ソニーグループ株式会社 | Semiconductor integrated circuit |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4870300A (en) * | 1986-08-06 | 1989-09-26 | Mitsubishi Denki Kabushiki Kaisha | Standard cell system large scale integrated circuit with heavy load lines passing through the cells |
US5565758A (en) * | 1994-11-21 | 1996-10-15 | Chip Express (Israel) Ltd. | Mapping of gate arrays |
US5656834A (en) * | 1994-09-19 | 1997-08-12 | Philips Electronics North America Corporation | IC standard cell designed with embedded capacitors |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61156751A (en) | 1984-12-28 | 1986-07-16 | Fujitsu Ltd | Semiconductor integrated circuit |
JPS62219539A (en) | 1986-03-20 | 1987-09-26 | Hitachi Ltd | Semiconductor integrated circuit device |
US4928160A (en) * | 1989-01-17 | 1990-05-22 | Ncr Corporation | Gate isolated base cell structure with off-grid gate polysilicon pattern |
US5191241A (en) | 1990-08-01 | 1993-03-02 | Actel Corporation | Programmable interconnect architecture |
US5132571A (en) | 1990-08-01 | 1992-07-21 | Actel Corporation | Programmable interconnect architecture having interconnects disposed above function modules |
JPH04216668A (en) * | 1990-12-15 | 1992-08-06 | Sharp Corp | Semiconductor integrated circuit |
JPH04306863A (en) | 1991-04-03 | 1992-10-29 | Hitachi Ltd | Semiconductor integrated circuit device |
US5576554A (en) | 1991-11-05 | 1996-11-19 | Monolithic System Technology, Inc. | Wafer-scale integrated circuit interconnect structure architecture |
JPH05136125A (en) | 1991-11-14 | 1993-06-01 | Hitachi Ltd | Clock wiring and semiconductor integrated circuit device having clock wiring |
JPH06252362A (en) * | 1993-03-02 | 1994-09-09 | Nec Yamaguchi Ltd | Semiconductor integrated circuit |
EP0624844A2 (en) | 1993-05-11 | 1994-11-17 | International Business Machines Corporation | Fully integrated cache architecture |
JP3057975B2 (en) | 1993-09-27 | 2000-07-04 | 日本電気株式会社 | Integrated circuit wiring |
JP2919257B2 (en) | 1993-12-15 | 1999-07-12 | 日本電気株式会社 | Multilayer wiring semiconductor device |
JPH07321295A (en) | 1994-05-27 | 1995-12-08 | Fujitsu Ltd | Method for arranging cell line and wiring channel for semiconductor integrated circuit |
US5635737A (en) * | 1994-09-23 | 1997-06-03 | Aspec Technology, Inc. | Symmetrical multi-layer metal logic array with extension portions for increased gate density and a testability area |
US5742099A (en) | 1994-09-29 | 1998-04-21 | Intel Corporation | Power bus for an integrated circuit including end-to-end arranged segments providing power and ground |
US5471093A (en) | 1994-10-28 | 1995-11-28 | Advanced Micro Devices, Inc. | Pseudo-low dielectric constant technology |
JP3309686B2 (en) | 1995-03-17 | 2002-07-29 | セイコーエプソン株式会社 | Resin-sealed semiconductor device and method of manufacturing the same |
JPH0964315A (en) | 1995-08-18 | 1997-03-07 | Nec Corp | Semiconductor integrated circuit device |
US5723883A (en) | 1995-11-14 | 1998-03-03 | In-Chip | Gate array cell architecture and routing scheme |
US6091090A (en) | 1997-09-19 | 2000-07-18 | In-Chip Systems, Inc. | Power and signal routing technique for gate array design |
US5981987A (en) * | 1997-12-02 | 1999-11-09 | Nurlogic Design, Inc. | Power ground metallization routing in a semiconductor device |
-
1997
- 1997-12-02 US US08/984,029 patent/US5981987A/en not_active Expired - Lifetime
-
1998
- 1998-12-02 WO PCT/US1998/025638 patent/WO1999028973A1/en not_active Application Discontinuation
- 1998-12-02 EP EP98960680A patent/EP0963609A1/en not_active Withdrawn
- 1998-12-02 JP JP53140499A patent/JP2001506429A/en active Pending
- 1998-12-02 KR KR10-1999-7006862A patent/KR100375753B1/en not_active IP Right Cessation
- 1998-12-02 CA CA002279182A patent/CA2279182A1/en not_active Abandoned
-
1999
- 1999-08-03 US US09/368,074 patent/US6307222B1/en not_active Expired - Lifetime
-
2001
- 2001-08-13 US US09/929,320 patent/US6570195B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4870300A (en) * | 1986-08-06 | 1989-09-26 | Mitsubishi Denki Kabushiki Kaisha | Standard cell system large scale integrated circuit with heavy load lines passing through the cells |
US5656834A (en) * | 1994-09-19 | 1997-08-12 | Philips Electronics North America Corporation | IC standard cell designed with embedded capacitors |
US5565758A (en) * | 1994-11-21 | 1996-10-15 | Chip Express (Israel) Ltd. | Mapping of gate arrays |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002099884A2 (en) * | 2001-06-01 | 2002-12-12 | Virtual Silicon Technology, Inc. | Integrated circuit design with library cells |
WO2002099884A3 (en) * | 2001-06-01 | 2003-08-07 | Virtual Silicon Technology Inc | Integrated circuit design with library cells |
US6766496B2 (en) | 2001-06-01 | 2004-07-20 | Virtual Silicon Technology, Inc. | Method and apparatus for integrated circuit design with a software tool |
US7051308B2 (en) | 2001-06-01 | 2006-05-23 | Virtual Silicon Technology, Inc. | Method and apparatus for integrated circuit design with library cells |
US7076756B2 (en) | 2002-11-05 | 2006-07-11 | Ricoh Company, Ltd. | Layout design method of semiconductor integrated circuit, and semiconductor integrated circuit, with high integration level of multiple level metalization |
US7426707B2 (en) | 2002-11-05 | 2008-09-16 | Ricoh Company, Ltd. | Layout design method for semiconductor integrated circuit, and semiconductor integrated circuit |
CN101499470B (en) * | 2008-02-01 | 2011-01-26 | 瑞昱半导体股份有限公司 | Power layout of integrated circuit and its design method |
Also Published As
Publication number | Publication date |
---|---|
US6307222B1 (en) | 2001-10-23 |
KR100375753B1 (en) | 2003-03-10 |
US6570195B2 (en) | 2003-05-27 |
CA2279182A1 (en) | 1999-06-10 |
US20010054720A1 (en) | 2001-12-27 |
JP2001506429A (en) | 2001-05-15 |
US5981987A (en) | 1999-11-09 |
EP0963609A1 (en) | 1999-12-15 |
KR20000070614A (en) | 2000-11-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5981987A (en) | Power ground metallization routing in a semiconductor device | |
US6635935B2 (en) | Semiconductor device cell having regularly sized and arranged features | |
EP0379330B1 (en) | Integrated circuit gate array | |
US6489689B2 (en) | Semiconductor device | |
US6525350B1 (en) | Semiconductor integrated circuit basic cell semiconductor integrated circuit using the same | |
US5420447A (en) | Double buffer base gate array cell | |
US6987293B2 (en) | Semiconductor integrated circuit device and standard cell placement design method | |
EP0683524B1 (en) | Base cell for BiCMOS and CMOS gate arrays | |
EP0867945A2 (en) | High density gate array cell architecture | |
US20020020857A1 (en) | Gate array layout for interconnect | |
US5671397A (en) | Sea-of-cells array of transistors | |
US7207025B2 (en) | Sea-of-cells array of transistors | |
US7986036B2 (en) | Power/ground network of integrated circuits and arrangement thereof | |
KR100306335B1 (en) | Semiconductor integrated circuit device | |
US6501138B1 (en) | Semiconductor memory device and method for manufacturing the same | |
US5691574A (en) | Semiconductor device capable of high speed operation and being integrated with high density | |
US6781869B2 (en) | Semiconductor memory | |
KR20040025817A (en) | A semiconductor device and a method of manufacturing the same | |
KR100827665B1 (en) | Semiconductor device and layout method of decoupling capacitor thereof | |
JP3981798B2 (en) | Semiconductor memory device and manufacturing method thereof | |
US20240282671A1 (en) | Front Side to Backside Interconnection for CFET Devices | |
EP0614224A1 (en) | Basic gate array cell with salicide power distribution | |
EP0151267B1 (en) | Vlsi integrated circuit having improved density | |
CN115565994A (en) | Semiconductor integrated circuit having a plurality of transistors |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): CA JP KR SG |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
ENP | Entry into the national phase |
Ref document number: 2279182 Country of ref document: CA Kind code of ref document: A Ref document number: 2279182 Country of ref document: CA |
|
ENP | Entry into the national phase |
Ref document number: 1999 531404 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1998960680 Country of ref document: EP Ref document number: 1019997006862 Country of ref document: KR |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWP | Wipo information: published in national office |
Ref document number: 1998960680 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1019997006862 Country of ref document: KR |
|
WWG | Wipo information: grant in national office |
Ref document number: 1019997006862 Country of ref document: KR |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1998960680 Country of ref document: EP |