WO1999025013A1 - Zones a charge metallique a basse temperature pour contacts ohmiques et trous d'interconnexion - Google Patents

Zones a charge metallique a basse temperature pour contacts ohmiques et trous d'interconnexion Download PDF

Info

Publication number
WO1999025013A1
WO1999025013A1 PCT/US1998/023910 US9823910W WO9925013A1 WO 1999025013 A1 WO1999025013 A1 WO 1999025013A1 US 9823910 W US9823910 W US 9823910W WO 9925013 A1 WO9925013 A1 WO 9925013A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
based metal
metal
seed layer
aluminum based
Prior art date
Application number
PCT/US1998/023910
Other languages
English (en)
Inventor
Walter E. Lundy
Eric C. Eichman
Original Assignee
Microchip Technology Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology Incorporated filed Critical Microchip Technology Incorporated
Priority to EP98956692A priority Critical patent/EP0951733A1/fr
Priority to JP52704599A priority patent/JP2001508244A/ja
Publication of WO1999025013A1 publication Critical patent/WO1999025013A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to methods for fabricating semiconductor structures and semiconductor structures resulting therefrom and. more particularly, to a method of forming low temperature metal fill regions for ohmic contacts and for via openings between spaced apart metal layers and semiconductor structures resulting therefrom.
  • metal evaporation techniques were used to deposit metal layers onto insulating layers as part of the process of making a semiconductor integrated circuit.
  • Other metal deposition techniques included either D.C. or A.C. metal sputtering operations.
  • a critical and important process consideration was to avoid semiconductor device and, subsequently, semiconductor integrated circuit failures resulting from a process inability to completely and reliably fill with metal the ohmic contact openings and/or via holes or openings between spaced apart metal layers.
  • the failure to completely and reliably fill with metal each ohmic contact opening and/or each via hole or opening between spaced apart metal layers would create a "void” or an electrical "open” in the desired electrical connection thereby causing both device and circuit failure.
  • an "open” or “void” in the metal fill for an ohmic contact opening or the via hole or opening became a very serious problem for semiconductor device or semiconductor integrated circuit manufacturers. Since the metal fill operation or process step occurs later in the semiconductor device or semiconductor integrated circuit manufacturing process after the formation of P and/or N regions in the semiconductor substrate, an undesired "void” or “open” created in the metal fill process step meant that all of the expense and time that was expended in the earlier steps of the semiconductor device or semiconductor integrated circuit manufacturing process was wasted. Correspondingly, since an "open” or “void” in the metal fill operation was not easily ascertained, then the costs and time associated with the remaining semiconductor process steps in completing the semiconductor device or semiconductor integrated circuit was also lost. As a result, it became extremely important in the process or method of forming semiconductor devices or semiconductor integrated circuits to develop a reliable metal fill process step.
  • It is a still another object of this invention to provide an improved method of forming, at low temperatures, reliable metal fill regions for ohmic contact openings and/or via holes which uses the deposition of an initial metal seed layer which partially fills the ohmic contact openings and/or via holes followed by the deposition of another metal covering layer which completely fills the ohmic contact openings and/or via holes as well as covers the edges of the portions of the insulating layers defining the ohmic contact openings and/or via holes and a resulting semiconductor structure fabricated therefrom.
  • a method is disclosed of filling with metal an ohmic contact opening located within an insulating layer formed on a semiconductor substrate which comprises the steps of: forming an ohmic contact to an exposed surface portion of the semiconductor substrate within an opening in the insulating layer; depositing a layer comprising a Titanium based metal on the metal ohmic contact, on side portions of the opening and on a top surface of the insulating layer; depositing a seed layer of an Aluminum based metal onto the layer of Titanium based metal partially filling the opening; and depositing an Aluminum based metal layer onto the seed layer of an Aluminum based metal to completely fill the opening with metal and to cover with metal top edge portions of the opening.
  • a method is disclosed of filling with metal an ohmic contact opening located within an insulating layer formed on a semiconductor substrate which comprises the steps of: forming an ohmic contact to an exposed surface portion of the semiconductor substrate within an opening in the insulating layer; depositing a reaction induced creep enhancing layer on the metal ohmic contact, on side portions of the opening and on a top surface of the insulating layer; depositing a seed layer of an Aluminum based metal onto the reaction induced creep enhancing layer partially filling the opening; and depositing an Aluminum based metal onto the seed layer to completely fill the opening with metal and to cover with metal top edge portions of the opening.
  • a method is disclosed of filling with metal a via hole located within at least one insulating layer and above an exposed metal land portion formed above a semiconductor substrate which comprises the steps of: depositing a layer of Titanium on the exposed metal land portion, on side portions of the at least one insulating layer defining the via hole and on a top surface of the at least one insulating layer; depositing an Aluminum based metal on the layer of Titanium partially filling the via hole; and depositing an Aluminum based metal layer on the seed layer of an Aluminum based metal to completely fill the via hole and to cover with metal top edge portions of the via hole.
  • a method is disclosed of filling with metal both an ohmic contact opening located within an insulating layer on a semiconductor substrate and a via hole located within at least one insulating layer and above an exposed metal land portion formed above the semiconductor substrate which comprises the steps of: forming an ohmic contact to an exposed surface portion of the semiconductor substrate within an opening in the insulating layer; depositing a layer comprising a Titanium based metal on the metal ohmic contact, and on side portions of the opening and on a top surface of the insulating layer; depositing a seed layer of an Aluminum based metal onto the layer of Titanium based metal partially filling the opening; depositing an Aluminum based metal layer onto the seed layer of an Aluminum based metal to completely fill the opening with metal and to cover with metal top edge portions of the opening; depositing a layer of Titanium on the exposed metal land portion, on side portions of the at least one insulating layer defining the via hole and on a top surface of the at least one insulating
  • Figure 1 is a side elevational sectional type view depicting a starting semiconductor substrate of one conductivity type having a region therein of opposite type conductivity and an insulating layer on one surface thereof with an opening therein exposing a surface portion of the region of opposite type conductivity.
  • Figure 2 is a side elevational sectional type view showing a layer of Titanium deposited on the insulating layer and in the opening therein of the structure of Figure 1.
  • Figure 3 is a side elevational sectional type view showing a layer of Titanium
  • Figure 4 is a side elevational sectional type view showing the formation of a Titanium Suicide ohmic contact to the region of opposite type conductivity created by a heat treatment of the structure of Figure 3.
  • Figure 5 is a side elevational sectional type view of the structure of Figure 4 after the deposition of a Titanium layer on the top surface thereof.
  • Figure 6 is a side elevational sectional type view of the structure of Figure 5 after the deposition of an Aluminum Silicon Copper seed layer on the top surface thereof partially filling the opening.
  • Figure 7 is a side elevational sectional type view of the structure of Figure 6 after the deposition of an Aluminum Silicon Copper layer on the top surface thereof completely filling the opening and also covering the top edge portions of the opening.
  • Figure 8 is a side elevational sectional type view of the structure of Figure 7 showing a portion of the metal (Aluminum Silicon Copper) formed as the first metal stripe for the structure of Figure 7 spaced from the region of opposite type conductivity (not shown) in the semiconductor substrate.
  • the metal Alignment Copper
  • Figure 9 is a side elevational sectional type view of the structure of Figure 8 after the deposition of a Silicon Dioxide layer thereon.
  • Figure 10 is a side elevational sectional type view of the structure of Figure 9 after the deposition of a Spin On Glass/low k Dielectric (SOG) on the top surface thereof to fill in and planarize the top surface of the structure.
  • SOG Spin On Glass/low k Dielectric
  • Figure 11 is a side elevational sectional type view of the structure of Figure 10 after the deposition of a Silicon Dioxide layer on the top surface thereof and after the formation of a via hole or opening through the Silicon Dioxide layers above the metal land portion to expose a surface portion thereof.
  • Figure 12 is a side elevational sectional type view of the structure of Figure 11 after the deposition of a layer of Titanium over the top surface of the structure and on the side walls and bottom portions of the via hole or opening.
  • Figure 13 is a side elevational sectional type view of the structure of Figure 12 after the deposition of an Aluminum Silicon Copper seed layer on the top surface of the structure partially filling the via hole or opening.
  • Figure 14 is a side elevational sectional type view of the structure of Figure 13 after the deposition of an Aluminum Silicon Copper layer on the top surface of the structure completely filling the via hole or opening and covering the top edge portions of the Silicon Dioxide layer defining the via hole or opening.
  • a silicon semiconductor substrate 10 is shown formed of, for example, a P-type conductivity (if desired, the substrate 10 can be of the opposite N- type conductivity and thus the conductivity of N region 12 shown in the substrate 10 would be opposite (or P-type) to the N conductivity region shown in Figures 1-7).
  • the substrate 10 of Figure 1 is a portion of a semiconductor chip containing various regions of selected N or P type conductivity (not shown).
  • the N type region 12 is formed using diffusion or ion implantation techniques preferably in an opening formed by photolithographic masking and etching operations in an insulating layer that exposes a surface portion of the semiconductor substrate 10.
  • an insulating layer 14 is formed on the top surface of the semiconductor substrate 10.
  • the insulating layer 14 comprises a bottom portion of Silicon Dioxide (not shown) which is in contact with the top surface of the semiconductor substrate 10 and the predominant portion of the insulating layer 14 comprises Boron Phosphorous Silicate Glass (BPSG)/low k Dielectric which can be created during the process of forming P type regions (not shown) in the semiconductor substrate 10 using a Boron (P type) impurity and N type regions in the semiconductor substrate such as the N type region 12 using a Phosphorous (N type) impurity.
  • the thickness of the semiconductor substrate 10, the depth of the N type region 12 and the thickness of the BPSG insulating layer 14 can be varied as desired.
  • the BPSG insulating layer 14 has a thickness of several thousand Angstroms.
  • An opening 16 is formed in the insulating layer 14 preferably by photolithographic masking and etching techniques using Photoresist (not shown) to etch away the portion of the insulating layer 14 to form the opening 16 and to expose a surface portion of the semiconductor substrate to create the N type region 12 by either diffusion or ion implantation.
  • a layer 18 of Titanium is deposited on the top surface of the semiconductor structure of Figure 1.
  • the layer 18 of Titanium preferably has a thickness of about 500 Angstroms and this layer 18 coats the side wall portions of the opening 16, the bottom portion of the opening 16 and the top surface portion of the insulating layer 14 as shown in Figure 2.
  • a Titanium Nitride layer 20 is deposited on the Titanium layer 18 and this Titanium Nitride layer coats the side wall portions of the opening 16, the bottom portion of the opening 16 and the top surface portion of the Titanium layer 18.
  • the semiconductor structure of Figure 3 is heat treated or annealed in a furnace preferably at a temperature of about 450-600 degrees C. for a sufficient period of time to form a Titanium Suicide (TiSi 2 ) relatively shallow ohmic contact 22 to the N type region 12.
  • TiSi 2 Titanium Suicide
  • the top two surface layers, namely, the Titanium Nitride (TiN) layer 20 and the underlying Titanium layer 18 together provide a barrier layer to permit the formation of the relatively shallow ohmic contact 22 to the N type region 12. This barrier layer prevents spike through of Aluminum from the Aluminum based metal layer subsequently deposited on the barrier layer as described below.
  • a second titanium layer 24 is deposited on a top surface of the semiconductor structure of Figure 4.
  • the two separate layers 20 and 18, (layer 18 merges with Doped Silicon Region) merge together to form, in effect, a single barrier layer 19 comprising both Titanium Nitride and Titanium and Titanium Silicide 22 as shown in Figure 5.
  • the deposited Titanium layer 34 preferably has a thickness of about 500 Angstroms and serves to cover the top surface of the barrier layer 19 and the side and bottom portions of the opening 16.
  • the layer 34 can be another refractory metal such as Tungsten Molybdenum, Platinum or Cobalt, however, Titanium is preferred for the disclosed embodiment.
  • the Titanium is a Reaction Induced Creep Enhancing layer which synergistically reacts with a subsequently deposited Aluminum Silicon Copper layer because of the presence of Silicon therein which is a Reaction Enhancing Metalization Impurity to permit the low temperature metal fill for the ohmic contact opening 16 and for the subsequently described metal fill for the via hole or opening.
  • This reaction between the Titanium and Silicon facilitates and enhances drawing the metal fill into the ohmic contact and via openings.
  • a metal seed layer 26 of an Aluminum based metal and preferably Aluminum Silicon Copper is deposited on the top surface of the semiconductor structure of Figure 5. As shown in Figure 6, the seed layer 26 partially fills the opening 16 and coats the side and bottom portions thereof as well as the top surface of the Titanium layer 24. Preferably, this metal seed layer 26 is deposited at a high deposition rate (i.e. a thickness of 1200 Angstroms is achieved at a deposition rate of 150 Angstroms per second. The temperature of the cold deposition ranges from ambient to about 250 degrees Centigrade. If desired, the metal seed layer 26 can have a thickness of from about 500-2000 Angstroms.
  • a metal covering layer 28 of Aluminum Silicon Copper is deposited on the top surface of the semiconductor structure of Figure 6.
  • This metal covering layer 28 is preferably deposited at a relatively low deposition rate (i.e. 20 Angstroms per second) and at a low temperature in the range of from about 240 decrees C to about 380 C.
  • the thickness of the Aluminum Silicon Copper metal covering layer 28 is selected to completely fill the opening 16 of the semiconductor structure of Figure 6 and to thereby cover the top edge portions of the opening 16 to prevent the possibility of an "open” or “short” from being created in the formation of the Aluminum Silicon Copper metal covering layer 28 that serves as the first level of metalization (Metal 1 ) layer.
  • the metal covering layer 28 of Aluminum Silicon Copper merges with underlying layer 30 which is a combination metal layer of a Titanium Silicide (TiSi x ) plus a Titanium Aluminum Silicide (TiAl x Si y ) because of the reaction of Titanium in prior layer 24 (see Figure 6) with the seed layer 26 ( Figure 6).
  • metal covering layer 28 which is the first level of metalization (Metal 1 ) of Aluminum Silicon Copper is shown as part of the metal land or metal stripe to carry electrical current to or carry electrical current away from the N region 12 (see Figure 7).
  • Metal 1 the first level of metalization of Aluminum Silicon Copper
  • the remaining portion of the Metal 1 layer 28 is provided or formed as shown in Figure 8.
  • the semiconductor structure depicted in Figure 8 is shown as spaced away from the N type region 12 to more simply show how the method of reliably and completely filling a via hole from a second level of metalization (not shown in Figure 8) is carried out to make electrical contact between the second level of metalization to the first level of metalization as shown by the metal land or metal stripe portion 28 in Figure 8.
  • a Silicon Dioxide layer 32 is deposited onto the top surface of the semiconductor structure of Figure 8. This Silicon Dioxide layer 32 covers the exposed top surface portion of the BPSG layer 14 and the metal land portion 28.
  • an insulating layer 34 which is preferably a Spin On Glass layer, is deposited on the top surface portions of the semiconductor structure of Figure 9 and then etched back to provide the substantially planar top surface configuration shown in Figure 10.
  • the Spin On Glass layer 34 which is a low k dielectric insulating layer serves, in effect, as a filler layer and support layer for subsequent depositions as described below.
  • the advantages of the Spin On Glass layer 34 is its ease of use and deposition, however, since it is made of a low k dielectric material, it cannot withstand high temperatures associated with prior art metal deposition techniques.
  • this Figure depicts the resulting semiconductor structure after the deposition of a relatively thick Silicon Dioxide layer 36 and the formation of a via hole or opening 38 therein by, for example, photolithographic masking and etching techniques using photoresist (not shown) as a mask.
  • This via hole or opening 38 is used to permit electrical connection between a second level of metalization (not shown in Figure 11) and the first level of metalization (Metal 1) which is the portion of the metal land 28.
  • a layer of Titanium 40 (preferably having a thickness of about 500 Angstroms) is deposited on the top surface of the semiconductor structure of Figure 11.
  • This layer 40 of Titanium covers the side and bottom portions of the via hole or opening 38 as well as the top surface of the Silicon Dioxide layer 36.
  • the Titanium layer 40 functions as a Reaction Induced Creep Enhancing layer as described below with reference to the Titanium layer 34 used in the metal fill operation for the ohmic contact opening 16.
  • a metal seed layer 42 of an Aluminum based letter such as Aluminum Silicon Copper is deposited on the top surface of the semiconductor structure of Figure 12.
  • This metal seed layer 42 has a thickness sufficient to partially fill the via hole or opening 38 and coats or covers the side and bottom portions of the via hole or opening 38 and also coats the top surface of the Titanium layer 40.
  • the metal seed layer 42 contains Silicon which is a Reaction Enhancing Metalization Impurity as described below with respect to the metal seed layer 26.
  • a metal covering layer 44 of Aluminum Silicon Copper, which serves to create the second level of metalization (Metal 2) is deposited on the metal seed layer 42 (see Figure 13).
  • the metal seed layer 42 of Figure 13 combines with the Titanium layer 40 (see Figure 13) to create a metal layer or region 41 that comprises Titanium Aluminum Silicide (TiAl x Si y ) and Titanium Silicide (TiSi x ) 41.
  • This metal layer 41 is part of the metal covering layer 44 which is the Metal 2 (second level metalization) layer.
  • Subsequent metal etching operations can be used to define metal lands or metal stripes for the Metal 2 layer 44.
  • the Metal 2 layer 44 functions to completely fill the via hole or opening 38 (see Figure 13) as well as to cover the top edge portion of the Silicon Dioxide insulating layer 36 forming the via hole or opening 38 to insure against any "voids” or "opens” that could result if there was no such coverage.
  • the method or process provides a simple and inexpensive process or method for achieving complete ohmic contact fill and/or via fill.
  • This low temperature metal fill process or method is thermally compatible with low k dielectrics that are unstable at elevated temperatures.
  • the deposition rates, temperatures and metal layer thicknesses in carrying out the via hole metal filling process is similar to those noted above for the metal filling process for the ohmic contact opening.

Abstract

L'invention concerne un procédé de dépôt métallique à relativement basse température permettant de remplir de manière sûre et complète des ouvertures et/ou des trous ou ouvertures d'interconnexion à contact ohmique avec un métal entre des couches de métallisation espacées dans une structure à semi-conducteur. Le procédé consiste à déposer une couche de titane ou d'un métal à base de titane dans l'ouverture et/ou dans le trou d'interconnexion à contact ohmique, à déposer successivement une couche de métal d'ensemencement d'un métal à base d'aluminium tel que le cuivre silico-aluminium pour remplir partiellement l'ouverture et/ou le trou d'interconnexion à contact ohmique et une couche de revêtement métallique d'un métal à base d'aluminium tel que le cuivre silico-aluminium pour remplir complètement l'ouverture à contact ohmique.
PCT/US1998/023910 1997-11-10 1998-11-10 Zones a charge metallique a basse temperature pour contacts ohmiques et trous d'interconnexion WO1999025013A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP98956692A EP0951733A1 (fr) 1997-11-10 1998-11-10 Zones a charge metallique a basse temperature pour contacts ohmiques et trous d'interconnexion
JP52704599A JP2001508244A (ja) 1997-11-10 1998-11-10 オーム接触およびバイア開口部のための低温金属充填領域

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US96704897A 1997-11-10 1997-11-10
US08/967,048 1997-11-10

Publications (1)

Publication Number Publication Date
WO1999025013A1 true WO1999025013A1 (fr) 1999-05-20

Family

ID=25512235

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/023910 WO1999025013A1 (fr) 1997-11-10 1998-11-10 Zones a charge metallique a basse temperature pour contacts ohmiques et trous d'interconnexion

Country Status (5)

Country Link
EP (1) EP0951733A1 (fr)
JP (1) JP2001508244A (fr)
KR (1) KR20000070047A (fr)
TW (1) TW405187B (fr)
WO (1) WO1999025013A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5036382A (en) * 1989-02-22 1991-07-30 Yamaha Corporation Semiconductor device having a multi-level wiring structure
EP0799903A2 (fr) * 1996-04-05 1997-10-08 Applied Materials, Inc. Méthodes de pulvérisation d'un métal sur un substrat et dispositif de traitement de semiconducteurs

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5036382A (en) * 1989-02-22 1991-07-30 Yamaha Corporation Semiconductor device having a multi-level wiring structure
EP0799903A2 (fr) * 1996-04-05 1997-10-08 Applied Materials, Inc. Méthodes de pulvérisation d'un métal sur un substrat et dispositif de traitement de semiconducteurs

Also Published As

Publication number Publication date
TW405187B (en) 2000-09-11
EP0951733A1 (fr) 1999-10-27
KR20000070047A (ko) 2000-11-25
JP2001508244A (ja) 2001-06-19

Similar Documents

Publication Publication Date Title
EP0279588B1 (fr) Contact dans une perforation dans un semi-conducteur et procédé pour sa fabrication
US4960732A (en) Contact plug and interconnect employing a barrier lining and a backfilled conductor material
US4948755A (en) Method of manufacturing self-aligned conformal metallization of semiconductor wafer by selective metal deposition
US5644166A (en) Sacrificial CVD germanium layer for formation of high aspect ratio submicron VLSI contacts
US4764484A (en) Method for fabricating self-aligned, conformal metallization of semiconductor wafer
EP0506426B1 (fr) Métallisation d'un circuit intégré satisfaisant les exigences d'un coffret à contact zéro et la méthode pour sa préparation
US8461692B2 (en) Semiconductor device structures including damascene trenches with conductive structures and related method
US5141897A (en) Method of making integrated circuit interconnection
US4833519A (en) Semiconductor device with a wiring layer having good step coverage for contact holes
JP3955644B2 (ja) 半導体接続構成体及び方法
EP0119497B1 (fr) Procédé pour fabriquer des électrodes et bandes d'interconnexion
US4562640A (en) Method of manufacturing stable, low resistance contacts in integrated semiconductor circuits
US5434451A (en) Tungsten liner process for simultaneous formation of integral contact studs and interconnect lines
JPH09199443A (ja) 集積回路におけるランディングパッド構成体の製造方法
US5504038A (en) Method for selective tungsten sidewall and bottom contact formation
US6229213B1 (en) Germanium alloy electrical interconnect structure
US6406998B1 (en) Formation of silicided contact by ion implantation
EP0448276A2 (fr) Prise de contact pour circuit intégré
KR100221656B1 (ko) 배선 형성 방법
EP0951733A1 (fr) Zones a charge metallique a basse temperature pour contacts ohmiques et trous d'interconnexion
US6597042B1 (en) Contact with germanium layer
KR100408182B1 (ko) 구리 배선용 장벽층 형성 방법
JPH10106973A (ja) 半導体装置およびその製造方法
KR0156122B1 (ko) 반도체장치의 제조방법
KR19990041753A (ko) 반도체 소자의 콘택배선 형성방법

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

ENP Entry into the national phase

Ref country code: JP

Ref document number: 1999 527045

Kind code of ref document: A

Format of ref document f/p: F

WWE Wipo information: entry into national phase

Ref document number: 1019997006267

Country of ref document: KR

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1998956692

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1998956692

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1019997006267

Country of ref document: KR

WWW Wipo information: withdrawn in national office

Ref document number: 1998956692

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 1019997006267

Country of ref document: KR