Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J3/00—Time-division multiplex systems
  • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
  • H04J3/1605—Fixed allocated frame structures
  • H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
  • H04J3/1617—Synchronous digital hierarchy [SDH] or SONET carrying packets or ATM cells
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J3/00—Time-division multiplex systems
  • H04J3/02—Details
  • H04J3/08—Intermediate station arrangements, e.g. for branching, for tapping-off
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04Q—SELECTING
  • H04Q11/00—Selecting arrangements for multiplex systems
  • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
  • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
  • H04Q11/0478—Provisions for broadband connections
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
  • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
  • H04J2203/0028—Local loop
  • H04J2203/003—Medium of transmission, e.g. fibre, cable, radio
  • H04J2203/0032—Fibre
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
  • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
  • H04J2203/0046—User Network Interface
  • H04J2203/0048—Network termination, e.g. NT1, NT2, PBX
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
  • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
  • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
  • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
  • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
  • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S370/00—Multiplex communications
  • Y10S370/916—Multiplexer/demultiplexer

Definitions

• signals with signals for broadband applications (e.g., video and data signals) in the
• the signal stream in a cell based format, can contain a mixture of cells having
• asynchronous application signals i.e., signals for asynchronous communication
• asynchronous application signals e.g., video
• a simple prior art method for extracting isochronous telephony signals reads all of the bytes in a received frame into a memory and subsequently
• FIGS 1 and 2 set forth one implementation of this prior art technique.
• the prior art includes a memory 105 which sequentially stores
• art implementation also includes a table of pointers 110 with a pointer for each
• the isochronous telephony bytes in the memory are routed to the
• 155 Mb/s SDH-like data stream having ATM and TDM cells could have 2,340 DS0
• the invention provides method and apparatus for identifying signals for a set
• Some embodiments of the invention are methods and
• These embodiments include an optical network unit that receives an optical network
• optical signal stream having signals for different types of applications.
• network unit includes a content addressable memory that stores locations in the
• Figure 1 presents a memory device and a table of pointers used in one prior art
• FIG. 2 presents four TIU cards used in conjunction with the memory device
• Figure 3 presents a fiber-to-the-curb network in which the invention can be
• Figure 4 presents one example of a SDH-like frame used in some
• Figure 5 presents one example of a telephony cell used in some embodiments
• Figure 6 presents a common control unit for use in the network of Figure 3.
• Figure 7 presents one embodiment of the invention.
• Figure 8 presents one example of a content addressable memory used in some embodiments
• Figure 9 presents one example of a memory interface unit used in some embodiments.
• Figure 10 illustrates one manner for forwarding extracted telephony data
• Figure 11 presents another embodiment of the invention.
• the invention provides method and apparatus for identifying signals for a set
• the communication device is a device that transmits and/or receives signals through the
• Examples of such communication devices include computers
• One or more communication devices form each set of communication devices.
• a set of communication devices can include similar communication devices (e.g., a
• a set of telephony communication devices can use similar telephony equipment).
• communication devices can be defined by a number of communication devices that
• a similar communication medium e.g., utilize twisted pairs or co-axial cables
• communication-medium terminating devices e.g., utilize similar line cards, adapter
• the FTTC network 300 connects one or more communication
• PSTN public switched telecommunications network
• ATM asynchronous transfer mode
• Each network subscriber site 305 can be residential or commercial subscriber sites.
• the FTTC network 300 transmits signal streams between the subscriber sites
• the PSTN 310 and the PSTN 310, the ATM network 315, or other networks (e.g., individual, private,
• the signal streams contain signals transmitted to,
• the FTTC network transmits signals to and from telephony
• non-telephony communication devices i.e., non-telephony application signals.
• the FTTC network 300 includes a host digital terminal (HDT) 320, element
• EMS management system
• optical network units (ONUs) 335 As shown in Figure 3, the HDT couples to the
• PSTN PSTN
• ATM network PSTN
• other networks PSTN, the ATM network, and/or other networks.
• the PSTN-HDT interface 340 follows the specification adopted by one of
• the physical interface to the PSTN can be twisted pairs
• the ATM network-HDT interface 345 can be realized using an optical
• the interface (such as OC-3, OC-12c, etc.).
• the interface (such as OC-3, OC-12c, etc.).
• HDT 320 has two optical broadcast ports, which can only receive signals carrying
• ATM cells and one optical interactive port which can receive and transmit signals.
• the HDT receives downstream signals from the PSTN, the ATM network, or
• the HDT serves a multiplexor which
• the PSTN, ATM, or other networks to the transmission media, and (2) transmits the
• the HDT serves as a
• demultiplexer which (1) parses the received upstream signals (i.e., the signals received
• the HDT also re-formats the downstream and upstream signals, before
• the HDT performs
• HDT does not perform all of these formatting operations, or performs additional
• the HDT combines (i.e., maps) the
• isochronous application signals such as telephony signals.
• the HDT transmits these
• the HDT also aims to assign frames to the ONUs at a prespecified rate (e.g., once every 125 ⁇ s).
• the HDT also aims to assign frames to the ONUs at a prespecified rate (e.g., once every 125 ⁇ s).
• Figure 4 presents one example of frames transmitted across the fiber optic
• Each frame shown in this figure is a SDH-like frame which includes
• the payload envelope includes 41 cells of
• Each cell has 57 bytes.
• Figure 5 presents one example of an isochronous, telephony cell. As shown in
• each cell includes three reserved bytes (R), and six groups of DSO bytes.
• Figure 5 presents each group as eight DSO data bytes following one signaling byte (S).
• the signaling byte contains the status and control signals (e.g., on/off hook, ring, etc.)
• each group can include nine clear DSOs bytes
• the HDT also adjusts the signal rate of the data it receives. For instance, for
• the HDT 320 converts the signals it receives from
• the PSTN 310 at a DSl-rate to signals at a DSO-rate; it then transmits these signals to
• the HDT performs the following steps:
• the HDT also converts the electrical
• the HDT couples to the EMS 325.
• the EMS is used to
• provision services and equipment on the FTTC network e.g., allocate twisted pairs off
• the TIUs in the central office where the HDT 320 is located, in the field, or in the
• the EMS is software based and can run on a personal computer in which
• HDTs and access networks are HDTs and access networks.
• the fiber optic cables 330 communicatively couple the HDT to a number of
• ONUs 335 located in a number of serviced areas.
• the invention use sixty four optical fiber cables to connect the HDT to sixty four
• each ONU includes a common control unit (CCU) 350,
• the CCU controls the operation of the ONU. In particular, the CCU performs
• the CCU (1) parses the received downstream signals (i.e., the signal
• the CCU also combines the signal streams that it
• optic cable 330 Different embodiments of the invention can be employed in the CCU,
• FIG. 6 presents one example of the CCU 350. As shown in this figure, the
• CCU includes a bi-directional (BIDI) optical converter 605, a framer 610, a TIU
• TIUI TIUI
• BIOS BIU interface
• microprocessor microprocessor
• the optical converter 605 converts optical signals, that it receives via
• the optical converter receives bit-wide, electrical signals
• the framer also scans the incoming signal stream in order to determine the
• the framer communicatively couples to the TIUI 615, in order to transmit and
• the TIUI in order to allow the TIUI to parse the telephony application signals from
• the framer also transmits signals to and receives signals from the BIUI.
• BIUI performs administrative functions (e.g., parity check and overhead addition
• the BIUI forwards the signals it receives from the downstream side.
• the BIU forwards the extracted signals to a network
• the BIUI 620 acts as an arbitrator for the
• the BIUI allocates different portions of each frame's payload to
• the microprocessor 625 of the CCU 350 is used to program various aspects of the microprocessor 625 of the CCU 350.
• the microprocessor controls the components of the CCU. For instance, as further described below, the microprocessor
• the TIUI is used to program various components of the TIUI. Through this programming, the TIUI can store the location of telephony bytes in the received or transmitted signal
• each ONU 335 includes four TIUs 355 coupled to the
• Each TIU 355 connects to six twisted
• the FTTC network 300 may be any suitable network.
• the FTTC network 300 may be any suitable network.
• ONUs that have different number of TIUs and/or different number of twisted
• a TIU When a TIU receives a signal stream from the CCU, it converts the signal
• a narrowband service such as plain old telephony
• POTS signals
• the TIU can generate analog POTS
• a network interface device (NID) 370 serves as an
• the NID provides high-voltage protection.
• each TIU 355 is transmitted to the NID 370 and twisted pairs 365 and 375.
• Each ONU 335 also includes eight BIUs 360 coupled to the CCU 350 through
• Each BIU 360 connects to two co-axial cables.
• each BIU communicatively couples to the BIUI 620 of the CCU 350.
• the BIU receives signals from the CCU.
• the BIU includes a filter which decodes a portion of the overhead bytes of
• each received cell to determine if the received cell is addressed to its BIU. If so, the
• filter also determines the addressed co-axial cable of the BIU. The filter then
• the BIU modulates the read-out signals onto an RF carrier and transmits
• Subscriber-site coaxial cables 390 couple the splitter to a number of
• TV television
• TV set-top 394 computer with a network
• NIC network interface card
• PID premises interface device
• Each of these devices parses and decodes the received reformatted cells in
• each communication device requires an interface sub-system
• the PID 398 extracts the
• the television set-top 394 converts
• the BIU also receives broadband signals for upstream transmission through
• the BIU demodulates the signals that it receives and
• position identifying indicia e.g., pointers
• the process extracts the telephony signal
• FIG. 7 sets forth one such embodiment. This apparatus is implemented in
• the CCU's TIUI 615 serves as the interface to the TIUs of the ONU 335.
• the interface includes a byte counter 705, a content addressable
• memory 710 a memory interface unit 715, swing data random access memories 720, a
• RAM control random access memory
• pointers 735 a pointer RAM control 740, a bit counter (not shown), a
• microprocessor interface unit 745 and a downstream synchronizing unit (not shown).
• the counter 705 and content addressable memory (CAM) 710 in conjunction
• the counter receives frame
• the counter also receives a synchronizing signal from the downstream
• This synchronizing signal maintains the counters in the
• the counter also receives the 19.44 MHz SDH-byte clock to generate three
• the counter is a byte counter which generates sets of count
• Each set of count values serves as a pointer that specifies the location of a byte
• Each pointer is input to the
• the invention are designed to multiplex and demultiplex SDH-like frames with a
• Each telephony cell is composed of
• the counter Given this cell structure, the counter generates (1) a cell count value
• RxCellCnt that specifies the cell count of the currently received byte
• RxGrpCnt that specifies the group count of the currently received byte
• the DSO number 8 within each group is used as the super-frame, multiplexed
• the CAM 710 receives the generated count values
• a CAM is a memory device with the ability to compare
• any set of signals (e.g., a data word) presented to it with all of the CAM contents at
• received packets are addressed to LANs connected to the bridges or routers.
• Figure 8 presents one example of the CAM 710 that can be used in some scenarios
• the CAM includes control
• circuitry 805 a first memory 810, a second memory 815, downstream comparators
• the first and second memories could be part of a single memory array.
• the first and second memories couple to the microprocessor 625 to receive respectively
• control signals e.g., block size
• the first memory 810 receives
• the first memory stores thirty position
• each position identifying indicia is a pointer that specifies
• each stored pointer can have
• the microprocessor stores control bits that
• the second memory stores thirty two sets of control
• set of control bits includes two bits.
• interface unit decodes the two control bits corresponding to the matched pointer in
• the CAM also includes thirty-two comparators 820. Each
• comparator compares a particular thirteen-bit pointer stored in the first memory with
• row in the first memory array receives the bits stored in row n (Rn) from columns 0 to
• RxCellCnt RxGrpCnt, and RxDSOCnt.
• Each comparator includes thirteen X-NOR gates, with each X-NOR gate
• comparator also has an AND gate (not shown) which receives the outputs of the
• pointer's comparator indicates a hit (i.e., a match) by pulling its output line high.
• the memory interface unit 715 receives the thirty bits
• This interface unit includes a priority encoder
• decoder 825 of the second memory This decoder then latches and outputs the two
• control bits stored at the row identified by the received address signal The memory interface unit then receives these two bits, which, as described later, direct the interface
• the CAM also receives the CellType signal (such as RxCellType or
• TxCellType This signal indicates whether the cell that is currently being received in
• the received frame is a telephony cell or a non-telephony cell.
• the CCU includes a memory (not shown) with forty one registers for the forty one cells
• Each register stores a CellType flag that indicates whether its
• corresponding cell is a telephony cell.
• the CCU sequentially reads the forty one registers to generate the
• interface unit receives the downstream signal stream. It also receives the generated
• the interface unit uses this address to retrieve the two
• the interface unit extracts
• embodiment includes a priority encoder 905, an OR gate 910, and a downstream (DS)
• Priority encoder 905 receives the thirty two bit output of the CAM.
• the state machine also receives an enable signal 920, as well as the five-bit
• the enable signal is the output of the OR gate 910, which
• the OR gate output is also active. This active signal causes the DS state
• the DS state machine determines
• the state machine 915 generates address and control signals to store the extracted bytes in the data and control RAMs 720 and 725. For some embodiments of the invention,
• RAMs 720 and 725 for storing extracted bytes whose locations in the signal stream
• the memory interface unit is designed
• the memory interface unit extracts either telephony data signals or telephony
• control signals from the frame The two signal types are treated differently in the way
• control signals are written to control RAM 725, whereas the data
• control RAM is a 128x8, dual port RAM, while the data RAM is formed by two
• RAMs 720 and 725 are where the telephony data and control signals cross from
• the "swing" buffer has two memory areas so the 19 MHz domain can write
• the memory interface unit 715 determines which of the "swing" RAMs to
• control signals do not require more than one RAM to cross the 19 MHz - 4
• the 4 MHz side is given priority over the 19 MHz side in the
• the DS TIU interface 730 couples to four TIUs A, B, C,
• This interface also couples to the pointer control 740 to receive addresses of
• the pointer table couples to the
• microprocessor 625 through the pointer control 740 and the microprocessor interface
• the pointer control 740 serves as an arbitor which controls access to the table
• the pointer control receives the 4.096 MHz clock signal, the frame synch signal,
• a bit counter (not shown) of this pointer control receives the
• the control unit 740 receives the DS synch signal from the
• downstream synchronizer (not shown), in order to synchronize its counter with the
• sixty four count values define sixty four time slots during which the pointer control
• the TIU interface 730 reads the RAMs at each of the four addresses output by the TIU interface 730.
• the TIU interface then forwards the four sets of retrieved signals to the four
• TIUs A, B, C, and D TIUs A, B, C, and D.
• FIG. 10 illustrates this read out operation pictorially for one embodiment of
• the invention which stores 120 telephony data bytes in each data RAM 720, and stores
• the DS TIU interface reads out overhead bytes (e.g., parity
• Each TIU 355 receives one set of
• the pointer RAM control 740 alternatively reads out telephony
• Data and control signal fetching are done for each of the TIU in a particular
• the DS TIU interface 730 retrieves
• pointer control 740 are designed and manufactured by using a hardware design
• one possible design for the DS TIU interface unit is
• network 300 multiplexes telephony application signals and non-telephony application
• This embodiment stores position
• identifying indicia e.g., pointers
• Figure 11 sets forth one such embodiment of the invention. This embodiment
• the interface apparatus 1100 constantly receives four telephony data
• the apparatus 1 100 of Figure 11 can be
• this apparatus has a byte counter 1105,
• a CAM 1100 a memory interface unit 1115, two dual port data RAMs 1120, a dual
• port control RAM 1 125 an upstream (US) TIU interface 1130 , a table 1135, a pointer
• control 1140 and a microprocessor interface unit 1145. However, it also includes a
• delay FIFO 1150 an early counter 1155, and a set of eight OR gates 1160.
• the operation of the apparatus 1100 is similar to the operation of the apparatus
• control 1140, the table 1135, and the US TIU interface 1130 act as a cross connect
• the US TIU interface 1130 couples to TIUs A, B, C,
• This interface also couples to the table 1135 via the control unit 1140 to receive addresses of locations in the data and
• control RAMs 1120 and 1125 in which it can store the received telephony bytes.
• table 1135 couples to the microprocessor 625 through the control unit 1140 and the
• microprocessor interface unit 1145 in order to receive and store address signals from
• the table 1135 is controlled by the pointer control 1140, which includes a bit
• This control unit receives the 4.096 MHz clock signal, the frame
• the control unit's bit counter receives the
• control unit 4.096 MHz clock signal to generate a nine-bit count at this frequency.
• the control unit 1140 receives the US synch signal from the
• downstream synchronizer (not shown), in order to synchronize its counter with the
• the US TIU interface 1130 uses these 256 addresses to
• the pointer RAM control 1140 directs the table 1135 to
• the table 1135 includes seven bits for defining a row address, one bit for selecting
• the pointer RAM the pointer RAM
• control 740 is designed and manufactured by using a hardware design language
• the US TIU interface 1130 is designed and manufactured by using a
• the memory interface unit 1115 also accesses the data and control RAMs 1120
• the memory interface unit 1115 couples to the 19.44 MHz
• the memory interface unit also couples
• the early counter 1 155 cause memory interface unit to read out the
• count values generated by the early counter are a predetermined number of bytes (e.g.,
• counter 1155 generates count values which identify the locations (or time slots or time
• the CAM 1110 can store up to
• each pointer specifies the location of a
• the CAM also stores
• the CAM receives a count value from the early counter, it simultaneously
• the CAM outputs a hit signal on the output line for
• the memory interface unit 1115 receives the thirty two output lines of the
• the memory interface unit (like the
• memory interface unit 715 of apparatus 700 uses a priority encoder to encode the
• the memory interface unit then receives these two bits.
• memory interface unit 1115 is designed and manufactured by using a hardware design
• the memory interface unit stores the extracted telephony data bytes in the
• delay FIFO 1150 while it stores some of the extracted telephony control bytes in a
• the early counter is a predetermined number of
• the memory interface unit uses the delay FIFO 1150 to store the extracted
• the delay FIFO stores thirty two sets of nine bits.
• the interface unit can store a telephony data byte in eight bits of each set.
• the memory interface unit (1) reads out the set of bits that was input first, and (2) can store a telephony data byte in the FIFO. Also, each time the
• FIFO are advanced one stage.
• the early counters and the delay FIFO allow the memory interface unit to
• the memory interface unit can combine in proper order the telephony control
• the memory interface unit stores the extracted telephony control bytes in a
• a three byte circular buffer is
• this unit uses a frame count
• the memory interface unit reads out the contents of the delay RAM and the
• gates receive the output of the memory interface unit or another signal stream, but not
• the invention also provides method and
• embodiments extract these sets of signals from the signal stream. This demultiplexing
• Some embodiments of the invention also efficiently perform the
• multiplexing operation by using a CAM to quickly identify appropriate locations in a
• CAMErr ⁇ ErrMulHit
• BitOffSetS ⁇ 9'dO; MsgUrD ⁇ - iUPD [7:0] ;
• BitOffSetChg ⁇ 1'bO; end end end else begin always a (posedge Clk4 or negedge RESET4M_)
• PCMSigOffB ⁇ B'h02; ⁇ /'dU,-ltOtfSct ⁇ 8 (16(dUltUttSct))), end else if (UpUr 8 dPCMSlgOffB) iimiii IIII im ii IIII mmmuiiimm/uuui/iiiiuuuim begin ' II Master bit counter, reference frame pulse and frame count register
• PrtyByteA ⁇ PrtyAccA
• PrtyByteB ⁇ PrtyAccB; MsgHldCmd ⁇ - MsgCmd;
• PrtyByteC ⁇ PrtyAccC
• PrtyByteO ⁇ PrtyAccD; else if (MsgHldCmdClr)
• PrtyAccA ⁇ -ShftOByteA
• PrtyAccC ⁇ -ShftOByteC
• PrtyAccD ⁇ -ShftOByteD; end always 3 (posedge Clk4 or negedge RESEI4M_) else if (LdShftRegs) If (IRESET4M ) begin begin
• TDDAReg ⁇ ⁇ TDDARegt6:01 ,1'bO); end end
• UpRdyDsTlnt4H reg [7:0] PrtyByteB; // iUPA, reg [7:0] PrtyByteC; // iUPRNU, reg [7:0] PrtyByteO; // iUPD, reg [7:0] PrtyAccA; //
• reg [7:0] SigAISByte; // Msgshn ⁇ eiu; reg AutoAIS; // HsgBLAddSelD; // reg [3:0] UpAIS; // wi re HsgBUrDSelD; // reg HsgPend; // wi re PCMBSelNrmA; // reg HsgEnA; // PCMBSelNrmB; // reg HsgEnB; // PCMBSelNrmC; // reg HsgEnC; // PCMBSelNrmD; //
• reg HsgEnD // PCMBSelAISA; // reg 17.0] HsgHldCmd; // PCMBSetAISB; // reg [7:0] HsgHldHAdd; // PCMBSelAISC; // reg [7:0] HsgHldLAdd; // PCMBSelAlSD; // reg [7:0] HsgHldUrD; // SigBSelNrmA; // reg [1:0] DrflsgFC; // SigBSelNrmB; // reg [8:0] BitOffSet; // SigBSelNr C; // reg [8:0] BitOffSetS; // // reg BltOffSetChg; // SigBSelAISA; //
• SigBSelAISB // wire dMsgCmd, // SigBSelAISC; // wire dMsgAdd; // SigBSelAISD; // ire dMsgUrD; // DnSigRen; // wire dHsgXmtEn; // wi re FSSel; // wire dMsgPend; // RsrvBSel, // wire dPCMStgOffB; // PrtyBSel; // wire dPCMAISByte; // AlrmBSel; // wire dSigAISByte; // PCMSigBSel; // wire dAutoAlS; // PCMBSel; // wire dUpAIS; // SigBSel; // wire dBltoffSet; // LdShftRegs; // wire dAny, // [5:0] DnPRAdd; // wire UpRdyOsTlnt4H; // [6:0] DnSigRAdd;
• UpRdyPtrRmCtUM, iUPA, always a (posedge Ct k4 or negedge RESET4M_) iUPRNU, i f ( I ESET4M ) iUPD, dUpReq4M ⁇ 1 'bO;
• Pointer RAH Add mux and control signals assign PtrRAdd : (PtrRAddDS 8 f CPtrRRenDS) ⁇ ) (PtrRAddUS 8 ⁇ 7 ⁇ PtrRAckUS)))
• ( ⁇ UPA[7:1l 8 ⁇ 7(UpPtrRmRdy))); assign PtrRCeb -(PtrRRenDS
• UpPtrRmRdy); assign PtrRURb -iUPRNU 8 UpPtrRmRdy;
• II sc ClkList ⁇ Clk4 Usclk4b) output // II sc create_clock Clk4 -period 220 -waveform ⁇ 0 110) output [7:0] //Up- stream PCH RAM Data-in II sc set_clock_skew -uncertainty 3 ClkList output [7:0] //Up- stream PCH RAH Urite Address- In II sc set fix hold ClkList output //Up- stream PCH RAH Urite Enable II sc set falsejiath -from (RESET4M_) output //Up- stream frame reference pulse II sc set ⁇ dont_touch_network ClkList * output UsOffSetRef; // .
• UpRDUslInt reg [6:0] UsPUAddLwr; // UplntUsTInt reg [1 :0] IntAdd; // ); reg [1 :0] PtrRAddLwr; // reg PtrRReqUSa; // reg PtrRReqUSb; // reg UsiigRdBlk4M; // reg SigEn; // input RESET4M ; reg PCMEn; // input Clk4; reg UsUen; // input UsCntrRst; // reg 17:0] Prty ⁇ yteA; // input [2:0] UsFrmCnt; / reg 17:0] PrtyByteB; //
• PrtyAccD // pUpRdyUsTlnt4H; // //
• III 11/111 II III// II III IIIII II I llll II III! III II llll llimillll I III llll I begin t Processor address decodes UpAIS ⁇ 4'hf ;
• PCHAISByte ⁇ 8'h7f; end assign Activity - ⁇ ActivityD,ActivityC,Act ⁇ vityB,ActivityA); else if (UpUr 8 dPCMAISByte) begin always 3 (posedge Clk4 or negedge RESET4H_)
• PCMAISByte ⁇ ⁇ ' UPD[7:0]; begin end if (!RESET4H_) end begin
• LatAlml [6] ⁇ LatAlml [6] 1 -(-OsPrtyAlmB 8 LatAlmlUr 8 ⁇ UPD[61) : DsPrtyAl If (IRESET4M )
• LatAlm1l10] ⁇ LatAlmKlO] ? -(-DsPrtyAlmC 8 LatAlmlUr 8 1UPDI10J) DsPrtyA else if (UpUr 8 dlntHskO)
• IntAtmOlO] ⁇ IntAlmOlO] 7 -(IntAlmOUr t lUPDIOl) : BitOffSetChg; ( ⁇ MsgHAdd.HsgLAdd) 8 ⁇ 16 ⁇ *sgAdd))>
• FrmCnt ⁇ UsFrmCnt; end end end always 3 (posedge Ctk4 or negedge RESET4M_) always 3 (posedge Clk4 or negedge RESET4H_) begin begin if (!RESET4M_) if (!RESET4M_)
• MsgFrmCnt ⁇ 2'bOO; begin else if (LastBit) TUDCReg ⁇ - B'hOO;
• SigHldRegB TUDBReg; always 3 (posedge Clk4 or negedge RESET4H )
• SigHldRegC ⁇ TUDCReg; if (IRESET4H )
• SigHldRegD ⁇ TUDDReg; begin end
• ActtvttyD ⁇ GotEdgeD; end end else if (LdPrty) begin
• PrtyByteD ⁇ PrtyAccD
• PrtyAccB ⁇ -TUDBReg
• PrtyAccA ⁇ PrtyAccA * TUDAReg; always 3 (posedge Clk4 or negedge RESET4H )
• PrtyAccB ⁇ PrtyAccB " TUDBReg; if (IRESET4M
• PrtyAccC ⁇ PrtyAccC " TUDCReg;

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• 1997
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