WO1999000904A1

WO1999000904A1 - Interleaved differential analog-to-digital converter

Info

Publication number: WO1999000904A1
Application number: PCT/US1998/010835
Authority: WO
Inventors: James Jason Locascio
Original assignee: Maxim Integrated Products, Inc.
Priority date: 1997-06-30
Filing date: 1998-05-28
Publication date: 1999-01-07
Also published as: WO1999000904A9; WO1999000904A8

Abstract

An interleaved differential analog-to-digital converter which allows differential analog-to-digital conversion of interleaved segments of two or more analog signals to be converted without loss of partial bits at the end of each conversion segment. The converter utilizes a separate feedback capacitor for each analog signal to be converted, together with a switch for switching the feedback capacitor into the circuit when the respective analog input is to be converted and for switching the respective capacitor out of the circuit when the respective analog input signal is not being converted. Thus, each feedback capacitor, when switched out of the circuit, will retain a charge representing whatever fraction of a bit remained thereon when switched out of the circuit, so that when switched back into the circuit, the conversion of the next respective analog signal segment may begin from that value of charge. Thus, loss of fractional bits at the end of the conversion of each segment is prevented. Various embodiments are described.

Description

INTER EAVED DIFFERENTIAL ANALOG- TO -DIGITAL CONVERTER

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of differential analog-to-digital converters .

2 . Prior Art

Differential analog-to-digital converters are well known in the prior art. These converters are characterized as having an analog input, reference voltage inputs, and a clock input, typically limited to a predetermined number N of clock cycles for a single A/D conversion. The output of such converters comprises a number of pulses which may range from zero to N pulses, depending on the analog input voltage and the reference voltages used for the converter.

A simplified block diagram for a converter of the foregoing type may be seen in Figure 1. In this Figure, an operational amplifier 20 has its non-inverting input connected to ground G. The output of the operational amplifier 20 is coupled through feedback capacitor 22 to the inverting input of the amplifier, with the inverting input also being connected to the input voltage Vin through a resistance 24, and connectable to a voltage reference VR+ through a resistance 26 and switching transistor 28, and connectable to a negative reference voltage VR- through a resistance 30 and a switching transistor 32. The output of the operational amplifier 20 is also applied as the inverting input to comparator 34, the non-inverting input of which is also connected to ground G. The output of the comparator 34 is coupled to a clocked flip-flop 36, which provides a gating signal to AND gate 38 to gate the clock signal CLK there through, as delayed by delay 40, whenever the output of the flip-flop 36 is high. The output of the flip-flop is also fed back through line 42 to control switching transistor 28 and inverted by inverter 44 to control switching transistor 32. Also, feedback capacitor 22 has a switching transistor N2 there across to allow the controlled discharging of capacitor 22 by a reset signal

RESET prior to each conversion operation.

In the description to follow, it is assumed that the potential G is ground, that the reference voltages VR+ and VR- are positive and negative voltages of the same magnitude, and that the resistances are equal. These restrictions are by no means required in the prior art, though are convenient for purposes of explanation of the operation of the circuit.

Prior to a conversion cycle, switching transistor 46 is momentarily turned on to discharge capacitor 22. Also assume that the flip-flop 36 is initially reset so that the output on line 42 is low. This turns on switching transistor 28, and turns off switching transistor 32 through inverter 44. If, by way of example, the input Vin is half way between the reference voltages VR+ and VR-, in this specific example Vin equals zero, current through resistance 26 will cause the output of amplifier 20 to go negative to drive the current into the inverting input of the amplifier to zero. This, in turn, causes the output of comparator 34 to go positive, so that on the first clock pulse CLK, AND gate 38 will gate the clock pulse to the AND gate output, delay 40 allowing the output of the flip-flop 36 to settle to enable (or in some cases to disable) the AND gate 38 prior to passage of the clock pulse to the second input of the AND gate.

The output of the flip-flop 36 going high turns off switching transistor 28 and turns on switching transistor 32, so that now the negative reference VR- is coupled through resistance 30 to the inverting input of amplifier 20. This then starts to drive the inverting input of the amplifier 20 negative, causing the output of amplifier 20 to move in the positive direction to again adjust the current to the summing point on the inverting input to zero. Assuming the output of the amplifier 20 actually goes positive, the output of comparator 34 will go negative so that on the next clock pulse, the output of flip-flop 36 will go negative, disabling AND gate 38 so that the delayed clock pulse CLK will not pass to the output of the gate. Again, the reversal of the output of the flip-flop reverses the state of switching transistors 28 and 32 so that, in general, half the clock pulses occurring during the conversion time will pass AND gate 38, and half will not. Going to the other extremes, if the input voltage were as high as VR+, then the current through resistance 24 would equal the current through resistance 30 in the reverse direction, so that once the state of the amplifier 20 and of comparator 30 were such that the output of flip-flop 30 was positive, enabling AND gate 38, the circuit would remain in this state throughout the conversion time, passing all N clock pulses during the conversion time, except perhaps for one clock pulse required to initially determine the output state of the amplifier 20. Similarly, if the input voltage equals the negative reference voltage VR-, the opposite will occur, the output of flip-flop 36 being low for all clock pulses except perhaps the first clock pulse, limiting the clock pulses output by AND gate 38 to one or less.

In general, it is preferred to not reach the extremes in the range of the converter. Also, the reference voltages VR+ and VR- need not be equal and opposite voltages, but might be both positive voltages or a positive voltage and ground. Similarly, the value of resistances 24, 26 and 28 need not be equal, but if they are, and the timing is equal, the range of the input voltage Vin should be limited in its lower value to the reference voltage VR- or slightly above, and at its upper value to the reference voltage VR+ or slightly there below.

The type of converter generally illustrated in Figure 1 works well when making successive analog-to- digital conversions on a continuous signal, as there is no requirement for the analog signal to be held steady during the conversion period, such as by a sample and hold circuit. Further, one can switch to a different analog signal after each conversion period so that the same converter may be used to sequentially convert a plurality of analog signals, the actual conversion times of course being staggered to allow the passage of the full conversion time for each analog signal before initiating conversion on the next analog signal. However, in some cases it may be desired to have the analog-to-digital conversion of two analog signals represent the state of the analog signals at the same or substantially the same time, as opposed to representing the conversion of one signal time shifted with respect to the conversion of the prior signal. In such a case, the conversion time for each analog signal may be broken into a plurality of partial conversion times interleaved in time so that, by way of example, for the conversion of two such analog signals, the conversion process would comprise a sequence of begin to convert signal one, then begin to convert signal two, then continue converting signal one, then continue converting signal two, then further continue converting signal one, etc., repeating the sequence in time until the full conversion of each of the two signals is achieved. In such a situation, one can switch back and forth between two counters so that each counter would accumulate the total pulse count for the respective analog signal conversion, or, as appropriate in the application of the preferred embodiment of the present invention, to use a single counter to count up during the conversion of one of the signals and to count down during the conversion of the other signal being converted.

The converter of Figure 1 could be used with such an interleaved conversion sequence by converting a first segment of one analog signal, then converting a first segment of the second analog signal, then converting a second segment of the first analog signal, then converting the second segment of the second analog signal, etc., until the full conversion is achieved. However, between conversions of each segment, capacitor 22 would have to be discharged through switching transistor 46, as any charge left on that capacitor from the conversion of a segment of one signal has no meaning and thus would create an error with respect to the conversion of a segment of the second signal. Discharging the capacitor in this manner, however, is equivalent to throwing away some fraction of an output pulse at the conclusion of the conversion of each segment. While this effect might be small and could average to zero for the conversion of each signal over the full conversion time, it could also be large, representing a large percentage of an additional pulse. By way of example, if two analog signals were converted using ten interleaved segments of each signal, the error could, without warning, be as high as nine pulses, negating the desirability of the interleaving in the first place. Thus, the only way to avoid this problem using the prior art converter of Figure 1 in the case of interleaved signal segments would be to go to the expense of using two converters, in which case, unless there was some other reason for interleaving the signals (as there actually is in the application of the preferred embodiment of the present invention) , the two converters could simply be operated simultaneously, each on a respective one of the two signals without any interleaving .

In Figure 1, resistances 24, 26 and 28 may be ordinary resistors . It is also known in the prior art generally, however, that a capacitor may be switched to simulate a resistor, with switched capacitor circuits having some advantages when realized in integrated circuit form over the inclusion of ordinary resistive elements as part of the integrated circuit . A typical switched capacitor circuit is shown in Figure 2, wherein capacitor C has one end connected to a fixed voltage such as ground, and the other end connected to two switches, SW and SW operating in a non-overlapping complementary manner so that both switches are never closed at the same time.

In this circuit, when switch SW is closed, capacitor C charges so that qi = CVi . When switch SW opens and then switch SW closes, the charge on the capacitor will readjust through the output V₂ to q₂ = CV₂. Thus the charge delivered to the output V₂ from the input Vi is equal to q2 - qi = C (V2 - Vi) . If this is repeated M times per second, then the charge transfer r\rr per second, — = i, = MC (V₂ - Vi) . Thus on average, the dt capacitor looks like a resistor between Vi and V₂, passing a current proportional to the voltage difference

V₂ - Vi with an apparent resistance equal to 1/MC.

BRIEF SUMMARY OF THE INVENTION

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a simplified block diagram for a prior art differential analog-to-digital converter. Figure 2 is a circuit diagram for a typical switched capacitor.

Figure 3 is a simplified block diagram of a preferred embodiment of the present invention.

Figure 4 is a representative waveform diagram for the clock signal CLK and the converter control signals

CON1 and CON2 for the embodiment of Figure 3.

Figure 5 is a block diagram of an alternate preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

In the description of the prior art, and in the following description of exemplary embodiments on the present invention, the exemplary circuits presented use n-channel FET transistors for the various switching devices in the circuits. It is to be understood however, that transistors of an opposite conductivity type, and transistors of different types may be used as desired.

Now referring to Figure 3, a simplified block diagram of a preferred embodiment of the present invention may be seen. In this Figure, elements identified by the numerals 44 and less correspond in structure and function with the elements of the same identification numerals in Figure 1. Thus, the clock signal CLK is gated or not gated through AND gate 38, dependent upon the output of comparator 34 responsive to the output of the operational amplifier 20, with the output of the flip-flop 36 determining which of switching transistors 28 and 32 is turned on, and thus which of the voltage references VR+ and VR- is connected to the inverting input of the operational amplifier. In place of the feedback capacitor 22 of Figure 1 are two feedback capacitors 50 and 52. Which of capacitors 50 and 52 is connected as the feedback capacitor for operational amplifier 20 at any particular time is controlled by which of transistors 54 and 56 is turned on at the particular time. These transistors are controlled by non-overlapping converter control signals

CON1 and CON2 (active low) . The signals CON1 and CON2 also control switching transistors 58 and 60, so that when feedback capacitor 50 is coupled as the operative feedback capacitor for operational amplifier 20, switching transistor 58 is also turned on, coupling the first input signal Vinl through transistor 58 and resistance 52 to the inverting input of operational amplifier 20.

When the converter control signal CONl is high, switching transistor 58 is turned off, decoupling the first input Vinl from the circuit, and similarly decoupling feedback capacitor 50 from the feedback circuit of the operational amplifier 20. When so decoupled, the capacitor 50 will maintain its charge, and thus maintain whatever partial bit in the converter output that may be represented thereby until the capacitor 50 is again switched back in circuit. Thus, when the converter control signal CON2 goes low, switching transistors 56 and 60 are turned on, now coupling the second input Vin2 through resistance 64 to the inverting input of amplifier 20, and similarly now coupling feedback capacitor 52, with whatever charge it may have thereon, into the feedback circuit of the operational amplifier 20.

The operation of the circuit of Figure 3 may be explained with reference to Figure 4, which shows the timing signals for an exemplary operation of the circuit of Figure 3. As shown therein, before the beginning of conversion, the signals RESETl and RESET2 are both low, turning on transistors 66 and 68 to initially discharge both feedback capacitors 50 and 52. In the sequence being described, RESETl and RESET2 may be connected in common, though as shall subsequently be seen, it may be required that these signals be independent signals.

Just before the conversion period begins, both

RESETl and RESET2 go high. Then the conversion control signal CONl goes low, turning on switching transistors 54 and 58, coupling feedback capacitor 50 into the feedback circuit of amplifier 20 and coupling the first input Vinl to the summing point of the amplifier. Conversion then proceeds for M clock cycles, after which the converter control signal CONl again goes high, turning off switching transistors 54 and 58. This decouples the first input Vinl from the summing point and decouples feedback capacitor 50 from the feedback circuit of amplifier 20, leaving whatever charge existed on capacitor 50 at the end of the partial conversion.

Then the converter control signal CO 2 goes low for another M clock cycles, turning on switching transistors 56 and 60. This couples feedback capacitor 52 into the feedback circuit and couples the second input Vin2 to the summing point of the amplifier. Thus, conversion of the second input signal Vin2 proceeds for M clock cycles, after which transistors 56 and 60 are turned off to decouple the second input Vin2 from the summing point and to decouple feedback capacitor 52 from the feedback circuit. Then transistors 54 and 58 are again turned on to couple feedback capacitor 50, with whatever charge was left over from the first partial conversion of M clock cycles, into the feedback circuit of amplifier 20, and to couple the first input Vinl back to the summing point . Accordingly, conversion will continue on the first input signal Vinl starting with whatever partial charge remained on the feedback capacitor 50 at the end of the first conversion segment. Thus, while the conversion of the two signals Vinl and Vin2 is an interlaced conversion, nothing is lost by the interlacing. In the example shown in Figure 4, the interlaced segments are each M clock cycles long, with the total conversion of each of the input signals Vinl and Vin2 being N such sequences long.

The output 70 of AND gate 38 (Figure 3) of course may be used as desired. In the preferred embodiment, Vinl and Vin2 are actually the voltage across the same two points, namely the voltage across a pn junction diode, though with two distinctly different currents through the diode. Thus, in this particular application, only one input connection is used, though that one input is converted as two signals synchronously with the alternating of the current in the pn junction between the two distinct current levels . In that application, the output on line 70 of AND gate 38 is provided to a counter, counting up during the conversion for the higher pn junction current conversion segments, and counting down during the lower current pn junction segments, to provide a final counter output at the end of the conversion responsive to absolute temperature.

In the foregoing example, the conversion of the two signals begins and ends at essentially the same time, except for the effect of the staggering due to the interleaving of the N signal segments of each of the two signals. In the case of the voltage across the pn junction diode, typically N will equal 10 in the preferred embodiment. However, in other instances, the beginning and/or the end of the conversions of the two signals need not coincide. By way of specific example, it might be desired to provide digitized values of an analog signal in time increments of ΔT, with each digitized value representing the average of the analog signal during the preceding time period of 2ΔT for smoothing purposes. For this purpose, the M clock pulses may be selected to occur by way of example, in a time period of ΔT/5, with the conversion of the two signals alternating five times during each ΔT time period. At the end of even increments of time ΔT, the total pulses for the first conversion for the prior 2ΔT time increments would be noted and the corresponding feedback capacitor momentarily discharged to begin a new even ΔT conversion cycle. Similarly, at the end of odd increments in ΔT, the total pulse count for the second conversion would be noted and the corresponding feedback capacitor momentarily discharged to again begin a new odd ΔT conversion cycle for the second signal. These, of course, are but mere examples in which the interleaved converter of the present invention may be used.

Now referring to Figure 5, a further embodiment of the present invention may be seen. In Figure 5, elements identified with the numerals 70 or less are the same as, and have the same function as, the elements have the corresponding identification numerals in Figure 3, and accordingly, the function and operation of these elements will not be expressly repeated. Also, in Figure 5, the diagram shown is exemplary only, and does not include provisions one would make to assure non- overlapping signals where such signals are required. By way of example, rather than utilizing separate conversion control signals CONl and C0N2 as in Figures 3 and 4, a single two state conversion control signal HL is used, turning on transistor 54 and inverter 80 turning off transistor 56 when the signal HL is high, and turning on transistor 56 through inverter 80 and turning off transistor 54 when the signal HL is low. It is important that both transistors 54 and 56 not be on at the same time, even momentarily, to avoid dumping any part of the charge on either capacitor 50 or 52 to the opposite capacitor. Thus, when the signal HL goes low, it is important that the gate of transistor 56 be driven high to turn off that transistor prior to the gate of transistor 54 getting sufficiently low to turn on that transistor, in spite of the slight time delay imposed by inverter 80. Similarly, the switched capacitor circuits used also require non-overlapping signal. Circuits to assure such non-overlapping signals are well known in the prior art, however, and accordingly will not be further described herein.

The embodiment shown in Figure 5 is intended for use with the pn junction temperature sensor herein before described. Since the voltage drop across the pn junction for the higher current and the lower current are both positive voltage drops, references voltages of VREF and ground are used, rather than the VR+ and VR- of the embodiment of Figure 3. Also, since the voltage drop across the pn junction is merely the voltage at a single point under two different pn junction current operating conditions which are synchronized with the signal HL, only a single input line Vin is used. Further, as shall subsequently be seen in greater detail, the resistances equivalent to resistances 26, 30 and 62 associated with reference voltages and the one input are realized using switched capacitors . Because of the VREF and ground reference rather than positive and negative reference voltages, the non-inverting inputs to amplifier 20 and comparator 34 are coupled to a positive reference voltage VRP5. The basic clock signal input CK to the circuit of Figure 5 is provided as one input to NOR gate 82 , the second input to the NOR gate being a stop clock signal STCK. When the signal STCK is high, the output of NOR gate 82 will be clamped low, holding the output of AND gate 38 low to prevent any further output pulses on line 70. When the signal STCK is low, NOR gate 82 will invert the clock signal CK to enable one input of AND gate 38 with the inverted clock signal. Also, inverter 84 reinverts the clock signal CK so that the signal CK appears on line 86, with inverter 88 providing the inverse thereof on line 90. The second input to Nor gate 110 is provided by the signal RAB. When the signal RAB is low, the output of NOR gate 110 will be clamped high, freezing the clock signal to the flip-flop 36. When the signal RAB is high, the output of NOR gate 110 reinverts the already twice inverted clock signal CK, clocking the output state of the comparator 34 to flip- flop 36, and after the delay of delay 40 (and with STCK low), through AND gate 38 to the pulse output 70.

The signals on lines 86 and 90 control switching transistors 92 and 94, forming the switches for switched capacitor 96 on the input Vin. The clock signal CK on line 86 also controls switching transistors 98 and 100, turning the same on when the clock signal CK is low. When the clock signal CK is high, the voltage on line 90 will be low, turning on transistor 100. The alternate (non-overlapping) on and off of transistors 98 and 100 similarly form the switches for switched capacitor 102 to effectively provide a switched capacitor resistance between the inverting input of amplifier 20 and ground. The signal on line 90, which is the inverse of the clock signal CK, is also applied as one input to AND gates 104 and 106. The other input to AND gate 106 is provided by the output Q of flip-flop 36 on line 108, with the second input to AND gate 104 from the output of inverter 40 being the inverse of the output of the flip-flop. The output of AND gate 104 controls switching transistor 112, with the output of AND gate 106 controlling the switching transistor 116 across the switched capacitor 116.

The operation of the circuit of Figure 5 may be described as follows. The signal CLR when driven low will discharge the feedback capacitors 50 and 52, like the reset lines RESETl and RESET2 of the embodiment of Figure 3. Also, the HL signal will select which of the feedback capacitors 66 and 68 are in the feedback circuit, much like the converter control signals CONl and CON2 of Figure 3. Assume that the feedback capacitors 50 and 52 have been discharged and the signal CLR driven high again. Also, signal HL has been set to select the desired feedback capacitor, the signal STCK is low, and the signal RAB is high. Also assume, for purposes of specificity, that the output Q of the flip- flop 36 is low, holding one input of AND gate 106 low to effectively disable the other input, and holding one input of AND gate 104 high, effectively enabling the other input to this AND gate. When the clock signal CK is low, the voltage on line 86 will be low, holding transistors 92, 98 and 100 off. The voltage on line 90 will be high, however, turning on transistor 94 to charge capacitor 96 to the input voltage Vin and to hold one input to AND gates 104 and 106 high. Because the output Q of the flip-flop 36 is low, the second input to AND gate 106 will be low, holding the output of the AND gate low and thus transistor 114 off. Thus, transistor 114 will remain off whenever the output Q of the flip- flop 36 is low. The second input to AND gate 104, however, through inverter 40, will be high, turning on transistor 112 to charge switched capacitor 116 to the reference voltage VREF. Also, because the output of the flip-flop 36 is low, the output 70 of AND gate 38 will remain low, even though the second input to the AND gate is high.

When the clock signal CK goes high, transistors 94, 100 and 112 will be turned off and transistors 92, 98 and 100 will be turned on to couple capacitors 92, 98 and 100 together and to the inverting input of amplifier 20. Charge from the switched capacitors dumps into (or out of) the summing point when the clock signal goes high. Since the purpose of the operational amplifier is to readjust the amplifier output to maintain the differential voltage between the inverting and non- inverting input at substantially zero, the output of the amplifier will quickly reduce (or increase) so that the feedback capacitor which is operative at the time will absorb the net charge dumped to (or taken from) the summing point. If that net charge is not adequate to drive the output of amplifier 20 below the reference voltage VRP5, the output of comparator 34 will itself remain low, maintaining the flip-flop output Q low for another cycle of the clock CK. However, whenever the charge dumped to the summing point is enough to drive the output of the amplifier 20 below the reference voltage VRP5, the output of inverter 34 will go high. Then, when the clock signal CK again goes low, the output of AND gate 110 will go high, clocking the high output of the comparator 34 to the flip-flop 36, and then to one input of AND gate 38. After that input stabilizes, the delay 40 will pass the high output of NOR gate 82 to the second input of AND gate 38 to pass the clock pulse to the output 70.

The high output of the flip-flop 36 will hold one input of AND gate 104 low and one input of AND gate 106 high. The low clock signal will also drive line 90 high, turning on transistor 100 to discharge capacitor 102 again, and driving the second input to AND gate 106 high, turning on transistor 114 to discharge resistor 116. Of course, at this time transistor 94 will also be turned on, to again charge capacitor 96 to the input voltage Vin. Then when the clock signal CK again goes high, transistors 94, 100 and 114 will be turned off and transistors 92, 98 and 100 will be turned on to readjust the charges on these three capacitors as well as the feedback capacitor, driving the output of amplifier 20 to a new voltage dependent upon the input voltage Vin.

It can be seen from the foregoing that in this embodiment, the switched capacitors 102 and 116 act as a voltage divider between the reference voltage VREF and ground. As a result, recognizing that each of capacitors 86, 102 and 116 effectively represent a resistance Rs_6> ^R ₁₀₂ and Rug, respectively, the input signal Vin appears to the summing point as a voltage source at the voltage Vin having an impedance of Rgβ in series therewith. However the reference voltage VREF appears to the summing point as a voltage source at the voltage with both the reference

voltage and ground reference voltage to the summing point appearing to have an impedance of

in

Rl02 + Rll6 series therewith.

There has been described herein interleaved differential analog-to-digital converters which allow the interleaving of the digital-to-analog conversion of multiple analog signals without loss of accuracy in the conversion due to the interleaving. Though the invention has been described with respect to circuitry and methods for the interleaving of the conversion of two signals, the principle of the invention may readily be extended to the interleaved conversion of three or more signals. Other changes may also be made as desired for the same or other applications of the invention. Thus while the present invention has been disclosed and described with respect to certain preferred embodiments thereof, it will be understood to those skilled in the art that the present invention may be varied without departing from the spirit and scope thereof.

Claims

CLAIMSWhat is claimed is:

1. In a differential analog-to-digital converter having an amplifier with a first feedback capacitor coupled between the amplifier output and the inverting input of the amplifier, the improvement comprising: a first switch coupled in series with the first feedback capacitor; a second feedback capacitor; a second switch in series with the second feedback capacitor, the second feedback capacitor and the second switch being coupled between the amplifier output and the inverting input of the amplifier.

2. The differential analog-to-digital converter of claim 1 wherein the first and second switches are controllable so that either switch may be closed without both switches being closed at the same time.

3. The differential analog-to-digital converter of claim 1 further comprised of third and fourth switches, the third switch being coupled in parallel with the first feedback capacitor and the fourth switch being coupled in parallel with the second feedback capacitor.

4. The differential analog-to-digital converter of claim 3 wherein the third and fourth switches are independently controllable.

5. The differential analog-to-digital converter of claim 3 wherein the third and fourth switches are controllable in unison.

6. The differential analog-to-digital converter of claim 3 wherein the switches are FET switches .

7. In a differential analog-to-digital converter, the improvement comprising: an operational amplifier having a non-inverting input, an inverting input and an output, the non- inverting input being coupled to a first voltage, the inverting input being coupled to receive first and second analog inputs, and a first reference voltage or a second reference voltage indirectly dependent on the output of the operational amplifier; the operational amplifier having a first feedback capacitor coupled in series with a first switch between the operational amplifier output and the inverting input, and a second feedback capacitor coupled in series with a second switch between the operational amplifier output and the inverting input, the first switch being closed and the second switch being open when the non- inverting input is coupled to the first analog input voltage, and the first switch being open and the second switch being closed when the inverting input is coupled to the second analog input.

8. The improvement of claim 7 wherein the first and second switches are FET switches.

9. The improvement of claim 7 wherein the first and second analog inputs are first and second analog signals appearing at different times on an analog input line.

10. The improvement of claim 7 further comprising: third and fourth switches; wherein the first and second analog inputs are first and second analog signals appearing on first and second analog input lines; the first and third switches being opened and closed in unison and the second and fourth switches being opened and closed in unison.

11. The improvement of claim 10 wherein the third and fourth switches are FET switches .

12. An interleaved differential analog-to-digital converter comprising: an operational amplifier, a comparator, a clocked flip-flop, a first feedback capacitor and a gate coupled as a differential analog-to-digital converter; the operational amplifier being coupled to receive first and second analog inputs the first feedback capacitor having a first switch coupled in series therewith; and, a second feedback capacitor and a second switch in series with the second switch, the second feedback capacitor and second switch being coupled in parallel with the first feedback capacitor and first switch; the first and second switches being controllable so that either switch may be closed without both switches being closed at the same time.

13. The differential analog-to-digital converter of claim 12 further comprised of third and fourth switches, the third switch being coupled in parallel with the first feedback capacitor and the fourth switch being coupled in parallel with the second feedback capacitor.

14. The differential analog-to-digital converter of claim 13 wherein the third and fourth switches are independently controllable.

15. The differential analog-to-digital converter of claim 13 wherein the third and fourth switches are controllable in unison.

16. The differential analog-to-digital converter of claim 13 wherein the switches are FET switches.

17. The differential analog-to-digital converter of claim 12 wherein the first and second analog inputs are first and second analog signals appearing at different times on an analog input line.

18. The differential analog-to-digital converter of claim 12 further comprising: third and fourth switches; wherein the first and second analog inputs are first and second analog signals appearing on first and second analog input lines; the first and third switches being coupled to open and close in unison and the second and fourth switches being coupled to open and close in unison.

19. A method of operating a differential analog- to-digital converter having an amplifier and a first feedback capacitor comprising the steps of: (a) providing a first switch in series with the first feedback capacitor;

(b) providing a second switch in series with a second feedback capacitor, and connecting the combination of the second switch and second feedback capacitor in parallel with the series combination of the first switch and the first feedback capacitor;

(c) turning on the first switch and turning off the second switch when a first analog signal is coupled to the differential analog-to-digital converter, and turning off the first switch and turning on the second switch when a second analog signal is coupled to the differential analog-to-digital converter; whereby analog-to-digital conversion of interleaved signal segments of first and second signals may be achieved without loosing feedback capacitor charge representing partial output pulses at the end of each conversion segment.