WO1998055880A1 - Procede de simulation de panne et de specification d'essais en parallele pour circuits analogiques et numeriques - Google Patents

Procede de simulation de panne et de specification d'essais en parallele pour circuits analogiques et numeriques Download PDF

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Publication number
WO1998055880A1
WO1998055880A1 PCT/CA1998/000538 CA9800538W WO9855880A1 WO 1998055880 A1 WO1998055880 A1 WO 1998055880A1 CA 9800538 W CA9800538 W CA 9800538W WO 9855880 A1 WO9855880 A1 WO 9855880A1
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WIPO (PCT)
Prior art keywords
fault
circuit
value
faults
output parameter
Prior art date
Application number
PCT/CA1998/000538
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English (en)
Inventor
Naim Ben Hamida
Khaled Saab
Bozena Kaminska
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Opmaxx, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Opmaxx, Inc. filed Critical Opmaxx, Inc.
Priority to AU76345/98A priority Critical patent/AU7634598A/en
Priority to CA002269914A priority patent/CA2269914A1/fr
Publication of WO1998055880A1 publication Critical patent/WO1998055880A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2257—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using expert systems
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316—Testing of analog circuits

Definitions

  • the present invention relates to a highly effective method for conducting parallel fault simulation and test set specification of digital and analog circuits.
  • the method according to the invention formulates the fault simulation problem as a problem of estimating the fault value based on the distance between fault-free and faulty circuit distributions of the output parameter.
  • fault simulation techniques for example parallel, deductive, and concurrent fault simulation techniques have been developed and differ from the serial method in two fundamental aspects: a) they determine the behaviour of the circuit N in the presence of a fault without explicitly changing the model of the fault-free circuit N and, b) they are capable of simultaneously simulating a set of faults.
  • cause-effect analysis enumerates all the possible faults (causes) existing in a fault model and determines all their corresponding responses (effects) to a given applied test in a serial manner.
  • the required simulation time can become impractically long, especially for large analog designs.
  • An object of the present invention is to provide a method for performing parallel fault simulation and test vector specification based on effect-cause analysis. From the distance between a fault-free circuit distribution and a faulty circuit distribution (effect), the method according to the present invention approximate a fault (cause) value for all modelled faults simultaneously by linear estimation.
  • a method for constructing a fault dictionary for a circuit in view of subsequently testing the circuit comprising the steps of:
  • the present invention also relates to a method for building test vectors in view of testing a given circuit, comprising the steps of:
  • step ( e) comparing the Frequency Division Multiple Access ( d) to a typical fault value; ( f) determining whether the selected fault is detected or undetected by applying said stimulus to the circuit including the selected fault in accordance with the result of the comparison of step ( e);
  • Figure 1 which is labelled as "prior art” is a fault model for a transistor, consisting of a transistor surrounded by switches;
  • Figure 2 is a schematic view of an inverter layout, including an intermediate list of faults of this inverter layout, and a final list of faults obtained from the intermediate list after redundancies have been eliminated;
  • Figure 3 illustrates the circuit of a simple voltage divider;
  • Figure 4 is a complete list of 9 faults that can be found in the voltage divider of Figure 3;
  • Figure 5 is a reduced list of 6 faults built from the complete list of Figure 4 after removal of redundant and undetected faults;
  • Figure 6 is a graph showing examples of fault-free and faulty circuit distributions
  • Figure 7 is a fault simulation flow chart as implemented by the method according to the invention for constructing a fault dictionary
  • Figure 8 is a hard fault test vector specification algorithm
  • Figure 9 is a schematic diagram of a second order band- pass filter
  • Figure 10 is a list of 5 faults connected to the second order band-pass filter of Figure 9, indicating that 4 out of the 5 faults have been detected by means of a single test vector;
  • Figure 11 is a graph of the output parameter of the second order band-pass filter of Figure 9 versus the frequency of the test vector, showing that for a test vector of 10 kHz the 4 detected faults of Figure 10 modified the output voltage (output parameter) by more than 5% with respect to the fault-free output voltage;
  • Figure 12 is a schematic diagram of the circuit of a fifth order chebychev filter.
  • Figure 13 is a graph showing the fault coverage as a function of the number of test vectors for an inverter, a low pass filter, a state variable filter, a chebychev filter, a 4-bit analog-to-digital converter, an 8-bit analog-to-digital converter flash, and an 8-bit current digital-to- analog converter.
  • Fault simulation is used to construct a fault dictionary.
  • a fault dictionary stores the signatures of faults in response to a specific stimulus T.
  • Prior art fault simulation techniques are fault oriented and consists of:
  • Figure 7 is a fault simulation flow chart, as implemented in the method according to the invention.
  • Step 19 A layout and/or schematic description of the circuit to be tested is first made.
  • Step 20 From the description of step 19, a layout-based fault list and/or a schematic-based fault list is/are extracted to form a fault list 21.
  • Step 22 The sensitivities of the output parameter to variations of circuit components due to manufacturing process variation is computed from the circuit description of step 19.
  • the sensitivity is defined as the ratio of the relative deviation of the output parameter to the relative deviation of the circuit component.
  • Step 23 In step 23, the fault-free circuit distribution (see Figure
  • Step 24 A stimulus T is selected.
  • Steps 25-26 The gradients of the output parameter with respect to all faults (step 25) are computed for the selected stimulus T (step 24).
  • the output of step 26 is representative of the faulty circuit distribution (see Figure 6) of the output parameter in response to stimulus T.
  • Step 27 The fault value R fau , t is calculated from the gradients computed in step 26 and the fault-free circuit distribution computed in step 23.
  • Step 29 If the response to additional stimuli is desired, the algorithm returns to step 24.
  • Step 30 If no additional stimulus response is desired (step 29) the algorithm terminates.
  • the fault dictionary is not constructed by storing the output signature of the fault f (effect), but by computing and storing the value R fau , t of the fault (cause) by parallel fault simulation.
  • R fau , t indicates the value of the resistance that, if added to the circuit, will drive the output parameter under test out of a predetermined tolerance range.
  • the output parameter is defined as a measured performance; the output parameter may be a voltage amplitude, a current amplitude or any other circuit response or specification.
  • the fault list is first extracted and the fault value R faU
  • the method according to the invention use a layout- based fault list and/or a schematic-based fault list.
  • the layout-based fault list is used at macro level while the schematic-based fault list is used at a higher level, i.e. at the level of interconnections between modules of the circuit.
  • the schematic-based fault list is also used at early design stage where macro layouts are not available.
  • the method used to generate the layout-based fault list consists of moving a defect over the entire area of the layout. At each position taken by the defect, the polygons touch and their net numbers are obtained to deduce the fault produced by the defect [H. Wlaker and
  • VLASIC A Catastrophic Fault Yield Simulator for
  • each fault is described by its type , the coordinates of the defect responsible for the fault, and a probability related to the size of the responsible defect.
  • FIG. 1 A total of 240 defects were inserted in the layout 14, which resulted in 26 faults.
  • An intermediateumble list 15 gives the type of the fault and the coordinates (position) of the defect causing the fault.
  • step 17 Eliminating the redundancy (step 17) led to the final fault list 16 of Figure 2, which contains three different faults.
  • each fault is weighted by the number of occurrences.
  • Figures 3-5 Extraction of a schematic-based fault list is illustrated in Figures 3-5.
  • the list shown in Figure 4 is not exhaustive since the only shorts listed are between the same element nodes.
  • the method according to the invention also enables generation of all combinations of two, three or more shorted nodes. Using this feature may lead to a large list of faults containing a significant amount of nonrealistic faults. The example treated in Figures 3-5 does not include these combinations.
  • the fault list is constructed of three shorts and two opens: short gate-source, short gate-drain, short source-drain, open drain, and open source.
  • the present invention proposes to construct a fault dictionary by storing the fault value
  • the effect is a constant value which represents the detectability threshold.
  • the cause is the minimal fault value that, if added to the circuit, will cause the output parameter to go out of a predetermined tolerance range and make the fault detectable.
  • the first two methods ( i) and ( ii) to define the detectability threshold are straightforward.
  • - out is the estimated value of the output parameter due to variation of the components
  • - o ⁇ is the standard deviation of the component ⁇ ,; and - o M1 are covariance terms.
  • R /( is the newly added component due to short or open and G fl out is the gradient of out with respect to the fault /, , cfy, is the standard deviation of the fault value (resistance), and o ⁇ Rfl is the covariance term between the newly added component and the components in the original fault-free circuit.
  • the detectability threshold is set to be the minimal distance between the fault-free and faulty circuits that guarantee detectability of the fault ( Figure 6). This minimal distance is given by the relation:
  • ⁇ ff and ⁇ are the mean output parameter values for the fault-free and faulty circuit distributions, respectively, and ⁇ ff and ⁇ are the estimated fault-free and faulty output standard deviations of these distributions, respectively.
  • the adjoint network method allows to compute the sensitivities of one output parameter with respect to all component variations (existing and non-existing components) in only two simulations, one for the original network and one for the corresponding adjoint network.
  • the values R feuff are stored in the fault dictionary.
  • the mean value and standard deviation of the output parameter due to circuit component variations is computed.
  • the resistance value that will drive the output parameter out of its tolerance range is computed and stored. Note that the resistance value which is obtained indicates the value of the resistance which, if added to the branch or circuit, will cause the output parameter to go out of its tolerance range. This resistance value will be used for test vector specification.
  • the following section describes an algorithm which uses the fault dictionary generation approach and fault dominance concept to derive the fault coverage and the test vector specification that detect the largest set of faults without targeting individual faults.
  • fault dominance is used to reduce the number of faults that need to be considered.
  • T g be the set of all tests that detects a fault g. Let's say that a fault / dominates a fault g if / and g are equivalent under T g .
  • any test that detects g will also detect / (on the same primary output). Therefore, for fault detection it is unnecessary to consider the dominating fault /, since by deriving a test to detect g we automatically obtain a test that detect / as well.
  • Step 31 A set of stimuli is selected.
  • a default stimulus could be used or it can be made by the test engineers in an interactive mode in order to consider any special characteristic of a circuit.
  • Stimuli are divided into DC, AC and transient stimuli [Majoj Sachdev, "A Realistic
  • Step 32 A stimulus T is selected from the set of stimuli of step
  • Step 33 A fault is selected from a fault list 48 constructed by the algorithm of Figure 7.
  • Step 34 is responsive to the selected stimulus from step 32 and the fault selected in step 33 to obtain a value of
  • Step 35 determines whether the fault is an open or a short.
  • Steps 36-40 - If the fault is an open (step 35) and R fau fry ⁇ R ca , (step 36; Table 1 presents a list of circuit defects and the corresponding typical resistance range obtained by statistical analysis of circuit defects [R.J.A. Harvey, A.M.D. Richardson, E.M.J.G. Bruls, K. Baker, "Analog
  • the fault is removed from the fault list (step 39) and the fault is marked as being detected by simulus T (step 40). Then, it is concluded that R fau , t (or higher resistance value) will cause the output parameter to deviate out of tolerance and the simulus T is accepted as a valid test vector; and
  • step 35 if the fault is a short (step 35) and R fau fry ⁇ F ⁇ yp ⁇ ca , (step 37), the fault is marked as being undetected by simulus T (step 38). Then, it is concluded that no deviation of the output parameter could be detected and the stimulus T is rejected as a valid test vector.
  • Step 41 In this step, the algorithm is returned to step 33 until all faults in the fault list have not been processed for a given stimulus T.
  • Step 42 In this step, the algorithm is returned to step 32 as long as all the stimuli of the set selected in step 31 have not been processed.
  • Step 43 The fault coverage is printed; this is a list of faults that can be detected by the set of stimuli selected in step 31.
  • Step 44 The test vectors are printed; this constitutes the test vector specification.
  • Step 45 The test algorithm is terminated.
  • the fault values R fau ⁇ corresponding to all the stimuli and all the faults are compared with typical values for shorts and opens (Table 1). More specifically, all the stimuli are evaluated for each fault; this iteration loop enables specification of test vectors that maximizes the observability of the fault.
  • Example 1 (second order band-pass filter of Figure 9):
  • t for open Rg, open R2, and open R3 was lower than R ⁇ , ⁇ and the test vector (10KHz sine wave) was marked as a valid test vector.
  • R fau , t was lower than R ⁇ , ⁇ and the test vector was rejected as a non-valid test vector for this fault.
  • each fault was reinjected manually into the circuit and simulated.
  • Figure 11 shows the results of the fault simulation over the considered catastrophic defects.
  • each fault is analysed to confirm whether or not it was detected at the output node at the 10KHz test frequency. Indeed, all the accepted resistances modified the signature of the fault-free output voltage by more than 5% which has been determined as a detection criteria.
  • Example 2 Fifth order chebychev filter of Figure 12
  • the fifth order chebychev filter of Figure 12 has been tested for 25 possible hard faults.
  • the set of stimuli T was selected as the frequency range 0-20kHz.
  • the detection threshold was set to 5% of the nominal output voltage, R typ ⁇ ca ⁇ for open set to 1 M ⁇ , and J ⁇ ⁇ ca , for shorts set to 1 k ⁇ .
  • the obtained fault coverage is 96% with only 5 test vectors (0Hz, 100Hz, 200Hz, 300Hz, 1 KHz).
  • a set of 7 benchmark circuits were simulated.
  • the benchmark circuits ranged from a simple operational amplifier to a complex 8 bit current DAC (digital-to-analog converter).
  • Level 3 Level 28 and level 49 transistor MOSFET models were used in the sensitivity computation environment.
  • the average fault coverage was 90% with small CPU cost. There was no way to compare the fault coverage and the simulation time with other publications due to the large variety of analog benchmarks.
  • Figure 13 presents the fault coverage as function of the number of test vectors, for an inverter, a low pass filter, a state variable filter, a chebychev filter, a 4-bit analog-to-digital converter, an 8-bit analog-to-digital converter flash, and an 8-bit current digital-to-analog converter.

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Abstract

Selon un procédé permettant d'élaborer un dictionnaire de pannes, on commence par décrire le circuit. On extrait une liste de pannes de ladite description, puis on calcule la distribution d'un circuit exempt de panne pour un paramètre de sortie dudit circuit en réponse à la description. On calcule la distribution d'un circuit en panne pour le paramètre de sortie en réponse aux pannes de la liste, puis une valeur de panne à partir des distributions de circuit exempt de panne et de circuit en panne. On met en mémoire la valeur de panne calculée dans le dictionnaire de pannes, dans le but de spécifier ultérieurement un vecteur d'essai qui sera appliqué au circuit pour le tester. Afin de spécifier des vecteurs d'essai pour tester un circuit donné, (a) on sélectionne une série de stimuli; (b) on sélectionne un stimulus dans ladite série; (c) on sélectionne une panne dans la liste de pannes; (d) on cherche, dans un dictionnaire de pannes, une valeur de panne reliée à la panne et au stimulus sélectionnés; (e) on compare la valeur de panne trouvée à l'étape (d) à une valeur de panne typique; (f) on détermine si la panne sélectionnée est détectée ou non détectée en appliquant le stimulus sélectionné au circuit qui présente la panne sélectionnée, en fonction du résultat de la comparaison de l'étape (e); (g) on répète les étapes (b), (c), (d), (e) et (f) pour chaque paire de stimulus et de panne; et (h) on construit des vecteurs d'essai à partir des stimuli de la série la plus susceptible de détecter des pannes dans le circuit.
PCT/CA1998/000538 1997-06-02 1998-06-02 Procede de simulation de panne et de specification d'essais en parallele pour circuits analogiques et numeriques WO1998055880A1 (fr)

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AU76345/98A AU7634598A (en) 1997-06-02 1998-06-02 Method for parallel analog and digital circuit fault simulation and test set specification
CA002269914A CA2269914A1 (fr) 1997-06-02 1998-06-02 Procede de simulation de panne et de specification d'essais en parallele pour circuits analogiques et numeriques

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CA 2206738 CA2206738A1 (fr) 1997-06-02 1997-06-02 Modelisation et simulation de defaillances pour systemes et circuits mixtes

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Cited By (9)

* Cited by examiner, † Cited by third party
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EP1212626A1 (fr) * 1999-05-19 2002-06-12 Georgia Tech Research Corporation Procede destine a tester des circuits
WO2003107019A2 (fr) * 2002-06-17 2003-12-24 University Of Strathclyde Systeme et procede numeriques d'essai de circuits ou de systemes a signaux analogiques et mixtes
US7185254B2 (en) 2000-06-08 2007-02-27 Advantest Corporation Method and apparatus for generating test patterns used in testing semiconductor integrated circuit
CN102520342A (zh) * 2011-12-07 2012-06-27 南京航空航天大学 基于动态反馈神经网络建模的模拟电路测试节点选择方法
CN104198922A (zh) * 2014-08-15 2014-12-10 电子科技大学 一种模拟电路早期故障诊断中的频率选择方法
WO2014204871A1 (fr) * 2013-06-19 2014-12-24 Dialog Semiconductor Inc. Pilote de del avec protections contre les contacts indirects complètes
US9641070B2 (en) 2014-06-11 2017-05-02 Allegro Microsystems, Llc Circuits and techniques for detecting an open pin condition of an integrated circuit
US10715169B1 (en) 2019-05-21 2020-07-14 Ciena Corporation Coarse-fine gain-tracking loop and method of operating
CN113900006A (zh) * 2021-08-26 2022-01-07 湖南艾科诺维科技有限公司 一种芯片故障测试装置、系统及方法

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CN103064009B (zh) * 2012-12-28 2015-03-11 辽宁大学 基于小波分析和有限高斯混合模型em方法的模拟电路故障诊断方法
US11463093B1 (en) 2021-05-12 2022-10-04 Ciena Corporation Reducing non-linearities of a phase rotator
US11750287B2 (en) 2021-05-25 2023-09-05 Ciena Corporation Optical DSP operating at half-baud rate with full data rate converters

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EP0568132A2 (fr) * 1992-04-30 1993-11-03 Schlumberger Technologies, Inc. Génération de test par émulation de l'environnement
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US4228537A (en) * 1978-08-29 1980-10-14 Genrad, Inc. Method of and apparatus for automatic fault diagnosis of electrical circuits employing on-line simulation of faults in such circuits during diagnosis
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Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1212626A4 (fr) * 1999-05-19 2006-05-24 Georgia Tech Res Inst Procede destine a tester des circuits
EP1212626A1 (fr) * 1999-05-19 2002-06-12 Georgia Tech Research Corporation Procede destine a tester des circuits
US7225377B2 (en) 2000-06-08 2007-05-29 Advantest Corporation Generating test patterns used in testing semiconductor integrated circuit
US7254764B2 (en) 2000-06-08 2007-08-07 Advantest Corporation Generating test patterns used in testing semiconductor integrated circuit
US7225378B2 (en) 2000-06-08 2007-05-29 Advantest Corporation Generating test patterns used in testing semiconductor integrated circuit
US7185254B2 (en) 2000-06-08 2007-02-27 Advantest Corporation Method and apparatus for generating test patterns used in testing semiconductor integrated circuit
US7174491B2 (en) 2002-06-17 2007-02-06 University Of Strathclyde Digital system and method for testing analogue and mixed-signal circuits or systems
WO2003107019A3 (fr) * 2002-06-17 2004-07-01 Univ Strathclyde Systeme et procede numeriques d'essai de circuits ou de systemes a signaux analogiques et mixtes
WO2003107019A2 (fr) * 2002-06-17 2003-12-24 University Of Strathclyde Systeme et procede numeriques d'essai de circuits ou de systemes a signaux analogiques et mixtes
CN102520342A (zh) * 2011-12-07 2012-06-27 南京航空航天大学 基于动态反馈神经网络建模的模拟电路测试节点选择方法
WO2014204871A1 (fr) * 2013-06-19 2014-12-24 Dialog Semiconductor Inc. Pilote de del avec protections contre les contacts indirects complètes
US9999110B2 (en) 2013-06-19 2018-06-12 Dialog Semiconductor Inc. LED driver with comprehensive fault protections
US10448480B2 (en) 2013-06-19 2019-10-15 Dialog Semiconductor Inc. LED driver with comprehensive fault protections
US9641070B2 (en) 2014-06-11 2017-05-02 Allegro Microsystems, Llc Circuits and techniques for detecting an open pin condition of an integrated circuit
CN104198922A (zh) * 2014-08-15 2014-12-10 电子科技大学 一种模拟电路早期故障诊断中的频率选择方法
CN104198922B (zh) * 2014-08-15 2017-02-01 电子科技大学 一种模拟电路早期故障诊断中的频率选择方法
US10715169B1 (en) 2019-05-21 2020-07-14 Ciena Corporation Coarse-fine gain-tracking loop and method of operating
CN113900006A (zh) * 2021-08-26 2022-01-07 湖南艾科诺维科技有限公司 一种芯片故障测试装置、系统及方法

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CA2206738A1 (fr) 1998-12-02

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