AU7634598A - Method for parallel analog and digital circuit fault simulation and test set specification - Google Patents

Method for parallel analog and digital circuit fault simulation and test set specification

Info

Publication number
AU7634598A
AU7634598A AU76345/98A AU7634598A AU7634598A AU 7634598 A AU7634598 A AU 7634598A AU 76345/98 A AU76345/98 A AU 76345/98A AU 7634598 A AU7634598 A AU 7634598A AU 7634598 A AU7634598 A AU 7634598A
Authority
AU
Australia
Prior art keywords
test set
digital circuit
circuit fault
fault simulation
parallel analog
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
AU76345/98A
Inventor
Naim Ben Hamida
Bozena Kaminska
Khaled Saab
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Opmaxx Inc
Original Assignee
Opmaxx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Opmaxx Inc filed Critical Opmaxx Inc
Publication of AU7634598A publication Critical patent/AU7634598A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2257—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using expert systems
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316—Testing of analog circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
AU76345/98A 1997-06-02 1998-06-02 Method for parallel analog and digital circuit fault simulation and test set specification Withdrawn AU7634598A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CA2206738 1997-06-02
CA 2206738 CA2206738A1 (en) 1997-06-02 1997-06-02 Fault modeling and simulation for mixed-signal circuits and systems
PCT/CA1998/000538 WO1998055880A1 (en) 1997-06-02 1998-06-02 Method for parallel analog and digital circuit fault simulation and test set specification

Publications (1)

Publication Number Publication Date
AU7634598A true AU7634598A (en) 1998-12-21

Family

ID=4160797

Family Applications (1)

Application Number Title Priority Date Filing Date
AU76345/98A Withdrawn AU7634598A (en) 1997-06-02 1998-06-02 Method for parallel analog and digital circuit fault simulation and test set specification

Country Status (3)

Country Link
AU (1) AU7634598A (en)
CA (1) CA2206738A1 (en)
WO (1) WO1998055880A1 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000070358A1 (en) * 1999-05-19 2000-11-23 Georgia Tech Research Corporation Method for testing circuits
JP4488595B2 (en) 2000-06-08 2010-06-23 株式会社アドバンテスト Test pattern generation method
GB0213882D0 (en) * 2002-06-17 2002-07-31 Univ Strathclyde A digital system & method for testing analogue & mixed-signal circuits or systems
CN102520342B (en) * 2011-12-07 2013-11-06 南京航空航天大学 Analog circuit test node selecting method based on dynamic feedback neural network modeling
CN103064009B (en) * 2012-12-28 2015-03-11 辽宁大学 Artificial circuit fault diagnosis method based on wavelet analysis and limited gauss mixed model expectation maximization (EM) method
WO2014204871A1 (en) 2013-06-19 2014-12-24 Dialog Semiconductor Inc. Led driver with comprehensive fault protections
US9641070B2 (en) 2014-06-11 2017-05-02 Allegro Microsystems, Llc Circuits and techniques for detecting an open pin condition of an integrated circuit
CN104198922B (en) * 2014-08-15 2017-02-01 电子科技大学 Frequency selection method in early fault diagnosis of analog circuit
US10715169B1 (en) 2019-05-21 2020-07-14 Ciena Corporation Coarse-fine gain-tracking loop and method of operating
US11463093B1 (en) 2021-05-12 2022-10-04 Ciena Corporation Reducing non-linearities of a phase rotator
US11750287B2 (en) 2021-05-25 2023-09-05 Ciena Corporation Optical DSP operating at half-baud rate with full data rate converters
CN113900006A (en) * 2021-08-26 2022-01-07 湖南艾科诺维科技有限公司 Chip fault testing device, system and method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5016618B1 (en) * 1969-02-12 1975-06-14
US4228537A (en) * 1978-08-29 1980-10-14 Genrad, Inc. Method of and apparatus for automatic fault diagnosis of electrical circuits employing on-line simulation of faults in such circuits during diagnosis
US5475624A (en) * 1992-04-30 1995-12-12 Schlumberger Technologies, Inc. Test generation by environment emulation
US5390193A (en) * 1992-10-28 1995-02-14 Motorola, Inc. Test pattern generation

Also Published As

Publication number Publication date
WO1998055880A1 (en) 1998-12-10
CA2206738A1 (en) 1998-12-02

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