WO1998054893A2 - Systeme d'egalisation de signaux video - Google Patents

Systeme d'egalisation de signaux video Download PDF

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Publication number
WO1998054893A2
WO1998054893A2 PCT/US1998/010768 US9810768W WO9854893A2 WO 1998054893 A2 WO1998054893 A2 WO 1998054893A2 US 9810768 W US9810768 W US 9810768W WO 9854893 A2 WO9854893 A2 WO 9854893A2
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WO
WIPO (PCT)
Prior art keywords
coupled
varactor diode
amplifier
capacitor
resistor
Prior art date
Application number
PCT/US1998/010768
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English (en)
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WO1998054893A9 (fr
WO1998054893A3 (fr
Inventor
Robert V. Seifert
Walter J. Schneider
Danny L. Beasley
Original Assignee
Apex Inc.
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Filing date
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Application filed by Apex Inc. filed Critical Apex Inc.
Priority to AU76014/98A priority Critical patent/AU7601498A/en
Publication of WO1998054893A2 publication Critical patent/WO1998054893A2/fr
Publication of WO1998054893A9 publication Critical patent/WO1998054893A9/fr
Publication of WO1998054893A3 publication Critical patent/WO1998054893A3/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/24—Frequency-independent attenuators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/04—Control of transmission; Equalising
    • H04B3/14—Control of transmission; Equalising characterised by the equalising network used
    • H04B3/143—Control of transmission; Equalising characterised by the equalising network used using amplitude-frequency equalisers
    • H04B3/145—Control of transmission; Equalising characterised by the equalising network used using amplitude-frequency equalisers variable equalisers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/10—Adaptations for transmission by electrical cable
    • H04N7/102—Circuits therefor, e.g. noise reducers, equalisers, amplifiers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/10—Adaptations for transmission by electrical cable
    • H04N7/108—Adaptations for transmission by electrical cable the cable being constituted by a pair of wires

Definitions

  • the present invention relates to computer systems in general, and in particular to systems for transmitting high-frequency signals over twisted wire cables.
  • the most common way of transmitting video signals to a remote location is over a set of twisted wire cables. These cables have the advantage of being relatively inexpensive and are commonly found in many office or factory environments.
  • One of the problems with twisted wire cables is the loss that occurs at high frequencies. In typical video signals, bandwidths up to 100 MHz are required to transmit high resolution video images. However, at such frequencies, much of the high-frequency components of the video signals transmitted on a twisted wire cable are lost or attenuated.
  • the loss versus frequency for twisted wire cables is generally non-linear and also vary depending upon the length and type of cable used.
  • the present invention comprises an equalization network that receives high-frequency signals on a twisted wire cable.
  • a differential amplifier converts a differential signal that is transmitted on a twisted wire cable into a single-ended signal.
  • This single- ended signal is applied to a plurality of equalizing networks, each of which is tunable for a range of cable lengths.
  • Each equalizing network comprises a non-inverting amplifier and a variable impedance placed in a feedback path of the amplifier.
  • the variable impedance preferably comprises a varactor diode that changes capacitance in proportion to a reverse bias DC voltage applied across the diode.
  • a digital-to-analog converter is coupled through a buffer amplifier to the varactor diodes in order to control the reverse bias DC voltage applied to each diode.
  • the digital values written to each of the digital-to-analog converters is controlled by a microprocessor in accordance with the length of twisted wire cable to be compensated.
  • FIGURE 1 illustrates a computer system and a remote workstation that are connected together via a length of twisted wire cable on which high-frequency signals are transmitted;
  • FIGURE 2 is a block diagram of an equalization network according to the present invention.
  • FIGURES 3A-3C are more detailed schematic diagrams of the equalization networks according to the present invention.
  • FIGURE 4 is a detailed schematic diagram of an alternative embodiment of the equalization network according to the present invention. Detailed Description of the Preferred Embodiment
  • the present invention is a system for compensating for high-frequency losses in twisted wire cables.
  • the system is particularly useful for recovering video signals transmitted on twisted wire cables up to 600 feet in length.
  • FIGURE 1 illustrates a typical environment where it is desirable to transmit video signals on a twisted pair cable.
  • a computer system 10 includes a central processing unit 12, keyboard 14, mouse 16, and video monitor 18.
  • the computer system 10 may be used for a variety of tasks such as controlling a local area network or operating as an Internet gateway, etc.
  • the computer system 10 is located in an environment that is not particularly suited for human operators. For example, the environment may be heavily air-conditioned, or crowded with other computer systems.
  • the workstation 30 generally includes a video monitor 32, keyboard 34, and mouse 36. Commands typed on the keyboard 34 or movements of the mouse 36 operate the remote computer system 10 as if they had been typed on the computer's own keyboard 14, or created by moving the mouse 16.
  • the video monitor 32 at the workstation displays the same image that is displayed on the video monitor 18 of the remote computer system. Key strokes entered on the keyboard 34 commands, or movements of the mouse 36 are collected and converted into a format suitable for transmission over a communication link by a signal conditioning unit 40.
  • the keyboard and mouse commands are transmitted over the communication link 42 where they are received by a local signal conditioning unit 44 that converts the keyboard and mouse commands back into their original form and applies them to the computer system 10.
  • Video signals produced by the computer system 10 are received by the local signal conditioning unit 44 and transmitted over the communication link 42 to the signal conditioning unit 40.
  • the signal conditioning unit 40 conditions the video signals and delivers them to the video monitor 32.
  • a commercially available system for connecting a workstation to a remote computer is the SWITCHBACK® product available from Apex PC Solutions, Inc., of Woodinville, Washington, the assignee of the present invention.
  • SWITCHBACK® product available from Apex PC Solutions, Inc., of Woodinville, Washington, the assignee of the present invention.
  • further descriptions of the signal conditioning units 40 and 44 can be found in U.S. Patent Application Serial No. 08/519,193 or PCT US96/13772, which are herein incorporated by reference.
  • the most common type of communication link 42 for connecting remotely located computers are one or more twisted wire cables. These cables are commonly used for Ethernet or token ring-type local area or wide area networks. As discussed above, the problem with twisted wire cables is the signal loss that occurs at high frequencies. For example, in a Category 5 twisted wire cable, a 100 MHz signal is attenuated by a factor of 30 when transmitted over a length of 500 feet. In order to successfully recover video signals transmitted over these types of cables, the signal loss must be recovered. In addition, it is important that the amplitude of the recovered signal remain within +/-1 dB for all its frequency components.
  • FIGURE 2 illustrates a block diagram of an equalization circuit 50 that recovers high-frequency signals that are lost due to the attenuation that occurs in a twisted wire cable.
  • the equalization circuit 50 is located within the signal conditioning unit 40 shown in FIGURE 1 and operates to increase the amplitude of the high-frequency components of video signals that are transmitted from the remote computer system.
  • the present invention is described with respect to recovering video signals, those skilled in the art will recognize that the equalization circuit is useful for recovering any high-frequency signal that is transmitted on a twisted wire cable.
  • an RGB color video signal comprises separate red, green, and blue video components. Each of these components is typically transmitted on its own twisted wire cable.
  • the horizontal and vertical synchronize signals can be transmitted on separate twisted wire cables or can be mixed in with any of the red, green, or blue video signals as described in U.S. Patent Application Serial No. 08/519,193, referenced above.
  • the equalization circuit for the red video signal is discussed. However, identical circuits are also provided to equalize the blue and green video signals.
  • a twisted wire cable generally comprises a first and second copper wire 102, 104 that are twisted around each other.
  • the video signal is transmitted on one of the wires while the inverse of the video signal is transmitted on the other wire. Assuming that the cable and receiving circuitry are properly balanced, the magnetic field created by the video signal is substantially canceled by the inverse video signal transmitted on the other wire in order to reduce cross-talk with neighboring twisted wire cables.
  • the wire 102 is connected into a non-inverting input of a differential receiver 106 while the wire 104 is coupled to an inverting input of the differential receiver.
  • the differential receiver 106 preferably comprises a CLC 522 amplifier available from National Semiconductor of Denver, Colorado.
  • a 200 ohm resistor 108 is positioned between the non-inverting and inverting inputs of the differential receiver to control the input impedance of the receiver.
  • the gain of the differential amplifier 106 is nominally set to .615 and can be adjusted by applying a varying voltage to a gain control pin 107.
  • the voltage applied to pin 107 is controlled with an eight-bit digital-to-analog converter (not shown) that produces an output voltage of zero to five volts.
  • the output of the digital-to-analog converter feeds a buffer amplifier having a gain of .396 and a DC offset.
  • the output of the buffer amplifier is connected to the gain control pin 107.
  • the differential receiver 106 produces a single-ended video signal at its output 110.
  • the single-ended video signal is applied to an input of a number of equalizing networks 120a, 120b, and 120c.
  • Each equalizing network is designed for a range of twisted wire cable lengths.
  • the equalizing network 120a is designed for cable lengths between 300 and 600 feet.
  • the equalizing network 120b is designed for cable lengths between 150 and 250 feet while the equalizing network 120c is designed for cable lengths between zero and 100 feet.
  • only one of the equalizing networks 120a, 120b, or 120c is activated at a given time.
  • the equalizing network 120a generally comprises an operational amplifier 130 that is part of a non-inverting gain circuit.
  • the low-frequency gain of the operational amplifier is generally determined by the ratio of a pair of fixed resistors 132 and 134.
  • the resistor 132 is connected between an output of the amplifier 130 and an inverting input of the amplifier.
  • the fixed resistor 134 is connected between the inverting input of the amplifier 130 and ground.
  • variable impedance is also connected between the inverting input of the operational amplifier 130 and ground.
  • the variable impedance comprises a resistor 136 having one terminal coupled to the inverting terminal of the operational amplifier 130. Coupled in series with the resistor 136 is a fixed capacitor 138 and coupled in series between the capacitor 138 and ground is a varactor diode 140.
  • the capacitance of the varactor diode 140 changes with the level of a reverse bias DC voltage that is applied to the diode. The higher the reverse bias voltage, the lower the capacitance.
  • the variable impedance defined by the resistor 136, fixed capacitor 138, and varactor diode 140 passes more current, thereby increasing the gain of the operational amplifier 130 to compensate for losses that occur in the twisted wire cable.
  • an eight-bit digital-to-analog converter 150 is provided.
  • a binary value written to the digital-to-analog converter 150 creates a voltage that is increased by an LM342 operation amplifier 152 having a gain of approximately 4.
  • the output of the amplifier 152 is coupled through a resistor to the cathode of the varactor diode 140.
  • the particular reverse bias voltage applied to the varactor diode 140 is dependent upon the length of cable that extends between the workstation and the remote computer.
  • a microprocessor 170 that is contained within the signal conditioning unit 40 shown in FIGURE 1 writes binary data to a series of digital-to-analog converters 150a, 150b, 150c and 150d.
  • Each of these digital-to-analog converters produces a variable DC voltage on a set of lines, CTRL0, CTRL1, CTRL2 and CTRL3.
  • the microprocessor is programmed to prompt the user for the approximate length of the twisted wire cable currently in use.
  • the microprocessor uses a look-up table to determine the correct binary value that should be written to the digital-to-analog converters 150a-150d in order to apply the proper reverse bias voltage to the varactor diodes. 98/54893
  • one of the equalization circuits 120a, 120b, or 120c is activated depending upon the length of twisted wire cable to be compensated.
  • the activation is performed by placing the appropriate logic signal on an enable pin 152 of the operational amplifier 130. By enabling this pin, the output of the amplifier is taken out of a high impedance state.
  • two of the amplifiers associated with the equalization circuits 120a, 120b, or 120c are in a high impedance state while one amplifier is enabled.
  • the output of the amplifiers in each of the equalization circuits are fed through a 10 ohm resistor and joined at a common node 160 where they are fed to a buffer amplifier.
  • the output of the buffer amplifier is sent to the appropriate input of a color monitor.
  • FIGURE 3 A shows in greater detail the equalization circuit 120a that is designed to compensate for attenuation in twisted wire cables having lengths between approximately 300 and 600 feet.
  • the single-ended video signal produced by the output of the differential amplifier 106, shown in FIGURE 2, is coupled to a non-inverting input of an operational amplifier U Q .
  • a 301 ohm resistor R62 is coupled between an inverting input of the amplifier U 0 and an output of the amplifier.
  • a 2 K ohm resistor R61 is also disposed between the inverting input of the amplifier Uo and ground.
  • a variable impedance network that comprises a 10 ohm resistor R41, a 0.01 microfarad capacitor C39 and a BB640 varactor diode Dl.
  • the resistor R41 is disposed between the inverting input of the amplifier U 0 and a lead on the capacitor C39.
  • the varactor diode Dl is coupled between another lead of the capacitor C39 and ground.
  • a variable reverse bias DC voltage is applied to the cathode of the varactor diode Dl .
  • the reverse bias voltage is supplied on the CTRLO lead from the digital-to-analog converter 150a which is controlled by the microprocessor 170.
  • the output of the digital-to-analog converter 150a is amplified by a buffer amplifier 152 (FIGURE 1).
  • the voltage on the CTRLO lead is coupled through a 100 K ohm resistor R39 that is connected between the buffer amplifier and the junction of the capacitor C39 and the varactor diode D 1.
  • a second variable impedance comprising a 499 ohm resistor R40, a 56 picofarad capacitor C32 and a BB512 varactor diode D2 is also coupled to the amplifier U Q .
  • One lead of the resistor R40 is coupled to the junction of the resistor R41 and the capacitor C39.
  • the other lead of the resistor R40 is coupled to the capacitor C32.
  • the cathode of the varactor diode D2 is coupled to the other lead 98/54893
  • the reverse bias voltage for the varactor diode D2 is supplied on the CTRL1 lead through a 100 K ohm resistor R28 to the junction of the cathode of the varactor diode D2 and the capacitor C32.
  • the output of amplifier U Q is coupled through a 49.9 ohm resistor R63 to a non-inverting input of a tri-stateable amplifier Ul. Disposed between the output of the amplifier Ul and an inverting input of the amplifier is a 301 ohm resistor R44. Disposed between the non-inverting input of the amplifier Ul and ground is a 4.99 K ohm resistor R43.
  • a variable impedance comprising a 200 ohm resistor R42, a 33 picofarad capacitor C35 and a BB512 varactor diode D4 is also coupled to the inverting input of the amplifier Ul .
  • the resistor R42 is coupled between the inverting input of the amplifier and a lead of the capacitor of the C35.
  • the other lead of the capacitor C35 is coupled to the cathode of the varactor diode D4, while the anode of the varactor D4 is grounded.
  • the reverse bias voltage for the diode D4 is supplied on a CTRL2 lead through a 100 K ohm resistor R31 to the junction of capacitor C35 and the cathode of the varactor diode D4.
  • the equalization circuit 120a also includes another variable impedance comprising a I K ohm resistor R30, a 180 picofarad capacitor C34 and a BB512 varactor diode D3.
  • One lead of the resistor R30 is connected to the junction of the resistor R42 and the capacitor C35.
  • Another lead of the resistor R30 is coupled to a lead of the capacitor C34, while the other lead of capacitor C34 is coupled to the cathode of the varactor diode D3.
  • the anode of the varactor diode D3 is grounded.
  • the reverse bias voltage for the varactor diode is supplied on a CTRL3 lead through a 100 K ohm resistor R29 to the junction of the capacitor C34 and the varactor diode D3.
  • the output of the amplifier Ul is fed through a 10 ohm resistor R45 to the node 160 (shown in FIGURE 2) where it combines with the outputs of the other equalization circuits 120b, and 120c.
  • the tri-stateable amplifier Ul can be placed in a high impedance state by placing the appropriate logic signal on a control lead Kl. When this lead is active low, the amplifier Ul is enabled.
  • the particular reverse bias voltages applied to the varactor diodes Dl, D2, D3, and D4, in order to compensate for signal losses in cables of 300-600 feet is set forth below.
  • FIGURE 3B illustrates the equalization circuit 120b used to compensate for attenuation occurring in twisted wire cables having lengths between 150 and 250 feet.
  • the single-ended signal produced by the differential receiver 106 shown in FIGURE 2 is coupled through a 121 ohm resistor R64 to a non-inverting input of a tri-stateable operational amplifier U2.
  • a 301 ohm resistor R66 Disposed between an output of the amplifier U2 and an inverting input is a 301 ohm resistor R66.
  • Also coupled between the inverting input of the amplifier U2 and ground is a 4.99 K ohm resistor R71.
  • a plurality of variable impedances are provided.
  • the first variable impedance comprises a 54.9 ohm resistor R69 that is coupled between the inverting input of the amplifier U2 and a 39 picofarad capacitor C43.
  • the other lead of the capacitor C43 is coupled to a cathode of a BB640 varactor diode D5.
  • An anode of the diode D5 is coupled to a collector terminal of an NPN transistor Ql.
  • a 2 K ohm resistor R50 couples a logic signal MIDO to a base terminal of the transistor.
  • the MIDO signal is set by a latching circuit 165 (FIGURE 2) that is controlled by the microprocessor 170.
  • the reverse bias voltage on the diode D5 is supplied on a CTRLO line through a 100 K ohm resistor R46 that is coupled to the junction of the capacitor C43 and the cathode of varactor diode D5.
  • a second variable impedance comprises a 75 ohm resistor R70, a 15 picofarad capacitor C44, a BB639 varactor diode D6, and a transistor Q2.
  • a lead of the resistor R70 is coupled to the junction of the resistor R69 and the capacitor C43.
  • Another lead of the resistor R70 is coupled to a lead of the capacitor C44.
  • a cathode of the varactor diode D6 is coupled to the other lead of the capacitor C44 while the anode of the varactor diode D6 is coupled to the collector terminal of the transistor Q2.
  • a logic signal MIDI is coupled through a 2 K ohm resistor R34 to a base terminal of the transistor Q2. The emitter terminal of the transistor Q2 is grounded.
  • the reverse bias voltage applied to the cathode of diode D6 is also supplied on the CTRLO line through a 100 K ohm resistor R47 that is connected to the junction of capacitor C44 and the cathode of the varactor diode D6.
  • a third variable impedance comprises a 100 ohm resistor R72, a 27 picofarad capacitor C45, and a BB640 varactor diode D7.
  • a lead of the resistor R72 is coupled to the junction of resistor R70 and capacitor C44, while another lead of the resistor R72 is coupled to a lead of capacitor C45.
  • a cathode of the varactor diode D7 is coupled to the other lead of the capacitor C45, while the anode of the varactor diode D7 is grounded.
  • a fourth variable impedance comprises a 301 ohm resistor R73, a 39 picofarad capacitor C50, and a BB512 varactor diode D8.
  • a lead of the resistor R73 is coupled to the junction of resistor R72 and capacitor C45.
  • Another lead of resistor R73 is coupled to a lead of the capacitor C50.
  • the other lead of capacitor C50 is coupled to the cathode of the varactor diode D8.
  • a fifth variable impedance comprising a 1.5 K ohm resistor R74, a 100 picofarad capacitor C59, and a BB512 varactor diode Dl l is included in the equalization circuit 120b.
  • a lead of the resistor R74 is coupled to the junction of the resistor R73 and the capacitor C50.
  • Another lead of the resistor R74 is coupled to a lead the capacitor C59.
  • the other lead of the capacitor C59 is coupled to the cathode of the varactor diode Dl l, while the anode of the varactor diode Dl l is grounded.
  • the reverse bias voltage applied to the varactor diode Dl 1 is supplied on the CTRL3 line through a 100 K ohm resistor R92 that is coupled to the junction of the capacitor C59 and the cathode of varactor diode Dl l.
  • the tri-stateable amplifier U2' is set in either its high impedance or active state by applying an appropriate logic signal on a control pin K2.
  • FIGURE 3C shows in greater detail the equalization circuit 120c that is used to recover video signals that are attenuated in twisted wire cables having lengths up to 100 feet.
  • the single-ended video signal produced by the output of the differential receiver 106 shown in FIGURE 2 is applied through a 100 ohm resistor R82 into a non-inverting terminal of a tri-stateable operational amplifier U3. Also coupled between the non-inverting input and ground is a 124 ohm resistor R83. Disposed between an output of the amplifier U3 and an inverting input is a 499 ohm resistor R68. A 332 ohm resistor R85 is coupled between the non-inverting input and ground.
  • a variable impedance comprising a 130 ohm resistor R84, an 18 picofarad capacitor C55, a BB640 varactor diode D9, and an NPN transistor Q3 are provided.
  • a lead of the resistor R84 is coupled to the inverting input of the amplifier U3, while another lead of the resistor R84 is coupled to a lead of the capacitor C55.
  • the cathode of varactor diode D9 is coupled to the other lead of capacitor C55, while the anode of varactor diode D9 is coupled to a collector terminal of the transistor Q3.
  • the emitter terminal of transistor Q3 is grounded.
  • the transistor Q3 is activated by a LOWO logic signal which is applied through a 2 K ohm resistor R75 to a base terminal of the transistor Q3.
  • the reverse bias voltage applied to the varactor diode D9 is supplied on the CTRLO line through a 100 K ohm resistor R86 that is coupled to the junction of the capacitor C55 and the cathode of the varactor diode D9.
  • Another variable impedance comprises a 301 ohm resistor R88, a 33 picofarad capacitor C57, and a BB640 varactor diode D16.
  • a lead of the resistor R88 is coupled to the junction of resistor R84 and capacitor C55.
  • Another lead of resistor R88 is coupled to a lead of the capacitor C57.
  • the other lead of capacitor C57 is coupled to the cathode of varactor diode D16.
  • the anode of varactor diode D16 is coupled to a collector terminal of an NPN transistor Q4 while an emitter terminal of the transistor is grounded.
  • the reverse bias voltage applied to the varactor diode D16 is supplied on the CTRLl line through a 100 K ohm resistor R102 that is coupled to the junction of capacitor C57 and varactor diode D16.
  • the last variable impedance included in the equalization circuit 120c comprises a 1 K ohm resistor R89, a 120 picofarad capacitor C56, and a BB512 varactor diode D10.
  • a lead of the resistor R89 is coupled to the junction of the resistor R88 and the capacitor C57.
  • Another lead of the resistor R89 is coupled to a lead of the capacitor C56.
  • the cathode of the varactor diode D10 is coupled the other lead of the capacitor C56.
  • the anode of varactor diode D10 is also coupled to the collector terminal of the transistor Q4.
  • the transistor Q4 is driven by the LOW1 logic signal which is applied through a 2 K ohm resistor R35 to a base terminal of the transistor Q4.
  • the equalization circuit 120c is activated by placing an appropriate logic signal on an enable pin K3 of the tri-stateable amplifier U3.
  • each equalization circuits 120a, 120b, and 120c are selectively enabled and the varactor diodes of the circuits are supplied with the appropriate reverse bias voltages to compensate for signal losses that occur in the twisted pair lines.
  • the following table defines the reverse bias voltage to be supplied on the CTRLO, CTRLl, CTRL2, and CTRL3 lines for Category 5 twisted wire cables having lengths between 25 and 600 feet.
  • the values listed in the table are set forth in base 16. These values can be converted to absolute voltages produced at the output of the buffer amplifiers by converting the number listed to base 10, and multiplying by approximately 0.0758. 98/54893
  • the following table describes the logic used to enable the various tri-stateable operational amplifiers in each of the equalization circuits 120a, 120b, and 120c as well as the logic levels to be applied to the transistors in the equalization circuits.
  • a 0 in the table indicates a logic low signal, while a 1 indicates a logic high signal, and an X indicates a don't care condition.
  • These logic levels are set by the latch circuit 165 shown in FIGURE 2, where the Ul line enables the amplifier Ul, the U2 line enables the amplifier U2 and the U3 line enables the amplifier U3.
  • FIGURE 4 illustrates an alternative, and currently preferred, equalization network according to the present invention.
  • the equalization network shown in FIGURE 4 is similar in operation to the equalization networks described above and shown in FIGURES 3A-3C but contains fewer components and can fit on a smaller printed circuit board.
  • the equalization network comprises a differential receiver 206 that receives a video signal on a twisted wire pair coupled to an inverting and noninverting input of the differential receiver. If need be, a transformer T3 can be placed in line with the video signals on the twisted wire cable to remove any common mode noise signals.
  • a 100 ohm resistor R124 is coupled between the inverting and noninverting input of the differential receiver 206.
  • a pair of 10 K ohm resistors R123 and R125 are coupled from the inverting and noninverting inputs to ground in order to control the input impedance of the differential amplifier.
  • the gain of the differential amplifier is set by a 787 ohm resistor R150 placed between pins 10 and 12, and a 464 ohm resistor R128 placed between pins 4 and 5.
  • the DC gain of the differential receiver 206 can be adjusted by varying the DC voltage on pin 2.
  • the single-ended video signal produced at the output of the differential receiver 206 is applied to an operational amplifier U4 that is connected in a noninverting configuration.
  • the single-ended video signal is applied to a noninverting input of the amplifier U4.
  • the DC gain of the amplifier is set by a 301 ohm resistor R173 coupled between an output of the amplifier and the inverting input.
  • a 4.99 K ohm resistor R160 is coupled between the inverting input and ground.
  • the amplifier U4 includes several variable impedances that are connected in the feedback loop of the amplifier.
  • the first variable impedance comprises a 10 ohm resistor R178, a 100 picofarad capacitor C165, a BB512 varactor diode D14, and an NPN transistor Q16.
  • One lead of the resistor R178 is connected to the inverting input of the amplifier U4.
  • the other lead of the resistor R178 is coupled to a lead of the 100 picofarad capacitor C165.
  • the other lead of the capacitor C 165 is coupled to the cathode of a BB512 varactor diode D14.
  • the anode of the diode D14 is coupled to a collector terminal of the NPN transistor Q16.
  • Transistor Q16 is turned on by placing the appropriate digital voltage signal on a BOOST0 lead which is coupled to the base terminal of the transistor Q16 through a 2 K ohm resistor R206.
  • a variable reverse bias voltage is supplied on a CTRLIO line through a 100 K ohm resistor R174 connected to the junction of capacitor C165 and the cathode of varactor diode D14.
  • a second variable impedance comprises a 499 ohm resistor R184, an 82 picofarad capacitor C179, a BB512 varactor diode D21 and an NPN transistor Q22.
  • One lead of the resistor R184 is coupled to the junction of resistor R178 and the capacitor C165.
  • the other lead of the resistor R184 is coupled to a lead of the capacitor C179.
  • the other lead of capacitor C 179 is coupled to a cathode of varactor diode D21, while the anode of varactor diode D21 is coupled to the collector terminal of transistor Q22.
  • the emitter terminal of transistor Q22 is grounded.
  • Transistor Q22 is turned on by an appropriate digital logic signal supplied on a BOOST3 lead, that is connected through a 2 K ohm resistor R238 to the base terminal of the transistor Q22.
  • a variable reverse bias voltage is supplied on a CTRL 13 line through a 100 K ohm resistor R218 that is coupled to the junction of capacitor C179 and the cathode of varactor diode D21.
  • a third variable impedance comprises a 1.5 K ohm resistor R205, a 180 picofarad capacitor C189, a BB512 varactor diode D24 and an NPN transistor Q31.
  • a lead of the resistor R205 is coupled to the junction of resistor Rl 84 and capacitor C179.
  • Another lead of resistor R205 is coupled to a lead of the capacitor C189.
  • the other lead of capacitor C 189 is coupled to the cathode of varactor diode D24, while the cathode of the varactor diode D24 is coupled to a collector terminal of transistor Q31.
  • the emitter terminal of transistor Q31 is grounded.
  • the transistor Q31 is turned on by supplying a digital logic signal on a BOOST5 line through a 2 K ohm resistor R246 that is coupled to a base terminal of the transistor Q31.
  • a variable reverse bias voltage is supplied to the varactor diode D24 on an LF10 line through a 100 K ohm resistor R231 that is coupled to the junction of capacitor C189 and the anode of varactor diode D24.
  • a 301 ohm resistor R157 is coupled between an inverting input of the amplifier U4 and a collector terminal of a transistor Q13. An emitter terminal of transistor Q13 is grounded.
  • the transistor is turned on by a digital logic signal applied on a BOOST6 line through a 2 K ohm resistor R151 that is coupled to a base terminal of the transistor Q13.
  • the output of the amplifier U4 is coupled through a 49.9 ohm resistor R172 to a noninverting input of an operational amplifier U5.
  • the amplifier is connected in a noninverting configuration with a 301 ohm resistor R193 coupled between an output of the amplifier and an inverting input.
  • Connected between the inverting input and ground is a 4.99 K ohm resistor R204.
  • a first variable impedance comprises a 10 ohm resistor R203, a 10 picofarad capacitor C186, a BB640 varactor diode D20 and an NPN transistor Q26.
  • One lead of the resistor R203 is coupled to an inverting input of the amplifier U5. Another lead of the resistor R203 is coupled to a lead of the capacitor C 186.
  • the other lead of capacitor C 186 is coupled to the cathode of the varactor diode D20, while the anode of diode D20 is coupled to a collector terminal of the transistor Q26.
  • the emitter terminal of transistor Q26 is grounded.
  • a variable reverse bias voltage is supplied on a CTRLl 1 lead through a 100 K ohm resistor R221 that is coupled to the junction of capacitor C186 and diode D20.
  • the transistor Q26 is turned on by a digital logic signal supplied on a BOOST 1 line through a 2 K ohm resistor R245 coupled to a base of the transistor Q26.
  • a second variable impedance comprises a 200 ohm resistor R212, a 33 picofarad capacitor C194, a BB640 varactor diode D27, and an NPN transistor Q30.
  • One lead of the resistor R212 is coupled to the junction of resistor R203 and capacitor C186.
  • the other lead of resistor R212 is coupled to a lead of the capacitor C194.
  • the other lead of capacitor C194 is coupled to the cathode of diode D27, while the anode of diode D27 is coupled to a collector terminal of the transistor Q30.
  • the emitter terminal of transistor Q30 is grounded.
  • a variable reverse bias voltage is supplied to the diode D27 on a CTRL 12 line through a 100 K ohm resistor R229, which is coupled to the junction of the capacitor C 194 and diode D27.
  • the transistor Q30 is turned on by a digital logic signal supplied on a BOOST2 line through a 2 K ohm resistor R249 that is coupled to a base terminal of the transistor Q30.
  • a third variable impedance comprises a 909 ohm resistor R217, a
  • a variable reverse bias voltage is supplied on an LF11 line through a 100 K ohm resistor R230 that is coupled to the junction of capacitor C195 and diode D30.
  • the transistor Q34 is turned on by a digital logic signal applied on a BOOST4 lead through a 2 K ohm resistor R250 coupled to a base terminal of the transistor Q34.
  • the output of the amplifier U5 is coupled through a 49.9 ohm resistor R171 to a buffer amplifier (not shown). The output of the buffer amplifier is sent to the appropriate input of a color monitor.
  • the following table defines the reverse bias DC voltages that are applied to the varactor diodes in order to compensate for various lengths of twisted wire cables.
  • the following table describes the logic used to enable the transistors to turn on the varactor diodes in each of the variable impedances to boost the gain of the amplifiers.
  • a 0 in the table indicates a logic low signal, while a 1 indicates a logic high signal, and an x indicates a don't care condition.
  • the logic signals are supplied by a latching circuit that is controlled by the microprocessor 170, shown in FIGURE 2.
  • the present invention allows high- frequency signals such as video signals to be transmitted on twisted wire cables up to 600 feet in length.
  • high- frequency signals such as video signals
  • twisted wire cables up to 600 feet in length.
  • additional lengths could be accommodated using the same techniques.
  • the loss curve of the twisted wire cables does not exhibit a simple slope with respect to frequency, numerous compensation stages must be provided to create a piecewise linear fit.
  • response curves that are flat to within ⁇ 1 dB up to 100 MHz or more can be obtained using Category 5 cable up to 600 feet in length.

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Networks Using Active Elements (AREA)
  • Picture Signal Circuits (AREA)

Abstract

L'invention concerne un système d'égalisation permettant de compenser l'atténuation de signaux de haute fréquence dans un câble à fils torsadés. Un circuit d'égalisation comporte un certain nombre d'amplificateurs opérationnels à impédance variable connectés dans une chaîne de retour. L'impédance variable comporte une diode varactor dont la capacité change avec la valeur d'une tension de polarisation inverse. La valeur de tension de polarisation inverse est commandée à l'aide d'un convertisseur numérique-analogique et d'un amplificateur de gain permettant d'accroître le gain des amplificateurs opérationnels à des fréquences élevées. Un microprocesseur sélectionne les tensions de polarisation inverse appropriées en fonction de la longueur du câble à fils torsadés devant être compensé.
PCT/US1998/010768 1997-05-30 1998-05-26 Systeme d'egalisation de signaux video WO1998054893A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU76014/98A AU7601498A (en) 1997-05-30 1998-05-26 Video signal equalization system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US86688897A 1997-05-30 1997-05-30
US08/866,888 1997-05-30

Publications (3)

Publication Number Publication Date
WO1998054893A2 true WO1998054893A2 (fr) 1998-12-03
WO1998054893A9 WO1998054893A9 (fr) 1999-04-01
WO1998054893A3 WO1998054893A3 (fr) 1999-06-17

Family

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AU (1) AU7601498A (fr)
WO (1) WO1998054893A2 (fr)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000042715A2 (fr) * 1999-01-12 2000-07-20 Adc Telecommunications, Inc. Egaliseur variable
EP1049327A2 (fr) * 1999-04-30 2000-11-02 General Electric Company Compensateur de longueur de cable variable pour des systèmes à imagerie vidéo
EP1061741A1 (fr) * 1999-06-11 2000-12-20 Dätwyler Ag Kabel + Systeme Système pour le câblage universel d'un bâtiment ou de plusieurs utilisateurs, les composants d'un tel système ainsi que le procédé correspondant
EP1474926A1 (fr) * 2002-02-15 2004-11-10 Avocent Corporation Egalisation automatique de signaux video
US6836184B1 (en) 1999-07-02 2004-12-28 Adc Telecommunications, Inc. Network amplifier with microprocessor control
CN105472293A (zh) * 2014-08-22 2016-04-06 浙江大华技术股份有限公司 一种实现视频信号均衡的方法及装置
US9743095B2 (en) 2002-10-01 2017-08-22 Avocent Corporation Video compression encoder
CN112655192A (zh) * 2018-09-13 2021-04-13 索尼公司 相机系统和线缆
CN114341667A (zh) * 2020-07-10 2022-04-12 深圳市速腾聚创科技有限公司 激光接收电路和激光雷达

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9560371B2 (en) 2003-07-30 2017-01-31 Avocent Corporation Video compression system

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EP0310237A2 (fr) * 1987-10-01 1989-04-05 International Control Automation Finance S.A. Circuits d'adaptation de ligne
US4888560A (en) * 1987-07-16 1989-12-19 Kabushiki Kaisha Toshiba Gain-variable amplifier circuit

Patent Citations (2)

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US4888560A (en) * 1987-07-16 1989-12-19 Kabushiki Kaisha Toshiba Gain-variable amplifier circuit
EP0310237A2 (fr) * 1987-10-01 1989-04-05 International Control Automation Finance S.A. Circuits d'adaptation de ligne

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000042715A3 (fr) * 1999-01-12 2001-04-05 Adc Telecommunications Inc Egaliseur variable
US6549087B1 (en) 1999-01-12 2003-04-15 Adc Telecommunications, Inc. Variable equalizer with independently controlled branches based on different frequency breakpoints
WO2000042715A2 (fr) * 1999-01-12 2000-07-20 Adc Telecommunications, Inc. Egaliseur variable
EP1049327A2 (fr) * 1999-04-30 2000-11-02 General Electric Company Compensateur de longueur de cable variable pour des systèmes à imagerie vidéo
EP1049327A3 (fr) * 1999-04-30 2002-08-14 General Electric Company Compensateur de longueur de cable variable pour des systèmes à imagerie vidéo
EP1061741A1 (fr) * 1999-06-11 2000-12-20 Dätwyler Ag Kabel + Systeme Système pour le câblage universel d'un bâtiment ou de plusieurs utilisateurs, les composants d'un tel système ainsi que le procédé correspondant
US6836184B1 (en) 1999-07-02 2004-12-28 Adc Telecommunications, Inc. Network amplifier with microprocessor control
EP1474926A4 (fr) * 2002-02-15 2010-08-18 Avocent Corp Egalisation automatique de signaux video
EP1474926A1 (fr) * 2002-02-15 2004-11-10 Avocent Corporation Egalisation automatique de signaux video
US9743095B2 (en) 2002-10-01 2017-08-22 Avocent Corporation Video compression encoder
CN105472293A (zh) * 2014-08-22 2016-04-06 浙江大华技术股份有限公司 一种实现视频信号均衡的方法及装置
CN112655192A (zh) * 2018-09-13 2021-04-13 索尼公司 相机系统和线缆
JPWO2020054266A1 (ja) * 2018-09-13 2021-08-30 ソニーグループ株式会社 カメラシステム、ケーブル
EP3852352A4 (fr) * 2018-09-13 2021-11-03 Sony Group Corporation Système de caméra et câbles
US11553125B2 (en) 2018-09-13 2023-01-10 Sony Corporation Camera system and cables
CN114341667A (zh) * 2020-07-10 2022-04-12 深圳市速腾聚创科技有限公司 激光接收电路和激光雷达
CN114341667B (zh) * 2020-07-10 2023-08-04 深圳市速腾聚创科技有限公司 激光接收电路和激光雷达

Also Published As

Publication number Publication date
AU7601498A (en) 1998-12-30
WO1998054893A9 (fr) 1999-04-01
WO1998054893A3 (fr) 1999-06-17

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