WO1998048355A3 - Method for transmitting an operating system in computer systems - Google Patents

Method for transmitting an operating system in computer systems Download PDF

Info

Publication number
WO1998048355A3
WO1998048355A3 PCT/DE1998/001071 DE9801071W WO9848355A3 WO 1998048355 A3 WO1998048355 A3 WO 1998048355A3 DE 9801071 W DE9801071 W DE 9801071W WO 9848355 A3 WO9848355 A3 WO 9848355A3
Authority
WO
WIPO (PCT)
Prior art keywords
operating system
real
address
hardware
gsp
Prior art date
Application number
PCT/DE1998/001071
Other languages
German (de)
French (fr)
Other versions
WO1998048355A2 (en
Inventor
Alfred Isele
Original Assignee
Siemens Nixdorf Inf Syst
Alfred Isele
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Nixdorf Inf Syst, Alfred Isele filed Critical Siemens Nixdorf Inf Syst
Priority to JP10544720A priority Critical patent/JP2000513128A/en
Priority to EP98931931A priority patent/EP0978042A2/en
Publication of WO1998048355A2 publication Critical patent/WO1998048355A2/en
Publication of WO1998048355A3 publication Critical patent/WO1998048355A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/109—Address translation for multiple virtual address spaces, e.g. segmentation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

The invention relates to a method enabling the use of an operating system (OS1) for source hardware (M1) supporting a real address mode, on target hardware (M2) supporting only a virtual address mode, while maintaining main memory address irrespective of configuration and process. This is achieved in that one of the virtual address spaces for process-independent addressing of the main memory (HS2) is reserved and, in accordance with the real address mode, used on the source hardware (M2). An upstream, separate control programme (GSP) enables the transferred operating system (OS2) to react to exceptional conditions (EV2) of the target hardware (M2), and the real addresses of the operating system that is to be transferred are imaged in the reserved address space on free addresses that are not occupied by the separate control programme (GSP) of the physical memory.
PCT/DE1998/001071 1997-04-23 1998-04-16 Method for transmitting an operating system in computer systems WO1998048355A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP10544720A JP2000513128A (en) 1997-04-23 1998-04-16 Operating system transfer method in data processing device
EP98931931A EP0978042A2 (en) 1997-04-23 1998-04-16 Method for transmitting an operating system in computer systems

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19717102.8 1997-04-23
DE19717102A DE19717102A1 (en) 1997-04-23 1997-04-23 Method for transferring an operating system in data processing systems

Publications (2)

Publication Number Publication Date
WO1998048355A2 WO1998048355A2 (en) 1998-10-29
WO1998048355A3 true WO1998048355A3 (en) 1999-01-28

Family

ID=7827471

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1998/001071 WO1998048355A2 (en) 1997-04-23 1998-04-16 Method for transmitting an operating system in computer systems

Country Status (4)

Country Link
EP (1) EP0978042A2 (en)
JP (1) JP2000513128A (en)
DE (1) DE19717102A1 (en)
WO (1) WO1998048355A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5038281A (en) * 1986-09-19 1991-08-06 International Business Machines Corporation Acceleration of system interrupts between operating systems in guest-host relationship
EP0645701A2 (en) * 1993-09-28 1995-03-29 Bull HN Information Systems Inc. Emulating the memory functions of a first system on a second system
US5479631A (en) * 1992-11-19 1995-12-26 International Business Machines Corporation System for designating real main storage addresses in instructions while dynamic address translation is on

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58102380A (en) * 1981-12-11 1983-06-17 Hitachi Ltd Virtual storage control system
JP2510605B2 (en) * 1987-07-24 1996-06-26 株式会社日立製作所 Virtual computer system
JP2839201B2 (en) * 1990-07-30 1998-12-16 株式会社日立製作所 Virtual computer system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5038281A (en) * 1986-09-19 1991-08-06 International Business Machines Corporation Acceleration of system interrupts between operating systems in guest-host relationship
US5479631A (en) * 1992-11-19 1995-12-26 International Business Machines Corporation System for designating real main storage addresses in instructions while dynamic address translation is on
EP0645701A2 (en) * 1993-09-28 1995-03-29 Bull HN Information Systems Inc. Emulating the memory functions of a first system on a second system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SHANG RONG TSAI ET AL: "ON THE ARCHITECTURAL SUPPORT FOR LOGICAL MACHINE SYSTEMS", MICROPROCESSING AND MICROPROGRAMMING, vol. 22, no. 2, 1 February 1988 (1988-02-01), pages 81 - 96, XP000284881 *

Also Published As

Publication number Publication date
DE19717102A1 (en) 1998-10-29
JP2000513128A (en) 2000-10-03
WO1998048355A2 (en) 1998-10-29
EP0978042A2 (en) 2000-02-09

Similar Documents

Publication Publication Date Title
CA2026224A1 (en) Apparatus for maintaining consistency in a multiprocess computer system using virtual caching
CA2245106A1 (en) Method and system for input/output control in a multiprocessor system utilizing simultaneous variable-width bus access
EP0747808A3 (en) Processor capable of supporting two distinct instruction set architectures
WO1998025196A3 (en) Dynamic branch prediction for branch instructions with multiple targets
GB2322209B (en) Computer system having shared address space among multiple virtual address spaces
AU2386400A (en) Recoverable methods and systems for processing input/output requests including virtual memory addresses
WO1998043176A8 (en) Shared reconfigurable memory architectures for digital signal processing
AU7595596A (en) Virtual memory system with local and global virtual address translation
HK1026316A1 (en) Method and system for data communication on the internet
AU3369497A (en) System for controlling access to a register mapped to an i/o address space of a computer system
WO1998055910A3 (en) Apparatus and method for secure device addressing
EP0843261A3 (en) Virtual channel memory system
CA2009779A1 (en) Uncoupling a central processing unit from its associated hardware for interaction with data handling apparatus alien to the operating system controlling said unit and hardware
EP0106668A3 (en) Computer system with multiple operating systems
AU7263496A (en) System for providing bios to host computer
NL185634C (en) COMPUTER SYSTEM AND METHOD OF ADDRESSING INDEPENDENT OF THE PROCESSING METHOD OF THE CENTRAL PROCESSING UNIT.
AU5148700A (en) Method for flashing a read only memory (rom) chip of a host adapter with updatedbios code
CA2050950A1 (en) Memory controller for direct or interleave memory accessing
TW325536B (en) Method and apparatus for accessing a register in a data processing system
CA2384254A1 (en) Fine grain translation discrimination
AU628548B2 (en) Method and apparatus for the direct transfer of information between application programs running on distinct processors without utilizing the services of one or both operating systems
EP0014581A3 (en) Addressing system for and methods of addressing memories in computer systems
EP0139254A3 (en) Apparatus and method for direct memory to peripheral and peripheral to memory data transfer
WO1998030948A3 (en) Apparatus and method for operably connecting a processor cache to a digital signal processor
WO1998048355A3 (en) Method for transmitting an operating system in computer systems

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): JP US

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1998931931

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 09403405

Country of ref document: US

ENP Entry into the national phase

Ref country code: JP

Ref document number: 1998 544720

Kind code of ref document: A

Format of ref document f/p: F

WWP Wipo information: published in national office

Ref document number: 1998931931

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 1998931931

Country of ref document: EP