WO1998039763A1 - Panneau d'affichage plat et procede pour alimenter ledit panneau - Google Patents

Panneau d'affichage plat et procede pour alimenter ledit panneau Download PDF

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Publication number
WO1998039763A1
WO1998039763A1 PCT/IB1997/001567 IB9701567W WO9839763A1 WO 1998039763 A1 WO1998039763 A1 WO 1998039763A1 IB 9701567 W IB9701567 W IB 9701567W WO 9839763 A1 WO9839763 A1 WO 9839763A1
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WO
WIPO (PCT)
Prior art keywords
electrodes
sustain
scan
sub
pairs
Prior art date
Application number
PCT/IB1997/001567
Other languages
English (en)
Inventor
Antonius Hendricus Maria Holtslag
Original Assignee
Koninklijke Philips Electronics N.V.
Philips Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V., Philips Ab filed Critical Koninklijke Philips Electronics N.V.
Priority to JP52914898A priority Critical patent/JP3918035B2/ja
Priority to PCT/IB1997/001567 priority patent/WO1998039763A1/fr
Priority to EP97946008A priority patent/EP0928477A1/fr
Priority to US09/180,159 priority patent/US6219012B1/en
Publication of WO1998039763A1 publication Critical patent/WO1998039763A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/294—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • the invention relates to a flat panel display apparatus with a drive circuit as defined in the precharacterizing part of claim 1.
  • the invention also relates to a method for driving a flat panel display as defined in the precharacterizing part of claim 5.
  • Prior art US 5,541,618 discloses sub field driven flat panel displays.
  • An embodiment describes a surface discharge type plasma display panel (further referred to as PDP).
  • a plurality of X-electrodes each arranged parallel and close to a plurality of Y- electrodes, and address electrodes orthogonal to the X and Y electrodes are arranged on a surface of a panel. Electrodes crossing each other are insulated with an insulating layer.
  • An address cell is formed at each crossing of the Y-electrodes and the address electrodes. Display cells are formed between the Y-electrode and the adjacent X-electrode, close to the corresponding address cells, respectively.
  • An address period is performed concurrently on all the Y-electrodes.
  • a write pulse is applied to all the X-electrodes while a first sustain pulse that is opposite to the write pulse is applied to all the Y-electrodes, and the address electrodes are kept at zero volts. Accordingly, all the display cells are discharged.
  • a second sustain pulse opposite to the write pulse is applied to all the X-electrodes, so that a wall charge is generated in each display cell and a part of the associated address cell.
  • an erase pulse is applied sequentially to each of the Y-electrodes.
  • an address pulse is selectively applied to an address electrode of a display cell not to be lit later during the subsequent display period by erasing a wall charge.
  • the wall charge is maintained and the cell will lit during the subsequent display period.
  • sustain pulses are applied to all the cells by applying first sustain pulses to all the Y-electrodes and second sustain pulses alternately to all X-electrodes. The cells with a wall charge are lit by the sustain pulses.
  • a first aspect of the invention provides a flat panel display apparatus with a drive circuit as defined in claim 1.
  • a second aspect of the invention provides a method of driving a flat panel display as defined in claim 5.
  • Advantageous embodiments are defined in the dependent claims.
  • a pair of scan and sustain electrodes (in the prior art referred to as X and Y electrodes, in the claims referred to as first and second electrodes) is associated with each display cell (also referred to as display element).
  • a display cell may be a portion of a plasma channel at the intersection of the a pair of scan and sustain electrodes and an address electrode (further referred to as data electrode).
  • the plasma channel may be aligned with the data electrodes or with the scan and sustain electrodes.
  • the scan and sustain electrodes each are divided in at least two groups such that the pairs of scan and sustain electrodes are divided in at least two groups.
  • Drive signals are supplied to the groups of scan and sustain electrodes such that the currents in the pairs of scan and sustain electrodes belonging to different groups flow in opposite direction.
  • the drive circuit for driving the sustain electrodes is very simple as it consists of conductors interconnecting the sustain electrodes in groups.
  • pairs of scan and sustain electrodes belonging to different groups alternate. In this way, a maximum compensation of the EMI generated by the two consecutive pairs is obtained, because a minimal area between successive pairs with opposite currents adds to the EMI, and a maximum correlation between the signals on the rows exist.
  • Fig. 1 schematically illustrates a circuit for driving a PDP of a surface- discharge type in a sub field mode as known from the prior art
  • Fig. 2 schematically illustrates a basic sub-pixel structure of a surface- discharge type PDP
  • Fig. 3 shows voltage waveforms between a scan and a sustain electrode of the prior art surface-discharge type PDP
  • Figs. 4A, 4B, and 4C show voltages supplied to the scan and the sustain electrodes during an erase period, a prime period and a sustain period
  • Fig. 5 shows the voltages supplied to the groups of scan and sustain electrodes according to an embodiment of the invention
  • Fig. 6 shows a basic sub-circuit of the scan driver circuit
  • Fig. 7 shows the connections of sub-circuits during a sustain period according to an embodiment of the invention.
  • Fig. 1 schematically illustrates a circuit for driving a PDP of a surface- discharge type in a sub field mode as known from the prior art.
  • Two glass panels (not shown) are arranged opposite to each other.
  • Data electrodes D are arranged on one of the glass panels.
  • Pairs of scan electrodes Sc and sustain electrodes Su are arranged on the other glass panel.
  • the scan electrodes Sc are aligned with the sustain electrodes Su, and the pairs of scan and sustain electrodes Sc, Su are perpendicular with respect to the data electrodes D.
  • Display elements (for example plasma cells) C are formed at the cross points of the data electrodes D and the pairs of scan and sustain electrodes Sc, Su.
  • a timing generator 1 receives display information Pi to be displayed on the PDP.
  • the timing generator 1 divides a field period Tf of the display information Pi into a predetermined number of consecutive sub field periods Tsf (see Fig. 3).
  • a sub field period Tsf comprises an address period or prime period Tp and a display period or sustain period Ts.
  • a scan driver 2 supplies pulses to the scan electrodes Sc for successively selecting the scan electrodes Sc one by one
  • a data driver 3 supplies data di to the data electrodes D to write the data di to the display elements C associated with the selected scan electrode Sc. In this way the display elements C associated with the selected scan electrode Sc are preconditioned.
  • a sustain driver 6 drives the sustain electrodes Su.
  • the sustain driver 6 supplies a fixed potential.
  • a sustain pulse generator 5 generates sustain pulses Sp which are supplied to the display elements C via the scan driver 2 and the sustain driver 6.
  • the display elements C which are preconditioned during the address period Tp to produce light during the display period Ts, produce an amount of light depending on a number or a frequency of the sustain pulses Sp. It is also possible to supply the sustain pulses Sp to either the scan driver 2 or the sustain driver 6. It is also possible to supply the sustain pulses Sp to the data driver 3 or both to the scan driver 2 or the sustain driver 6 and the data driver 3.
  • the timing generator 1 further associates a fixed order of weight factors Wf to the sub field periods Sf in every field period Tf.
  • the sustain pulse generator 5 is coupled to the timing generator 1 to supply a number or a frequency of the sustain pulses Sp in conformance with the weight factors Wf such that an amount of light generated by a preconditioned display element C corresponds to the weight factor Wf.
  • a sub field data generator 4 performs an operation on the display information Pi such that the data di is in conformance with the weight factors Wf.
  • Fig. 2 schematically illustrates a basic AC plasma sub-pixel of a surface- discharge type PDP.
  • the plasma sub-pixel or display element C is associated to phosphor emitting one of the three primary colors.
  • the plasma sub-pixel C is formed by the crossing of two row electrodes Sc, Su and a column electrode Co.
  • the two row electrodes Sc, Su are situated at the bottom of the sub-pixel and are referred to as scan electrode Sc and sustain electrode Su.
  • the column electrode Co is situated on top of the sub pixel and is referred to as data electrode D.
  • Plasma P is arranged between the column electrode Co and the two row electrodes Sc, Su via respective dielectric layers Di.
  • the plasma P is insulated from the dielectric layers Di by MgO layers Mg.
  • the sustain electrodes Su are interconnected for all rows of the PDP panel.
  • the scan electrodes Sc are connected to row IC's and scanned during the addressing or priming phase.
  • the column electrodes Co are operated by column IC's.
  • the plasma cells C are operated in three modes: 1) The Erase mode. Before each sub-field is primed, all plasma cells C are erased together at the same time. This is done by first driving the plasma cells C into a conducting state and then removing all charge built up in the cells C. 2) Prime mode. Plasma cells C are conditioned such that they will be in an on or off state during sustain mode. Since a plasma cell C can only be fully on or off, several prime phases are required to write all bits of a luminance value. Plasma cells C are selected on a row-at-a-time basis and the voltage levels on the columns Co will determine the on/off condition of the cells. If a luminance value is represented in 6 bits, then also 6 sub- fields are defined within a field.
  • Fig. 3 shows voltage waveforms between scan electrodes Sc and sustain electrodes Su of the known surface-discharge type PDP. Since there are three modes, the corresponding time sequence is indicated as Te,bx (erase mode for bit-x subfield), Tp,bx (prime mode for bit-x subfield SFi) and Ts,bx (sustain mode for bit-x subfield SFi.
  • the number of sustain pulses will vary in time to time limit the power dissipation so a residual time Tr is taken into account to match the field frequency again.
  • Fig. 4 shows result of a measurement of the differential voltage between a scan and the common sustain electrodes Sc, Su when this voltage is measured over a field.
  • Fig. 4 only gives a rough indication of what happens in a field period Tf.
  • Prime and erase sequences in each subfield SFi are the same.
  • the duration of the sustain sequence depends on the weight of the individual bits and contains a number of alternating pulses with the same frequency.
  • the number of alternating pulses during sustain time Ts,bx will be less. This results in shorter sustain periods Ts,bx in the sub-fields SFi and the residual time T r will increase to match the field frequency.
  • Table 1 Timing in erase, prime and sustain modes.
  • Table 1 gives an overview of the panel's timing when an over-all black (level 0) or white (level 63) picture is displayed. As can be seen from the table, the prime and erase modes are not changed when the power dissipation is limited by the electronics.
  • the number of sustain pulses is roughly halved when a complete white picture is displayed.
  • Equation 1 can be used to calculated the sustain time Ts,bx in a subfield SFi.
  • N stands for pulse count, printed in the table. Each pulse takes 9.6 ⁇ s and N pulses are always preceded by a specified sequence of 19 ⁇ s.
  • Figs. 4A, 4B, and 4C show voltages supplied to the scan and the sustain electrodes Sc, Su during an erase period Te, a prime period Tp and a sustain period Ts, respectively.
  • each plasma cell C (further referred to as cell) is addressed with two row electrodes (the scan and the sustain electrodes Sci, Sui) and one column electrode (the data electrode Dj).
  • a VGA display may consists of 480 * (3 * 852) cells C.
  • the number of rows Ri is 480, the number of pixels in a row is 852, and a pixel consists of three adjacent cells CR, CG, CB, one for each of the three primary colors.
  • Fig, 4 A shows voltages applied to the electrodes Sc, Su, D during the erase period Te.
  • a sequence of scan voltages Vsc applied to the scan electrodes Sc is denoted by five numbers arranged in a column at the left side of the plasma panel. The five numbers correspond to five consecutive sub periods of the erase period Te. The first number of the column denotes the value of the scan voltage Vsc during a first sub period of the erase period Te, the fifth number in the column denotes the value of the scan voltage Vsc during the last sub period of the erase period Te. All scan electrodes Sc are interconnected.
  • a sequence of sustain voltages Vsu applied to the sustain electrodes Su is denoted at the right side of the plasma panel. All sustain electrodes Su are interconnected.
  • a sequence of data voltages Vd applied to the data electrodes D is denoted at the right side of the plasma panel.
  • Voltage values which have a same vertical position in a column belong to a same sub period of the erase period Te.
  • the scan voltage Vsc is minus 160 volts
  • the sustain voltage Vsu is zero volts
  • the data voltage is zero volts.
  • Fig. 4B shows the scan voltage Vsc, the sustain voltage Vsu, and the data voltage Vd during a sub period of the prime period Tp.
  • the scan voltage Vsc of the selected row Rs has a value of minus 170 volts.
  • a scan voltage Vsc of minus 70 volts is applied.
  • All sustain electrodes Su are interconnected and receive a sustain voltage of 50 volts.
  • the data voltage Vd has either a value of zero volts or 60 volts to precondition a cell C to stay dark or to emit light, respectively, during the subsequent sustain period Ts.
  • the prime period Tp all rows are selected subsequently to precondition all the cells C row by row. Only the primed cells C will ignite during the sustain period.
  • Fig. 4C shows the scan voltage Vsc, the sustain voltage Vsu, and the data voltage Vd during the sustain period Ts, as applied in the prior art.
  • the scan voltage Vsc is applied to the scan electrodes Sc which are all interconnected.
  • the sustain voltage Vsu is applied to the sustain electrodes Su which are all interconnected.
  • the data electrodes D supply a data voltage Vd with a value of 60 volts.
  • the sustain period Ts comprise sustain pulses Sp with a typical repetition time of about 20 us.
  • a sustain pulse Sp comprises two consecutive periods, a first period during which the scan voltage Vsc is 170 volts and the sustain voltage Vsu is zero volts, and a second period during which the scan voltage Vsc is zero volts and the sustain voltage Vsu is 170 volts.
  • large currents flow in the rows R of the PDP to create the light output.
  • a maximum current of about 300 mA flows in each row R of a 42" PDP when a white line has to be displayed. Consequently, a total display peak current of 144 ampere with a frequency of about 50 kHz flows in a VGA display with 480 rows R if a white plane has to be displayed. This introduces a lot of EMI.
  • the total return current is collected at the back of the PDP in the middle. So, the total current is supplied to, or withdrawn from the scan electrodes Sc via a scan conductor connected to the scan electrode Sc arranged in the middle of the PDP, and the total current is supplied to or withdrawn from the sustain electrodes Su via a sustain conductor connected to the sustain electrode Su arranged in the middle of the PDP. Both the scan and the sustain conductor end at the right side of the PDP near to each other.
  • the total area enclosed by the currents equals approximately:
  • Atotal 2 * (1 + 2 + ... +240) * Ar - 57840 Ar.
  • This total area Atotal is a measure for the amount of EMI generated by the PDP.
  • Fig. 5 shows the voltages supplied to the groups of scan and sustain electrodes Sc, Su during the sustain period Ts according to an embodiment of the invention.
  • the scan electrodes Sc and the sustain electrodes Su both are divided in two groups. All scan electrodes Sco of odd rows Ro are interconnected to receive a first voltage VI, and all scan electrodes See of even rows are interconnected to receive a second voltage V2. All sustain electrodes Suo of the odd rows are interconnected to receive the second voltage V2, and all sustain electrodes Sue of the even rows are interconnected to receive the first voltage VI . Both the first voltage VI and the second voltage V2 have alternately a value of zero and 170 volts.
  • the PDP is divided in blocks of n (for example 16) successive rows R in which the current flows in a same direction followed by a block of successive rows R in which the current flows in a direction opposite to the current direction of the preceding block of successive rows R.
  • Fig. 6 shows a basic sub-circuit 20 of the scan driver circuit 2.
  • the basic sub-circuit 20 of Fig. 6 comprises a first field effect transistor (FET) 22 with a main current path arranged in series with a main current path of a second FET 24.
  • First and second diodes 23, 25 are the parasitic diodes of the first and second FET, respectively.
  • a control circuit 21 receives an input control signal on input I and supplies control signals to control electrodes of the first and the second FET 22, 24.
  • the interconnected main terminals of the first and the second FET 22, 24 are connected to a terminal C. Terminal C is connected to one of the scan electrodes Sc.
  • the yet free main terminal of the first FET 22 is connected to a terminal B, and the yet free main terminal of the second FET 24 is connected to a terminal A.
  • a first negative voltage (for example: -70 V) is applied to the terminal B, and a second negative voltage (for example: -170 V) is applied to the terminal A.
  • the input control signal applied to the input terminal I determines whether the first FET 22 or the second FET 24 is conductive. If the first FET 22 is conductive, the first negative voltage is supplied to the scan electrode Sc and the associated row is not selected. If the second FET 24 is conductive, the second negative voltage is supplied to the scan electrode Sc and the associated row is selected.
  • a sub-circuit 20 is connected to every scan electrode Sc to enable priming of the rows R one by one (the cells C associated with the selected row R are preconditioned) by applying appropriate input control signals to respective inputs I of the control circuits 21.
  • the control circuits 21 control the first and the second FET 22, 24 to be non-conductive. So, only the first and second diodes 23, 25 are relevant during the sustain period Ts.
  • a first period of a sustain pulse Sp a high positive voltage (for example: +170 V) is applied to terminal A, while terminal B is open ended.
  • a current II flows from terminal A via diode 25 to the scan electrode Sc connected to. terminal C.
  • a second period of a sustain pulse Sp a low voltage (for example: 0 V) is applied to terminal B, while terminal A is open ended.
  • a current 12 flows from terminal C via diode 23 to terminal B.
  • Fig. 7 shows the connections of sub-circuits 20i during a sustain period Ts according to an embodiment of the invention. As discussed earlier, only the first and second diodes 23, 25 are relevant during the sustain period Ts. Therefore, Fig. 7 only shows the first and second diodes 23, 25 of each sub-circuit 20.
  • a sub drive circuit 2e comprises the left column of sub-circuits 20e with first and second diodes 23e, 25e to drive the scan electrodes See of the even rows Re.
  • a sub drive circuit 2o comprises the right column of sub-circuits 20o with first and second diodes 23o, 25o to drive the scan electrodes Sco of the odd rows Ro.
  • All terminals Ao of the sub-circuits 20o in the right column are connected to a first contact 1 of a first switch SI .
  • All terminals Bo of the sub-circuits 20o are connected to a second contact 2 of the first switch SI .
  • All terminals Be of the sub-circuits 20e in the left column are connected to a first contact 1 of a second switch S2.
  • All terminals Ae of the sub- circuits 20e are connected to a second contact 2 of the second switch S2.
  • a common contact of the first switch SI receives a first voltage VI from the sustain pulse driver 5, and a common contact of the second switch S2 receives a second voltage V2 from the sustain pulse driver 5.
  • the first voltage VI is also applied to the even sustain electrodes Sue, via a sub drive circuit 6e.
  • the second voltage V2 is also applied to the odd sustain electrodes Suo, via a sub drive circuit 6o.
  • the sub drive circuits 6e and 6o are conductors. Both the first and the second switch SI, S2 connect their common contact with contact 1 if the first voltage VI has a high level (for example: 170 V), and both the first and the second switch SI, S2 connect their common contact with contact 2 if the first voltage VI has a low value (for example: 0 V).
  • the first and the second switch may be omitted if impedance's of the conductors between the first and the second switch contacts 1, 2 are negligible.
  • the first and the second contact 1, 2 of the first switch SI may be interconnected to receive the first voltage VI
  • the first and the second contact 1, 2 of the second switch S2 may be interconnected to receive the second voltage V2.
  • a first row R of cells C is associated to a first scan electrode Sc and a sustain electrode Su
  • a second row R of cells is associated to the same sustain electrode Su and a second scan electrode Sc
  • the sustain electrodes Su are divided in two groups such that two sustain electrodes Su arranged on either side of a scan electrode Sc belong to different groups.
  • the priming of only one row R of cells C is possible by applying appropriate voltages to the scan electrode Sc and the adjacent sustain electrodes Su.
  • By further dividing the groups of sustain electrodes Su it is possible to obtain groups of pairs of sustain electrodes Su and scan electrodes Sc, whereby the currents in pairs belonging to different groups flow in opposite directions.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

On décrit un panneau d'affichage plat qui comprend une pluralité d'éléments d'affichage (C) arrangés en une matrice constituée de rangées (R) et de colonnes, un premier jeu et un deuxième jeu d'électrodes (Sc, Su), lesdites électrodes étant alignées l'une par rapport à l'autre en rangée ou en colonne. Les premier et deuxième jeux d'électrodes (Sc, Su) sont formés par paires associées auxdits éléments d'affichage (C). Un certain niveau d'interférence électromagnétique provoqué par des courants traversant les premier et deuxième jeux d'électrodes (Sc, Su) est atténué par séparation des électrodes en au moins deux groupes, de sorte que les paires soient réparties en deux groupes et que le courant traversant des paires appartenant à des groupes différents circule en sens contraire.
PCT/IB1997/001567 1997-03-07 1997-12-15 Panneau d'affichage plat et procede pour alimenter ledit panneau WO1998039763A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP52914898A JP3918035B2 (ja) 1997-03-07 1997-12-15 フラットパネルディスプレイ装置およびこのようなパネルの駆動方法
PCT/IB1997/001567 WO1998039763A1 (fr) 1997-03-07 1997-12-15 Panneau d'affichage plat et procede pour alimenter ledit panneau
EP97946008A EP0928477A1 (fr) 1997-03-07 1997-12-15 Panneau d'affichage plat et procede pour alimenter ledit panneau
US09/180,159 US6219012B1 (en) 1997-03-07 1997-12-15 Flat panel display apparatus and method of driving such panel

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP97200691 1997-03-07
EP97200691.0 1997-03-07
PCT/IB1997/001567 WO1998039763A1 (fr) 1997-03-07 1997-12-15 Panneau d'affichage plat et procede pour alimenter ledit panneau

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EP0936655A2 (fr) * 1998-02-16 1999-08-18 Sony Corporation Dispositif plat d'affichage par décharge plasma
FR2787909A1 (fr) * 1998-12-25 2000-06-30 Nec Corp Unite de chargement a plasma a nombre d'elements d'image pouvant etre excites de facon simultanee reduit de moitie
JP2002093353A (ja) * 2000-09-14 2002-03-29 Futaba Corp Ｉｃチップ付き蛍光表示管及び点灯方法

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US5030888A (en) * 1988-08-26 1991-07-09 Thomson-Csf Very fast method of control by semi-selective and selective addressing of a coplanar sustaining AC type of plasma panel
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EP0936655A2 (fr) * 1998-02-16 1999-08-18 Sony Corporation Dispositif plat d'affichage par décharge plasma
EP0936655A3 (fr) * 1998-02-16 1999-12-08 Sony Corporation Dispositif plat d'affichage par décharge plasma
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JP2002093353A (ja) * 2000-09-14 2002-03-29 Futaba Corp Ｉｃチップ付き蛍光表示管及び点灯方法
JP4642984B2 (ja) * 2000-09-14 2011-03-02 双葉電子工業株式会社 Ｉｃチップ付き蛍光表示管の駆動方法並びにエージング方法

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