WO1998020674A1 - Drive control method, image pickup control method, image pickup controller, image pickup system, and image pickup device for image pickup element - Google Patents

Abstract

The operation control of the image pickup device (310) is performed by the image pickup controller (320), according to the trigger signal TRIG obtained by detecting an object (302) to be inspected, with an object sensor (303), so as to pick up the image of the object (302) to be inspected, transferred on a transfer path (301), with the image pickup device (310). The image pickup controller (320) is equipped with a variable pulse width setter (307) which generates a modulated trigger signal MTRIG where pulse width can be set variably based on the trigger signal TRIG, a synchronizing signal generator (323) which generates a standard vertical synchronizing signal VD and a standard horizontal synchronizing signal HD conforming to a standard television system, a sub-synchronizing signal generator (324) which generates a sub-vertical synchronizing signal EXT-VD to give the second timing based on the first timing being the timing of the leading edge of the above modulated trigger signal MTRIG, and a high-speed horizontal synchronizing signal generator (325) which generates over a first period a high-speed horizontal synchronizing signal Hi-HD higher in frequency than the above standard horizontal synchronizing signal HD.

Description

 TECHNICAL FIELD The present invention relates to an imaging device of an imaging device suitable for imaging, for example, an object that moves at high speed, and a method for controlling the driving of the imaging device, an imaging control method, an imaging control device, an imaging system, and an imaging device. TECHNICAL FIELD The present invention relates to a drive control method, an imaging control method, an imaging control device, an imaging system, and an imaging device.

Background technology

By controlling the effective charge storage time of an interline transfer (IT) -type solid-state imaging device (CCD image sensor), the applicant of the present invention can eliminate the need for a mechanical iris. An imaging device having an electronic shutter function for adjusting the exposure time is proposed in US Pat. No. 5,157,502.

 In this imaging apparatus, the sensor gate signal SG shown in FIG. 1B output during a vertical blanking period VBLK in which the vertical blanking signal VB shown in FIG. The charge stored in each pixel is read out to the vertical transfer unit. the above.

The charge storage time of the CD image sensor is determined by the reset signal shown in Figure 1C. The CCD image sensor is controlled by RT. When the reset signal R # is supplied, the CCD image sensor sweeps the charge accumulated in the pixel to the overflow drain.

 For this reason, while the reset signal R 供給 is supplied every horizontal period (1 電荷) (charge sweeping period Τ Τ), no effective charge is accumulated in the CCD image sensor. Accordingly, effective charge is accumulated in the photoelectric conversion unit of the CCD image sensor from the time when the reset signal RT supplied to the CCD image sensor is stopped, and the reset signal RT is stopped when the reset signal RT is stopped. By controlling the timing, the effective charge accumulation time TE, that is, the shirt speed can be controlled.

 The above-described imaging device is advantageous in capturing an image particularly in a high-speed moving object because the use of such an electronic shirt function makes it possible to vary the shutter speed in accordance with the movement of the subject. . Here, as an imaging device for factory automation (FA), for example, an imaging device for imaging a moving object with a configuration as shown in FIG. 2 is known. In this imaging device, when the object 2 moving on the moving path 1 moves in front of the imaging unit 3, the object detection unit 4 detects this and falls at the timing t11 shown in FIG. 3A. The trigger signal TRIG which becomes low level is supplied to the shirt signal generator 5 and the synchronizing signal generator 8.

When the above-mentioned trigger signal TRIG is supplied, the above-mentioned trigger signal generating circuit 5 generates a shut-down control signal which rises at the timing t11 when the above-mentioned trigger signal TRIG falls, as shown in FIG. 3B. Supply STC to CCD control circuit 6. The CCD control circuit 6 supplies a reset signal RT for sweeping out the charges accumulated in the photoelectric conversion unit of the CCD image sensor 7 to an overflow drain, and supplies the trigger signal TRIG. Then, the supply of the reset signal RT to the CCD image sensor 7 is stopped. As a result, the accumulation of effective charges in each pixel of the photoelectric conversion unit of the CCD image sensor 7 is started.

 As shown in FIG. 3C, the CCD control circuit 6 includes a vertical synchronizing signal VD and a vertical synchronizing signal VD, which are at a low level during the period from timing t11 to timing t12, as shown in FIG. 3C. The indicated horizontal synchronization signal HD is supplied. When the shirt control signal STC is supplied, the CCD control circuit 6 outputs the signal of the horizontal synchronization signal HD shown in FIG. 3D from the timing t11 when the vertical synchronization signal VD shown in FIG. 3C falls. After counting the number of pulses 9 times, the master clock is counted a predetermined number, and then the sensor gate signal SG rising at the timing t13 shown in FIG. 3E is supplied to the CCD image sensor 7.

 As a result, after the shutter control signal STC rising at the timing t11 shown in FIG. 3B is supplied to the CCD image sensor 7, the timing t13 shown in FIG. Until the rising sensor gate signal SG is supplied to the CCD image sensor 7, charges corresponding to the imaging light irradiated through the imaging lens 9 are accumulated in the CCD image sensor 7. The effective charge accumulation time TE is between the timing t11 and the timing t13. FIG. 3F shows the vertical blanking period VBLK.

The charge read from the CCD image sensor 7 is supplied to the signal processing circuit 10 as an image signal. The signal processing circuit 209 includes: The image signal is subjected to signal processing such as adding a synchronization signal, and is output as a video signal via the output terminal 11. The video signal output via the output terminal 11 is supplied to, for example, a monitor. Thereby, the state of the object 2 when the object 2 is moved can be analyzed.

 As described above, in this imaging device, the moving object 2 is imaged by generating the vertical synchronization signal VD in accordance with the trigger signal TRIG supplied from the object detection unit 4 and starting the accumulation of the effective charge. It has become.

 By the way, since the imaging device that captures an image of a moving object is mainly used for FA, the imaging device 2 shown in FIG. 2 is moved at a high speed, for example, at a high speed of 1/1000 second or the like. You may want to take an image due to a shut down.

 However, in the above-described imaging apparatus, the output timing of the sensor gate signal SG is preset and fixed based on the pixel arrangement of the CCD image sensor. For example, the horizontal synchronization signal is output from the fall of the vertical synchronization signal VD. After counting 9 HD pulses, the sensor gate signal SG is supplied to the CCD image sensor at the timing when the clock is counted a predetermined number. Therefore, in the above-described imaging apparatus that performs the imaging operation by generating the vertical synchronization signal VD from the trigger signal TRIG, the timing from the falling of the vertical synchronization signal VD to the timing when the sensor gate signal SG is output. The effective charge accumulation time could not be shortened in less than the time, and it was not possible to perform imaging by high-speed shutdown such as 1/1000 second.

In addition, using an image processing device, the video signal from the There are times when you want to perform image processing. Generally, an image processing device operates based on a predetermined synchronization signal. Therefore, for example, when synthesizing video signals from a plurality of imaging devices, video recording / reproducing devices, and the like, it is necessary to supply a video signal synchronized with a reference synchronization signal to an image processing device.

 In such a case, when the trigger signal TRIG is supplied at an arbitrary timing, for example, as shown in FIG. 4A, after a predetermined effective charge accumulation time, that is, an exposure time, the imaging apparatus returns to FIG. 4B. The sensor gate signal SG shown in the figure is supplied to the CCD image sensor, and the electric charge accumulated in each pixel of the photoelectric conversion unit is read out to the vertical transfer unit. At the same time, a vertical synchronization signal V-SYNC is generated, as shown in FIG. 4C. The charge read out to the vertical transfer unit in synchronization with the generated vertical synchronization signal V-SYNC is output as an image signal VIDE # via the horizontal transfer unit. In this imaging device, as shown in FIG. 5A, video signals VIDE 0 are output at random intervals as shown in FIG. 5B according to an arbitrary timing, that is, a randomly supplied trigger signal TRIG. Therefore, the vertical synchronization signal V_SYNC cannot be output at a constant cycle.

Alternatively, this imaging apparatus generates a vertical synchronizing signal V-SYNC having a constant period as shown in FIG. 6C, and supplies a trigger signal TRIG shown in FIG. After a period of time, the sensor gate signal SG shown in Fig. 6B is supplied to the CCD image sensor, and the electric charges accumulated in each pixel of the photoelectric conversion unit are read out to the vertical transfer unit, and at the same time, the vertical synchronization signal Unlike V_SYNC, the vertical synchronization signal V-SYNC is generated at the timing based on the trigger signal TRIG. By the way, in a video processing device such as a frame memory or a monitor that performs processing using a video signal from such an imaging device, it is required to synchronize its operation with a supplied video signal.

 However, in these video processing devices, synchronizing with a synchronization signal having a random period is very difficult technically and is not generally performed.

 Therefore, an object of the present invention is to provide a drive control method for an image sensor, which performs an image pickup operation by high-speed random shutter synchronized with a trigger signal so that an effective charge in a predetermined image pickup range can be obtained as an image pickup signal. It is to provide an imaging device, an imaging control device, and an imaging system.

 Another object of the present invention is to provide a drive control method, an image pickup device, an image pickup control device, and an image pickup system of an image pickup device capable of obtaining an image pickup signal in an arbitrary image range.

 Also, in the field of speed competition such as land and swimming in sports competitions,

The arrival order is determined with an accuracy of 1/1000 second.

 Therefore, an object of the present invention is to capture such a game content at an interval of 1/1100 seconds and to combine and output an image having a time difference of 1/1100 seconds into one image. It is an object of the present invention to provide an imaging control method, an imaging control device, an imaging system, and an imaging device that can perform the following.

Further, another object of the present invention is to provide an imaging control method, an imaging control device, an imaging system, and an imaging method capable of imaging an object moving at high speed with a predetermined time difference, synthesizing and outputting a single image. Equipment. DISCLOSURE OF THE INVENTION In the present invention, a standard vertical synchronizing signal and a standard horizontal synchronizing signal conforming to the standard television system are generated, and based on the standard vertical synchronizing signal, a period of 1/2 or less of the standard vertical synchronizing signal is generated. A trigger signal is generated, and at the first timing according to the trigger signal, all charges accumulated in each light receiving element of the interline transfer solid-state imaging device are eliminated as reactive charges. At a second timing after a predetermined time from the second timing, the charges accumulated in the plurality of light receiving elements are read out to the vertical transfer unit, and the second timing from the second timing to the third timing is read out. The charge transferred to the vertical transfer unit is vertically transferred at a first transfer rate over a period of 1, and the fourth timing, which is the timing of the next trigger signal from the third timing, Second period until The charge of the vertical transfer unit is vertically transferred at a second transfer rate corresponding to the standard television system, which is slower than the first transfer rate, so that the vertical signal is transmitted every cycle of the trigger signal. The above-mentioned line transfer solid-state imaging device is controlled so as to output one frame of image information via the transfer unit. Then, the image information output from the in-line transfer type solid-state imaging device during a plurality of cycles of the trigger signal is temporarily stored, and the stored image information of a plurality of frames is stored. At the rate based on the standard vertical sync signal and the standard horizontal sync signal, it is read out as one frame of output image information, and the read out one frame of output image information is compared with the standard vertical sync signal and standard Add horizontal sync signal. As a result, image information obtained by capturing an object moving at high speed with a predetermined time difference and combining it into one image Obtainable. For example, a standard vertical sync signal and a standard horizontal sync signal conforming to the CCIR (Interational Radio Consultative Committee) method are generated, and a trigger signal having a period of 1/2 of the standard vertical sync signal is generated, and the CCIR image pickup is performed. By performing the imaging control of the apparatus, an image having a time difference of 1/1100 seconds can be synthesized and output as one image.

Further, according to the present invention, a second trigger signal having a pulse width variably set by a user is generated based on the first trigger signal, and the timing of the leading edge of the second trigger signal is generated. In a second timing based on a certain first evening, all charges accumulated in a plurality of light receiving elements of the interline transfer solid-state imaging device are eliminated as invalid charges, and the second evening is performed. The charges accumulated in the plurality of light receiving elements are read out to the vertical transfer unit at a third timing after a predetermined time from the third timing, and during the first period from the third evening to the fourth timing described above. The charge transferred to the vertical transfer unit is vertically transferred at a first transfer rate over a period from the fourth timing to the fifth evening based on the trailing edge of the second trigger signal. For the second period, the vertical transfer unit Is transferred vertically from the horizontal transfer unit during the second period as the effective charge. Let it. As a result, the electronic shutter function of the in-line and one-line transfer type solid-state imaging device is used to perform a high-speed random shutter imaging operation synchronized with the first trigger signal, and the second trigger signal pulse is output. An imaging signal in an image range determined by the width can be obtained. In addition, by setting the pulse width of the above trigger signal, the number of lines to be output as the imaging signal is changed, and an arbitrary image range is set. A surrounding image signal can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a time chart for explaining an electronic shutdown function in a conventional imaging device.

 FIG. 2 is a block diagram showing a configuration of a conventional imaging device.

 FIG. 3 is a time chart showing an effective charge accumulation period in an imaging operation of a conventional imaging device.

 FIG. 4 is a time chart showing an imaging operation in synchronization with a trigger pulse signal in a conventional imaging device.

 FIG. 5 is a time chart showing an imaging operation in synchronization with a trigger pulse signal in a conventional imaging device.

 FIG. 6 is a time chart showing an imaging operation in synchronization with a trigger pulse signal in a conventional imaging device.

 FIG. 7 is a block diagram showing an overall configuration of an imaging system to which the present invention is applied.

 FIG. 8 is a block diagram illustrating a configuration of an imaging device used in the imaging system.

 FIG. 9 is a plan view schematically showing a configuration of a CCD image sensor in the imaging device.

FIG. 10 is a timing chart showing the operation of the imaging apparatus. ₍ FIG. 11 is a circuit diagram showing a specific configuration of a sub-synchronous signal generation unit in the imaging control apparatus used in the imaging system. . FIG. 12 is a timing chart showing the operation of the sub-synchronization signal generator.

 FIG. 13 is a circuit diagram showing a specific configuration of a high-speed horizontal synchronizing signal generator in the imaging control device.

 FIG. 14 is a timing chart showing the operation of the imaging control device.

 FIG. 15 is a diagram for explaining a video signal obtained by the imaging control device.

 FIG. 16 is a diagram showing an image on a monitor screen represented by a video signal obtained by the imaging control device.

 FIG. 17 is a diagram showing the overall configuration of another imaging system to which the present invention is applied.

 FIG. 18 is a block diagram showing a configuration of an imaging device used in the imaging system.

 FIG. 19 is a plan view schematically showing a configuration of a CCD image sensor in the imaging device.

 FIG. 20 is a timing chart illustrating the operation of the imaging apparatus. FIG. 21 is a circuit diagram illustrating a specific configuration example of a variable pulse width setting unit in the imaging control apparatus used in the imaging system. It is.

 FIG. 22 is a time chart showing the operation of the variable pulse width setting unit.

 FIG. 23 is a circuit diagram showing a specific configuration of a sub-synchronous signal generation unit in the imaging control device used in the above-described imaging system.

FIG. 24 is a timing chart showing the operation of the sub-synchronous signal generator. FIG. 25 is a diagram illustrating the principle for changing the reading start position of an image captured by the CCD image sensor in the above-described imaging apparatus.

 FIG. 26 is a view for explaining the principle for changing the image reading start position.

 FIG. 27 is a diagram illustrating an image size of an image pickup signal read from the CCD image sensor in the image pickup apparatus.

 FIG. 28 is a diagram for explaining the image size.

 FIG. 29 is a diagram illustrating a trigger cycle of an imaging operation by the imaging device.

 FIG. 30 is a diagram showing a state where the position of the subject imaged by the imaging device is shifted on the screen.

 FIG. 31 is a diagram illustrating a state in which the position of the subject imaged by the imaging apparatus, which is shifted on the screen, is automatically corrected so as to be output at the same timing.

 FIG. 32 is a block diagram showing a configuration of a setting circuit of a high-speed horizontal synchronizing signal generation unit having the function of performing the automatic correction.

 FIG. 33 is a circuit diagram showing the configuration of the sawtooth wave generator of the setting circuit.

 FIG. 34 is a timing chart for explaining the operation of the setting circuit.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

 The present invention is applied to, for example, an imaging system having a configuration as shown in FIG. This imaging system is an imaging system that captures a subject 102 traveling on a travel path 101 by an imaging device 110 and captures the image as a still image, and controls the operation of the imaging device 110. The video signal VIDE 0 from the imaging device 110 is taken into the memory 121 as a video signal VIDE 0 from the imaging device 110 as a still image signal, and the video signal VIDE 0 from the imaging device 110 is stored in the memory 1. And an image processing device 130 supplied as a still image signal via the image processing device 21.

 As shown in FIG. 8, the imaging device 110 is provided with a synchronization signal generation unit 11 to which external synchronization signals EXT_VD and EXT-HD are supplied from the imaging control device 20 via terminals CI and C2. 1A, a sub-synchronous signal generator 111B and a gate signal generator 112 to which a trigger signal CTRIG is supplied from the imaging control device 120 via a terminal C4. A switch circuit 113 controlled to be switched by the gate signal GATE supplied from the signal generator 112, and a mass of approximately 28.6 MHz supplied from the mass clock generator 114 It is driven by a timing generator 115 that operates with the evening clock MCK and a CCD driver 116 that operates according to various timing signals supplied from the timing generator 115. The correlation between the CCD image sensor 1 17 and the imaging signal from the CCD image sensor 1 17 Sampling (CDS: Correlated double sampling) comprising a processing unit 1 1 9 supplied via the circuit 1 1 8.

The above CCD image sensor 117 has a structure as shown in FIG. All-pixel readout by simultaneous readout of two lines of IT (Interline Transfer) type. In a CCD image sensor, the light receiving section SODD corresponding to each pixel in the odd field and the pixels in the even field are used. The corresponding light receiving section S _EVEN , the vertical transfer section VREG in which the charges of all the pixels _stored in each of the light receiving sections S _0DD and S EVEN are read out for each field, and the charge read out to the above vertical transfer section V _KEFI the horizontal transfer section H _{REG 1} for two lines to be output as an image signal of one horizontal line unit,

_{ΕΑ Κ ΕΑ2,} and by controlling the potential of a not-shown _substrate formed below the light receiving sections S ODD and S EVEN, the electric charges accumulated in each light receiving section S OD D and S EVEN are It has an electronic shutdown function that controls the charge storage time by sweeping it down to the substrate. The synchronizing signal generator 111A receives the clock CL of about 14.3 MHz obtained by dividing the master clock MCK by 1/2 from the timing generator 115, and this clock CL And generates internal signals VD and HD, and divides the clock CL by 1/4 to generate a CL / 4 signal with a frequency of about 3.5 MHz. . The synchronization signal generator 111A is configured to enable external synchronization. When the external synchronization signals EXT-VD and EXT-HD are supplied to the terminals C1 and C2, the external synchronization is performed. Signal EXT — Generates internal synchronization signals VD and HD synchronized with VD and EXT_HD. Then, the internal synchronization signals VD, HD, and CL / 4 signal generated in the synchronization signal generation section 111A are supplied to the sub synchronization signal generation section 111B. Further, the internal synchronization signals VD and HD are supplied to the gate signal generation unit 112 and the processing unit 119. Further, the sub-synchronous signal generation section 111 B is provided with a modulation vertical synchronization signal TG-VD and a modulation horizontal synchronization signal TG- based on the timing t1 of the trigger signal CTRIG supplied to the terminal C4. Generates HD and electronic shutdown control signal X—SUB. The sub-synchronous signal generator 111B generates a modulated vertical synchronizing signal TG as shown in FIG. 10C with reference to the rising timing t1 of the trigger signal TRIG as shown in FIG. 10A. Generates VD and stops the electronic shirt evening control signal X-SUB as shown in Fig. 10B for a period T1 corresponding to the preset shutdown speed based on this modulated vertical synchronization signal TG—VD. At the same time, the above-mentioned CL / 4 signal is used only for a predetermined period T2 after the above period T1 has elapsed, and the normal internal horizontal synchronization signal HD is used for the periods other than the above periods T1 and T2. Generate The modulated vertical synchronizing signal TG-VD generated by the sub-synchronizing signal generating unit 1111B is supplied to the timing generator 115, and the modulated horizontal synchronizing signal TG-HD is controlled by the switch. The electronic circuit control signal X—SUB is supplied to the switch circuit 113, and furthermore, to the CCD drive section 116.

The gate signal generator 112 counts 16 internal horizontal synchronization signals HD based on the rising edge timing t1 of the trigger signal C TRIG supplied to the terminal C4. After the elapse of the 16 H period, the gate signal GATE shown in FIG. 10E is generated, which becomes the logic “H” for the predetermined period T 3 (the 19 H period here) of the above period T 2. . The gate signal GATE generated by the gate signal generation unit 112 is supplied to the switch circuit 113.The switch circuit 113 also controls the imaging control. From device 1 2 0 A high-speed horizontal synchronizing signal Hi_HD having a frequency twice as high as the horizontal synchronizing frequency f π in the CCIR system is supplied via a terminal C 4, and a period T 3 in which the gate signal GATE becomes logic “H” Only the high-speed horizontal synchronization signal H i—HD is selected, and during the period other than the period T 3, the modulated horizontal synchronization signal TG—HD supplied from the sub-synchronization signal generation unit 11 1 B is selected. It has become. The modulated horizontal synchronizing signal TG_HD ′ as shown in FIG. 10F composed of the high-speed horizontal synchronizing signal Hi-HD and the modulated horizontal synchronizing signal TG—HD selected by the switch circuit 113 is Supplied to the timing generator 115.

 In addition, the timing generator 115 includes the modulated vertical synchronization signal TG—VD supplied from the sub-synchronization signal generator 111B and the high-speed horizontal synchronization signal selected by the switch circuit 113. Various timing signals necessary for driving the CCD image sensor 117 are generated based on the Hi-HD and the modulated horizontal synchronization signal TG_HD, and supplied to the CCD drive unit 116. I do.

 In addition, the CCD drive section 116 generates the sensor gate signal SG, horizontal transfer pulse, and vertical transfer pulse shown in FIG. 10D based on the various timing signals, the electronic control signal X—SUB, and the timing signal. And the like to drive the CCD image sensor 117.

Further, the CDS circuit 118 responds to the imaging signal read out simultaneously from the CCD image sensor 117 by two lines based on a sampling pulse supplied from the timing generator 115 so-called. Performs correlated double sampling to extract the information component of the image signal and noise such as reset noise contained in the image signal. Is removed.

 Then, the processing section 119 performs predetermined processing such as gamma correction on the imaging signal supplied from the CDS circuit 118. The video signal V output from this process section 119 as shown in Fig. 10G

1 D E 0 1, V I D E 02 is connected to the above imaging control device 1 via a terminal C 5.

Supplied to 20.

 The imaging control device 120 includes a memory 12 1 to which video signals VIDE 01 and VIDE 02 obtained by the imaging device 110 are supplied via a terminal C 51, and data to the memory 12 1 It has a memory controller 122 that controls writing / reading of data. The imaging control device 120 includes a synchronization signal generator 123, a sub-synchronization signal generator 124, a high-speed horizontal synchronization signal generator 125, a master clock generator 126, and a trigger signal. A generator 1 27 is provided. The trigger signal C TRIG generated by the trigger signal generating section 127 is supplied to the memory controller 122 and the sub-synchronous signal generating section 124 and output via the terminal C 41. Further, the imaging control device 120 applies CC to the video signal read from the memory 122.

Equipped with a signal adder 128 that adds a 50 Hz composite sync signal MCS conforming to the 1R system. And this imaging control device 1

Numeral 20 outputs a video signal VIDEO compliant with the CCIR method from the signal adder 128 through the terminal C52. In the imaging control device 120, the synchronization signal generating section 23 conforms to the CCIR method based on a mask clock MCK of about 28.6 MHz supplied from the master clock generator 126. The master vertical sync signal MVD, composite sync signal MCS and In addition to generating the synchronization signals VD and HD, it also generates a 2 FH signal with a frequency twice that of the horizontal synchronization signal HD and a CL / 4 signal obtained by dividing the master clock MCK by 1/4. The master / slave vertical synchronization signal MVD generated by the synchronization signal generator 123 is supplied to the memory controller 122 and the trigger signal generator 27, and the synchronization signal VD, HD is supplied to the memory controller 122, the vertical synchronization signal VD and the 2FH signal are supplied to the sub-synchronization signal generator 124, and the CL / 4 signal is supplied to the high-speed horizontal The synchronization signal is supplied to the synchronization signal generator 125, and the horizontal synchronization signal HD is supplied to the image pickup device 110 as an external synchronization signal EXT-HD via a terminal C21.

 Further, the sub-synchronization signal generation unit 124 generates an external synchronization signal EXT_VD to be supplied to the imaging device 110 from the trigger signal CTRIG, the vertical synchronization signal VD, and the 2FH signal, For example, it is configured as shown in FIG.

 The sub-synchronous signal generation unit 124 shown in FIG. 11 includes an edge detection circuit 200 to which the trigger signal CTRIG and the 2FH signal are supplied, and a 2FH signal to the clock input terminal CLK. It has first to third counters 2 1 1, 2 1 2, 2 13.

The edge detection circuit 200 includes first and second D-type flip-flops 201 and 202 in which the 2FH signal is supplied to a clock input terminal CK, and the first D-type flip-flop. And a NAND gate 203 to which an inverted output of the second D-type flip-flop 202 is supplied, and the above-mentioned trigger signal CTRIG is provided by the first flip-flop 201. It is supplied to the data input terminal D of the D-type flip-flop 201, The non-inverted output of the first D-type flip-flop 201 is supplied to the data input terminal D of the second D-type flip-flop 202. The edge detection circuit 200 having such a configuration detects the rising edge of the trigger signal CTRIG. The detection output of the edge detection circuit 200 is supplied to the load terminal LD of the first counter 211 and to the reset terminal R of the D-type flip-flop 214.

 The first count signal 211 is a 4-bit binary count signal that performs a count-up operation at the rising edge of the 2FH signal. [100] is preset at each rising edge of the trigger signal CTRIG, and is counted up at each rising edge of the 2FH signal. The carry output RC is supplied to the clock input terminal CK of the D-type flip-flop 214. The D-type flip-flop 214 has a logic “H” applied to its data input terminal D, and the detection output of the edge detection circuit 200 is supplied to the reset terminal R. The trigger signal is reset at each rising edge of the trigger signal CTRIG, and the carry output RC of the first counter 211 is used as a clock to latch the logic `` H '' of the data input terminal D and non-inverted The output is supplied to the control input terminals SPE of the second and third power terminals 2 1 2 and 2 13 and the reset terminal R of each D-type flip-flop 2 16 and 2 19 To supply.

The second counter is an 8-bit binary programmable down counter whose control input terminal SPE is logical. The period during which the signal is low, that is, the D-type flip-flop 214 is reset at the rising edge timing t1 of the trigger signal CTRIG, and the first counter 211 Until the logic “H” is output by the carry output RC, [1 0 0 0 1 0 0 0] is preset at the rising edge of the 2FH signal, and then the control input terminal SPE When the signal becomes logic "H", the count is down-counted at each rising edge of the 2FH signal, and the count output CO / CZ is passed through the NAND gate 215 via the NAND gate, and the D-type flip-flop is output. Supplied to the clock input pin CK of step 2 16. The D-type flip-flop 216 has a logic “H” applied to its input terminal D, and the output of the D-type flip-flop 216 corresponds to the reset terminal R. The reset signal is reset at each rising edge of the output of the D-type flip-flop 214, and the inverted signal of the count output CO / CZ of the second counter 212 is reset. As a lock, the logic "H" of the input terminal D is latched, and the inverted output is supplied to one input terminal of the NAND gate 217. The NAND gate 217 has the other input terminal supplied with the non-inverted output of the D-type flip-flop 214, and the non-inverted output of the D-type flip-flop 21 and the above-mentioned input terminal. As a NAND output with the inverted output of the D-type flip-flop 216, the timing of the rising edge of the trigger signal CTRIG shown in Fig. A first vertical synchronization signal VD1 as shown in FIG. 12B is generated.

The output of the NAND gate 217, that is, the first vertical synchronization signal VD1, is connected to one input terminal of each of the NAND gates 221 and 229. As well as to the reset terminal R of the D-type flip-flop 228.

 The third counter 213 is an 8-bit binary programmable down counter, and is a period during which the control input terminal SPE is at the logic “L” level, that is, the D-type free counter. Until the flip-flop 2 14 is reset at the timing t1 of the rising edge of the trigger signal CTRIG and a logic “H” is output by the carry output RC of the first counter 2 11 During this time, [1 0 0 1 0 1 0 0] is preset at the timing of the rising edge of the 2FH signal, and when the control input terminal SPE becomes logic “H”, the 2FH signal rises Down-counting is performed at each edge, and the count output CO / CZ is supplied to the clock input terminal CK of the D-type flip-flop 219 via an inverter 218 using a NAND gate.

 The D-type flip-flop 219 has a logic “H” applied to its input terminal D, and the output of the D-type flip-flop 219 is connected to the reset terminal R. The reset signal is reset at each rising edge of the output of the D-type flip-flop 214, and the inverted signal of the count output CO / CZ of the third counter 211 is supplied. Latches the logic "H" of the data input terminal D and supplies the non-inverted output to the trigger terminal A of the monostable multivibrator 220.

The monostable multi-vibration signal 220 is triggered by the non-inverted output of the D-type flip-flop 219, and as an inverted output thereof, as shown in FIG. 12C, the trigger signal CTRIG of The second vertical synchronization signal VD2 which becomes logic "L" only for 17H period after 20H has elapsed from the rising edge timing t1 is generated. The inverted output of the monostable multivibrator 220, that is, the second vertical synchronizing signal VD2 is supplied to the other input terminal of the NAND gate 221 and the D-type It is supplied to the clock input pin CK of the flip-flop 228.

 The NAND gate 221 is connected to the first vertical synchronizing signal VD1 supplied from the NAND gate 217 and the second vertical synchronizing signal VD1 supplied from the monostable multivibrator 220. The NAND output of the vertical synchronizing signal VD2 is supplied to one input terminal of the NAND gate 223 as a signal VD, as shown in Fig. 12D, via an inverter 222 using a NAND gate.

 In the NAND gate 222, the other input terminal is supplied with the vertical synchronizing signal VD from the synchronizing signal generator 123, and the vertical synchronizing signal VD and the signal VD ′ are connected to each other. A signal VD "as shown in FIG. 12E is generated as a NAND output. The signal VD" generated by the NAND gate 223 is supplied to a D-type signal through an inverter 224 formed by a NAND gate. Supplied to the overnight input terminal D of rip flop 227.

 In the D-type flip-flop 227, the 2FH signal is phase-adjusted by a two-stage monostable multivibrator 225, 226 to a clock input terminal CK, and is supplied as a clock signal. The above signal VD "is latched by this clock signal.

The sub-synchronous signal generator 124 uses the latch output from the D-type flip-flop 227 as an external synchronizing signal EXT-VD. The signal is supplied to the imaging device 110 via the terminal C111.

 Further, in the sub-synchronous signal generating section 124, the D-type flip-flop 228 has a logic “H” applied to its data input terminal D, and is supplied from the NAND gate 217. The first vertical synchronizing signal VD1 is reset at the rising edge of the first vertical synchronizing signal VD1, and the second vertical synchronizing signal VD2 supplied from the monostep multi-vibration unit 220 is used as a clock. The logic "H" of D is latched, and the inverted output is supplied to the other input terminal of the NAND gate 229.

 The NAND gate 229 NANDs the first vertical synchronization signal VD1 supplied from the NAND gate 217 and the NAND output of the inverted output of the D-type flip-flop 228. A gate signal GATE is supplied to the high-speed horizontal synchronization signal generation section 125 through a gate 230 through the gate. As shown in FIG. 12F, the gate signal GATE is changed from the timing of the rising edge of the first vertical synchronization signal VD1 to the timing of the rising edge of the second vertical synchronization signal VD2. It becomes logic "H" only during the period T3 of 17H until t3.

 The high-speed horizontal synchronizing signal generator 125 generates the high-speed horizontal synchronizing signal Hi_HD to be supplied to the imaging device 110 from the CL / 4 signal. It is configured as follows.

The high-speed horizontal synchronizing signal generator 125 shown in Fig. 13 sets the counter 251, where the CL / 4 signal is supplied to the clock input terminal CLK, and the preset value of the counter 251, There is a setting circuit 2 52 to be used. The counter 251 is an 8-bit binary program-counter counter. The control input terminal SPE is at the logic “L” level and the clock input terminal CLK is At the timing of the rising edge of the CL / 4 signal supplied to the controller, the setting value of the setting circuit 25 is preset. After that, when the control input terminal SPE becomes logic "H", the CL / 4 signal is reset. By down-counting at each rising edge, a pulse having a frequency 2 to 7 times the frequency of the horizontal synchronizing signal HD is supplied to one input terminal of the NAND gate 254 as the count output CO / CZ.

 The NAND gate 254 receives the inverted output of the monostable multivibrator 253 triggered by the horizontal synchronizing signal HD, and supplies the inverted output of the monostable multivibrator 253 to the other input terminal. Gate control. Then, the NAND output of the NAND gate 254 is supplied to the NAND gate 256, and the control input of the counter 251 through the inverter 255 by the NAND gate. Supplied to terminal SPE. In the NAND gate 256, the gate signal GATE is supplied to the other input terminal from the sub-synchronization signal generation section 124, and the gate is controlled by the gate signal GATE. I have. The NAND gate 256 is connected to the count output CO / CZ of the counter 251, which is supplied as the NAND output of the NAND gate 254, by the gate signal GATE. The logic "H" is supplied to the trigger input terminal B of the monostable multivibrator 257 for the period T3 of 19H.

This monostable multivibrator 2 5 7 During period T3, the count output CO / C Ζ is triggered at twice the frequency of the horizontal synchronization signal HD, and the inverted output is output as the high-speed horizontal synchronization signal Hi_HD.

 The trigger signal generation 127 shown in FIG. 14A is based on a 50 Hz cycle master / slave vertical synchronization signal MVD compliant with the CCIR method supplied from the synchronization signal generator 13. As shown, a trigger signal CTRIG with a repetition period of 1/1000 second is generated.

 The memory controller 122 controls the writing / reading of the memory based on the trigger signal CTRIG and the synchronization signals VD and HD by the memory controller 122, and the memory controller 122 via the terminal C51. The supplied video signals VIDE01 and VIDE02 are taken in, and the video signals VIDEO1 and VIDEO2 are supplied as still image signals from the terminal C52 to the image processing apparatus.

In the imaging control device 120 having such a configuration, the horizontal synchronization signal HD compliant with the CCIR method generated by the synchronization generation section 123 is supplied to the imaging device 110 as an external horizontal synchronization signal EXT—HD. When the rising edge of the trigger signal CTRIG as shown in FIG. 14A to be supplied to the imaging device 110 is set to a logic “L” for a 9 H period after a lapse of 9 H from the timing t 1. The vertical sync signal VD 1 and the second vertical sync signal VD 2 which becomes logic “L” for only 17 H after 11 H have passed are inserted into the normal vertical sync signal VD conforming to the CCIR method. The sub-synchronous signal generator 124 supplies the external synchronizing signal EXT—VD as shown in FIG. B to the image pickup device 110. Further, FIG. 14C having twice the frequency of the horizontal synchronizing signal HD The high-speed horizontal synchronization signal Hi 1 HD shown in FIG. Supply 1 1 o.

 Then, in the imaging device 110, based on the external synchronization signals EXT—VD, EXT—HD, the high-speed horizontal synchronization signal Hi—HD, and the trigger signal CTRIG supplied from the imaging control device 120. , The modulated vertical synchronization signal TG—VD generated by the sub-synchronization signal generation unit 1 1 1 B and the shutdown control signal X_S UB, and the high-speed horizontal synchronization signal Hi 1 HD selected by the switch circuit 113. The imaging operation by reading all pixels is performed according to the modulated horizontal synchronization signal TG-HD and the modulated horizontal synchronization signal TG-HD.

The video signals VIDE 01 and VIDE 02 obtained by the imaging device 110 are simultaneously read in two lines by a high-speed horizontal synchronization signal Hi-HD having twice the frequency of the horizontal synchronization signal HD conforming to the CCIR method. Therefore, as shown in FIG. 15, a signal of an image for two frames during one field period. Since the frequency of the vertical synchronizing signal VD conforming to the CCIR method is 5.0 Hz, the imaging signal of two frames of images output during one field period is 1/1100 second. The images are captured with a time difference. Therefore, the memory controller 122 in the imaging control device 120 is provided with a 50 Hz period master / slave vertical synchronization signal MVD based on the CCIR method generated by the synchronization signal generator 23. Based on the synchronization signals VD, HD and the trigger signal CTRIG generated by the trigger signal generation section 27, the write control signals MWE N2, MWE N 1 and the read control signals MR EN 2 and MRE 1 as shown in FIG. 14F and FIG. 14G are generated to control the writing / reading of data to / from the memory 12 1. That is, the memory controller 122 captures the video signals VIDE 0 1 and VIDE〇 2 simultaneously read by the imaging device 110 two lines into the memory 122, and reads the first half of the video signal for two frames. The write / read to / from the memory 121 is controlled so that the odd field video signal in one frame and the even field video signal in the second half frame are read.

 As a result, as shown in FIG. 14H, the odd-field video signal and the second half of the first half frame captured with a time difference of 1/1000 seconds are obtained from the memory 12 1. The video signal VIDE 0 for one field is output from the video signal of the even field in the frame. Specifically, a video signal having a 100-Hz period in a 103-line effective video period is output including a blanking period of 11 lines in a 50-Hz sync cycle. Then, the signal adder 128 adds a composite synchronizing signal MCS having a cycle of 50 Hz conforming to the CCIR method to the video signal read from the memory 122 in this way. The video signal VIDE 0 output from the signal adder 1 28 via the terminal C 52 is a video signal compliant with the CCIR system, and the image on the monitor is displayed on the screen as shown in FIG. The video that is exactly 1/1000 second later than the video above is output to the bottom of the screen.

 In this imaging system, a video signal containing an image captured by the imaging device 110 with a time difference of exactly 1/1000 second at the front end and the second half of the screen is obtained from the memory 122. The video signal is supplied to the image processing device 130 as a still image signal.

Here, the video signal read from the memory 1 2 1 is CC Although the scan rate is twice as high as that of the IR system, since a normal CCIR synchronization signal is added by the signal adder 128, it can be recorded on a video tape recorder.

As described above, the imaging control method, the imaging control device, the imaging system, and the imaging device according to the present invention generate the standard vertical synchronization signal and the standard horizontal synchronization signal based on the standard television system, and Based on the trigger signal, a trigger signal with a cycle of 1/2 or less of this standard vertical sync signal is generated, and the first timing according to the trigger signal is used for the first timing. All charges accumulated in the elements are eliminated as invalid charges, and the charges accumulated in the plurality of light receiving elements are transferred to the vertical transfer unit at a second timing after a predetermined time from the first evening. Reading, and vertically transferring the electric charge transferred to the vertical transfer unit at a first transfer speed over a first period from the second timing to the third timing, and Next from mining The vertical transfer is performed at a second transfer rate corresponding to the standard television system, which is slower than the first transfer rate, for a second period until the fourth timing, which is the evening of the trigger signal. The line transfer type solid-state imaging device outputs one frame of image information via the vertical transfer portion for each cycle of the trigger signal by vertically transferring the charge of the portion. Control the device. Then, the image information output from the interline transfer solid-state imaging device during a plurality of cycles of the trigger signal is temporarily stored, and the stored image information of a plurality of frames is synchronized with the standard vertical synchronization. 1 frame of output image information at a speed based on the signal and the standard horizontal synchronization signal. Since a vertical synchronization signal and a standard horizontal synchronization signal are added and output, it is possible to capture an object moving at high speed with a predetermined time difference and to synthesize and output a single image. Therefore, for example, a standard vertical synchronizing signal and a standard horizontal synchronizing signal conforming to the CCIR (International Radio Consultative Committee) method are generated, and a trigger signal having a period of 1/2 of the standard vertical synchronizing signal is generated. By performing the imaging control of the imaging device of the above, an image having a time difference of 1/1100 seconds can be synthesized and output as one image.

 The present invention is applied to, for example, an imaging system having a configuration as shown in FIG. This imaging system is based on the detection output of an object sensor 3 that detects a subject 302 that is transported by a transport path 301 formed of a belt conveyor or the like, and captures the subject 302 based on the detection output. An imaging system for capturing an image as a still image and controlling the operation of the imaging device 10 in accordance with the detection output of the object sensor 303 to output a video signal from the imaging device 310 An imaging control device 320 that captures a still image signal into the memory 321, and an image processing device 330 that receives a video signal from the imaging device 310 as a still image signal via the memory 321 And

 In this imaging system, the object sensor 303 detects the subject 202 transferred by the transfer path 1, and when the subject 302 reaches the front of the object sensor 303, A trigger signal TRIG is generated, and the trigger signal TRIG is supplied to the imaging control device 320.

Further, as shown in FIG. 18, the image pickup device 310 is supplied with external synchronization signals EXT-VD and EXT-HD from the image pickup control device 320 via terminals C 1 and C 2. Synchronization signal generator 3 1 1 A A sub-synchronous signal generator 3 11 B and a gate signal generator 3 1 2 to which a modulation trigger signal MTRIG is supplied from an image controller 3 20 via a terminal C 4, and a gate signal generator 3 1 A switch circuit 3 13 controlled by the gate signal G ATE supplied from 2 and a master clock generator MCK of about 28.6 MHz supplied from the master clock generator 3 14 And a CCD image sensor 317 driven by a CCD drive section 316 which operates according to various timing signals supplied from the timing generator 315. It comprises a process section 319 to which an image signal from the CCD image sensor 317 is supplied via a correlated double sampling (CDS) circuit 318. The above-mentioned CCD image sensor 317 is an interline transfer (IT) type CCD image sensor having a structure as shown in FIG. 19, and a light receiving unit corresponding to each pixel of an odd field. S _0DD and the light receiving section S EVEN corresponding to each pixel in the even field, and the vertical transfer section V from which the charge accumulated in each light receiving section S ODD and S EVEN is read out

_REG, and a horizontal transfer unit H _REQ that outputs the electric charge read out to the vertical transfer unit V _{RE <3} as an image signal per horizontal line unit.

By controlling the potential of a substrate (not shown) formed below S ODD and S EVEN, the electric charge accumulated in each of the light receiving units S ODD and S EVEN is swept away to the substrate and the electric charge is removed. It has an electronic shirt function that controls the storage time.

The synchronizing signal generator 311A is supplied with a clock CL of approximately 14.3 MHz obtained by dividing the master clock MCK into 1/2 from the timing generator 15 and this clock CL Based on In addition to generating internal signals VD and HD, the clock CL is divided by 1/4 to generate a CL / 4 signal with a frequency of about 3.5 MHz. The synchronization signal generator 311A is configured to enable external synchronization. When the external synchronization signal EXT-VD, EXT-HD is supplied to the terminals CI and C2, the external synchronization signal is generated. No. EXT — VD, EXT — Generates internal synchronization signals VD and HD synchronized with HD. Then, the internal synchronization signals VD, HD and CL / 4 generated by the synchronization signal generation section 311A are supplied to the sub-sync signal generation section 311B. Further, the internal synchronization signals VD and HD are supplied to the gate signal generator 312 and the process section 319.

 The sub-synchronous signal generation section 311B is provided by changing the pulse width of a trigger signal TRIG as shown in FIG. 2OA, for example, a modulated trigger signal as shown in FIG. 20B. MT RIG is supplied to the terminal C4. The sub-synchronization signal generation section 311 B uses the modulation vertical synchronization signal TG as shown in FIG. 20D based on the rising timing t1 of the modulation trigger signal MTR IG supplied to the terminal C4. — Generates VD and stops the electronic shutdown control signal X—SUB as shown in Figure 20C for a period T1 corresponding to the preset shutdown speed based on this modulated vertical synchronization signal TG—VD. In addition, the modulated horizontal synchronizing signal is the CL / 4 signal for the predetermined period T2 after the elapse of the period T1 and the internal horizontal synchronizing signal HD conforming to the standard television system except for the periods T1 and T2. TG—Generate HD.

The modulated vertical synchronizing signal TG-VD generated by the sub synchronizing signal generator 311B is supplied to the timing generator 315. The modulated horizontal synchronizing signal TG-HD is supplied to the switch circuit 313, and the electronic shirt evening control signal X-SUB is supplied to the CCD drive section 316. ing.

 In addition, the gate signal generation section 312 counts 16 internal horizontal synchronization signals HD based on the rising edge timing t1 of the modulation trigger signal MT RIG supplied to the terminal C4. After the lapse of the 16 H period, a gate signal GATE as shown in FIG. 20F, which becomes a logic “H” for a predetermined period T 3 (the 21 H period here) of the period T 2, is generated. The gate signal GATE generated by the gate signal generation section 312 is supplied to the switch circuit 313.

 Further, the switch circuit 313 is connected to the high-speed horizontal synchronizing signal Hi having a frequency of 2 to 7 times the horizontal synchronizing frequency fH in the standard television system via the terminal C4 from the imaging control device 320. HD is supplied and the high-speed horizontal synchronizing signal Hi-HD is selected only for the period T3 during which the gate signal GATE becomes logic "H", and during periods other than the period T3 The modulation horizontal synchronizing signal TG-HD supplied from the sub synchronizing signal generator 311B is selected. The modulated horizontal synchronizing signal TG-HD 'as shown in FIG. 20G comprising the high-speed horizontal synchronizing signal Hi-HD and the modulated horizontal synchronizing signal TG-HD selected by the switch circuit 3 13 Mining generator 3 15.

Further, the timing generator 315 includes the modulated vertical synchronization signal TG—VD supplied from the sub-synchronization signal generation section 311B and the high-speed horizontal synchronization signal H selected by the switch circuit 313. i- Based on the HD and the modulated horizontal synchronization signal TG_HD, various timing signals necessary for driving the CCD image sensor 317 are generated and supplied to the CCD drive section 316.

 In addition, the CCD drive section 316 generates the sensor gate signal SG, the reset signal, the horizontal transfer pulse, and the vertical signal shown in FIG. 20E based on the various timing signals and the electronic shutdown control signal X—SUB. A drive pulse such as a transfer pulse is generated to drive the CCD image sensor 317.

 The CDS circuit 318 performs so-called correlated double sampling based on a sampling pulse supplied from the timing generator 315 with respect to the imaging signal read out from the CCD image sensor 317 simultaneously by two lines. To extract the information component of the imaging signal and remove noise such as reset noise contained in the imaging signal.

Then, the processing section 319 performs predetermined processing such as gamma correction on the imaging signal supplied from the CDS circuit 318. A video signal VIDE 0 as shown in FIG. 20H output from the process section 3 19 is supplied to the imaging control device 320 via the terminal C 5. The imaging control device 320 is provided with a memory 321, to which the video signal VIDE 0 obtained by the imaging device 310 is supplied via a terminal C51, and a data readout for the memory 3221. Equipped with a memory controller 322 that controls writing / reading. Further, the imaging control device 320 includes a synchronization signal generation section 32 3, a sub synchronization signal generation section 32 4, a high-speed horizontal synchronization signal generation section 32 5, a master clock generator 32 26 and a pulse width. Equipped with a variable setting section 327, the detection output of the object sensor 303 The trigger signal TRIG obtained as a force is supplied to the pulse width variable setting section 327 via the terminal C20. The pulse width variable setting section 327 arbitrarily sets the pulse width of the trigger signal TRIG supplied to the terminal C20, and a specific configuration example is shown in FIG. As shown in the figure, a time constant circuit consisting of a mono-multi vibrator 3 27 A, a semi-fixed resistor 1 27 a and a capacitor 3 27 b connected to this mono-multi bilayer 3 27 A It consists of B. As shown in FIG. 22, the pulse width variable setting unit 327 is configured to output the monomultivibration signal 327 A by the trigger signal TRIG from the object sensor 303 as shown in FIG. Time constant circuit Generates a modulated trigger pulse signal MTRIG with a pulse width W according to the time constant of 327B. The pulse width W of the modulation trigger signal MT RIG according to the time constant of the time constant circuit 327 B can be continuously and variably set by the semi-fixed resistor 327 a.

 Then, the modulation trigger signal MT RIG is supplied to the memory controller 32 2 and the sub-synchronous signal generation section 324 and from the terminal C 41 to the imaging device 3 10. I have.

In the imaging control device 320, the synchronizing signal generator 3 23 generates a synchronizing signal VD, based on a main clock MCK of about 28.6 MHz supplied from the main clock generator 326. HD and the horizontal sync signal 2FH signal of twice the frequency of the HD and the master clock M〇1 <are frequency-divided by 1/4 (1 ^ / 4 signal is generated. Synchronization signal generator The synchronization signals VD and HD generated by 3 2 3 are supplied to the memory controller 32 2, and the vertical synchronization signals VD and 2 FH signals are supplied to the sub-sync signal generation section 324. , Also, The CL / 4 signal is supplied to the high-speed horizontal synchronizing signal generator 3 25, and the horizontal synchronizing signal HD is supplied to the image pickup device 310 as an external synchronizing signal EXT—HD via a terminal C 21. It is being supplied.

 The sub-synchronous signal generating section 324 generates an external synchronizing signal EXT-VD to be supplied to the image pickup device 310 from the modulated trigger signal MTRIG, the vertical synchronizing signal VD and the 2FH signal. Thus, for example, it is configured as shown in FIG.

 The sub-synchronous signal generator 324 shown in FIG. 23 includes an edge detection circuit 400 to which the modulation trigger signal MTRIG and the 2 FH signal are supplied, and a 2 FH signal to the clock input terminal CLK. First to third counties 4 1 1, 4 1 1 2 and 4 1 3 are provided.

The edge detection circuit 400 includes first and second D-type flip-flops 401 and 402 in which the 2FH signal is supplied to a clock input terminal CK, and the first D-type flip-flop. A non-inverted output of the flip-flop 401 and a NAND gate 43 to which an inverted output of the second D-type flip-flop 402 is supplied, and the modulation trigger signal MTR IG Is supplied to the data input terminal D of the first D-type flip-flop 401, and the non-inverted output of the first D-type flip-flop 401 is supplied to the second D-type flip-flop 402. It is supplied to data input terminal D. The edge detection circuit 400 having such a configuration detects a rising edge of the modulation trigger signal MTRIG. The detection output of the edge detection circuit 400 is supplied to the load terminal LD of the first counter 411 and to the reset terminal R of the D-type flip-flop 414. Is done. The first count 411 is a 4-bit binary count that performs a count-up operation at the rising edge of the 2FH signal, and the detection output of the edge detection circuit 400 is the load By supplying the signal to the terminal LD, [100] is preset at each rising edge of the above-mentioned modulated trigger signal TRIG, up-counted at each rising edge of the above-mentioned 2FH signal, and the carry output RC is output. Is supplied to the clock input terminal CK of the D-type flip-flop 414.The logic `` H '' is given to the input terminal D of the D-type flip-flop 414. When the detection output of the detection circuit 400 is supplied to the reset terminal R, it is reset at each rising edge of the modulation trigger signal MTRIG, and the capacitance of the first power source 411 is reset. Lead output RC The logic "H" of the data input terminal D is latched as a clock, and its non-inverted output is supplied to the control input terminals SPE of the second and third counters 4 1 2 and 4 13 together. Supply to the reset terminal R of each D-type flip-flop 416, 419.

The second count 412 is an 8-bit binary programmable down count, and is a period during which the control input terminal SPE is at the logic “L”, that is, the D-type flip-flop. Step 4 14 is reset at the timing t1 of the rising edge of the modulation trigger signal MTRIG, and until the logic `` H '' is output by the carry output RC of the first counter 4 11 1. [1 0 0 0 1 0 0 0] is preset at the timing of the rising edge of the above 2FH signal, and then when the control input terminal SPE becomes logic “H”, every rising edge of the above 2FH signal Downcount and count The output C0 / CZ is supplied to the clock input terminal CK of the D-type flip-flop 416 via an inverter 415 using a NAND gate.

 The D-type flip-flop 416 has a logic “H” applied to its input terminal D, and the output of the D-type flip-flop 414 is connected to the reset terminal R. By being supplied, it is reset at the rising edge of the output of the D-type flip-flop 414, and the inverted signal of the count output CO / CZ of the second count 412 is used as a clock. The logic “H” of the input terminal D is latched and the inverted output is supplied to one input terminal of the NAND gate 417. In the NAND gate 417, the non-inverted output of the D-type flip-flop 414 is supplied to the other input terminal, and the non-inverted output of the D-type flip-flop 414 is supplied. As a NAND output of the inverted output and the inverted output of the D-type flip-flop 4 16 described above, the logic is generated only for 9 H period after 7 H from the rising edge timing tl of the modulation trigger signal MT RIG shown in Fig. The first vertical synchronizing signal VD1 as shown in FIG. 24B which becomes "L" is generated.

 The output of the NAND gate 417, that is, the first vertical synchronizing signal VD1, is supplied to one input terminal of each of the NAND gates 421 and 429, and the D-type flip-flop. Supplied to the reset terminal R of 428.

The third counter 413 is an 8-bit binary programmable down counter, and is a period during which the control input terminal SPE is at the logic “L”, that is, the D-type free switch. The flip-flop 4 1 4 is the timing of the rising edge of the above-mentioned modulated trigger signal MTRIG. Reset at t1, and until the logic “H” is output by the first output RC of the first counter 4 1 1 and output RC, the timing of the rising edge of the above 2FH signal is [1 0 0 1 0 1 0 0] is preset, and when the control input terminal SPE goes to logic “H”, the countdown CO / CZ is counted down by the NAND gate at every rising edge of the 2FH signal. It is supplied to the clock input pin CK of the D-type flip-flop 419 via the inverter 418.

 The D-type flip-flop 419 has a logic “H” applied to its input terminal D, and the output of the D-type flip-flop 414 is connected to the reset terminal R. By being supplied, it is reset at the rising edge of the output of the D-type flip-flop 414, and the inverted signal of the count output CO / CZ of the third counter 413 is clocked. As a result, the logic “H” of the input terminal D is latched, and the non-inverted output is supplied to the trigger terminal A of the monostep multivibrator 420.

The monostable multivibrator unit 420 is triggered by the non-inverted output of the D-type flip-flop 419, and as the inverted output, as shown in FIG. The second vertical synchronizing signal VD2 which becomes logic "L" for 9H period after 28H has elapsed from the rising edge timing t1 of the rigger signal MT RIG is generated. The inverted output of the monostable multi-bi-plane signal 420, that is, the second vertical synchronizing signal VD2 is supplied to the other input terminal of the NAND gate 121 and the D-type flip-flop is provided. It is supplied to clock input terminal CK of 128. The NAND gate 421 includes a first vertical synchronizing signal VD1 supplied from the NAND gate 417 and a second vertical synchronizing signal VD1 supplied from the monostable multi-multiplexer 420. The NAND output of the vertical synchronizing signal VD 2 is supplied to one input terminal of the NAND gate 423 as a signal VD ′ as shown in FIG. 24D via an inverter 422 using a NAND gate.

 The NAND gate 4 23 is a pulse output from the monostable multi-bi-layer 4 0 5 which is output to the other input terminal at the timing t 5 of the falling edge of the modulation trigger signal MTRIG. A signal is supplied, and a signal VD "as shown in FIG. 24E is generated as a NAND output of the pulse signal and the signal VD '. <The signal VD" generated by the NAND gate 4 23 is The data is supplied to the data input terminal D of the D-type flip-flop 127 through the inverter 424 by the NAND gate.

 In the D-type flip-flop 422, the 2FH signal is phase-adjusted by a two-stage monostable multivibrator 425, 426 to its clock input terminal CK and supplied as a clock signal. The signal VD "is latched by this clock signal.

 Then, the sub-synchronous signal generating section 324 supplies the latch output by the D-type flip-flop 127 as the external synchronizing signal EXT-VD to the image pickup device 310 via the terminal C11.

Further, in the sub-synchronous signal generating section 324, the D-type flip-flop 428 has a logic “H” applied to its data input terminal D, and the first flip-flop 428 supplied from the NAND gate 4 17 Reset at the rising edge of the vertical sync signal VD1 The logic “H” of the data input terminal D is latched by using the second vertical synchronization signal VD 2 supplied from the multi-vibrator 420 as a clock, and the inverted output is output to the NAND gate 4. 2 Supply to the other input terminal of 9.

 The NAND gate 429 outputs the first vertical synchronizing signal VD1 supplied from the NAND gate 417 and the NAND output of the inverted output of the D-type flip-flop 428. The signal is supplied to the high-speed horizontal synchronization signal generation section 325 as a gate signal GATE via an inverter 430 using a NAND gate. The gate signal GATE is, as shown in FIG. 24F, from the timing of the rising edge of the first vertical synchronization signal VD1 to the timing of the rising edge of the second vertical synchronization signal VD2. Becomes logic "H" only during the period T3 of 21H.

 The high-speed horizontal synchronizing signal generation section 3 25 generates the high-speed horizontal synchronizing signal Hi_HD to be supplied to the imaging device 10 from the CL / 4 signal, as shown in FIG. The configuration is the same as that of the high-speed horizontal synchronization signal generator 125 shown.

 The memory 3221 is controlled by the memory controller 3222 to write / read data based on the modulation trigger signal MT RIG and the synchronization signals VD and HD. The video signal VIDE 0 supplied through the terminal is taken in, and this video signal is supplied as a still image signal from a terminal C 52 to the image processing apparatus.

In the imaging control device 320 having such a configuration, the horizontal synchronization signal HD compliant with the standard television system generated by the synchronization generation section 3233 is excluded. When the object sensor 303 detects the subject 302 on the transfer path 1 and generates a trigger signal TRIG, the trigger signal is output. A trigger signal TRIG is supplied to the imaging device 310, and the first vertical signal which becomes logic "L" for only 9H period after a lapse of 7H from the rising edge timing t1 of the trigger signal TRIG. Synchronization signals VD 1 and 28 External synchronization signal EXT—VD, in which second vertical synchronization signal VD 2 that becomes logic “L” for only 9 H after 8 H has been inserted into vertical synchronization signal VD of the standard television system, The sub-synchronization signal generator 324 supplies the imaging device 310 with the high-speed horizontal synchronization signal Hi-HD having a frequency 2 to 7 times the frequency of the horizontal synchronization signal HD. The generating section 3 25 supplies the image to the imaging device 3 10.

 Then, in the imaging device 310, the external synchronization signals EXT—VD, EXT—HD, the high-speed horizontal synchronization signal Hi-HD, and the modulation trigger signal MTRIG supplied from the imaging control device 320 are provided. The modulated vertical synchronizing signal TG_VD and the shutdown control signal X—SUB generated by the sub synchronizing signal generator 311 B, and the high-speed horizontal synchronizing signal Hi 1 selected by the switch circuit 3 13 HD and modulated horizontal sync signal TG—Performs imaging operation in accordance with the modulated horizontal sync signal TG—HD 'consisting of HD.

Here, the CCD image sensor 317 in the image pickup device 310 requires one cycle of the vertical transfer operation, that is, about 8.3〃s to send one image pickup charge. Since the number of vertical transfer operation cycles that can be performed in the H period, that is, 63.556 / s, is limited to 7.66, that is, 7 cycles, the high-speed horizontal synchronization signal Hi 1 The HD frequency is 2 to 7 times the frequency of the horizontal synchronizing signal HD ₍ and the period T3 during which the high-speed horizontal synchronizing signal Hi-HD is inserted is 21H. vertical transfer cycle, the high Hayami horizontal sync signal frequency of the H i one HD becomes 2 1 x 2 = 42 cycles when 2 f H, also when the frequency of the high-speed horizontal synchronizing signal H i _HD is 7 f _H 2 1 x 7 = 147 cycles.

 That is, when the frequency of the high-speed horizontal synchronizing signal Hi-HD is 2 fH, as shown by hatching in FIG. 25, the upper part of the imaging surface of the CCD image sensor 317 during the period T3. Is read out for 42 lines. Then, since the reading of the above-mentioned 42 lines has been completed at the end of the period T3, a normal image pickup signal is read from the line of the first storage after returning to the normal cycle.

 When the frequency of the high-speed horizontal synchronizing signal Hi-HD is 7 f „, as shown by hatching in FIG. 26, during the period T3, the CCD image sensor 3 17 147 lines are read from the upper part of the imaging surface, and since the reading of 147 lines has been completed at the end of the period T3, after returning to the normal cycle, the line from the first line is returned. A normal imaging signal is read.

Thus, by varying the frequency of the high-speed horizontal synchronization signal Hi-HD, the position of the video to be shot can be freely set. That is, in the imaging device 310, an in-line one-line transfer type CCD image sensor 317 having an electronic shirt function in accordance with the modulated trigger signal MTRIG generated based on the trigger signal TRIG. Stops the sweeping of the electric charge to the electric charge sweeping section for a predetermined time T1, and after the elapse of the predetermined time T1, the imaging electric charge accumulated in the light receiving section becomes an effective electric charge. After reading the image charge read to the vertical transfer unit VREG for a predetermined number of transfer cycles at high speed, the timing t5 of the trailing edge of the modulated trigger signal MTR IG is read. Perform vertical transfer up to the standard television system. Then, the effective charge excluding the imaging charge of a predetermined number of lines by the high-speed vertical transfer is converted into an imaging signal for the number of lines corresponding to the pulse width of the modulation trigger signal MT RIG. The data is output via the horizontal transfer unit HR EG by transfer. As a result, the electronic shutter function of the above-mentioned in-line transfer type CCD image sensor 317 is used to perform an imaging operation using a high-speed random shirt synchronized with the above-mentioned trigger signal TRIG. Necessary effective charges after the line can be obtained as an imaging signal.

 In this imaging system, the CL / 4 signal is counted in the high-speed horizontal synchronizing signal generation section 325 of the imaging control device 320. The preset given to the counter 251 shown in FIG. The high-speed horizontal synchronizing signal Hi-HD having a frequency 2 to 7 times the horizontal synchronizing signal HD is generated by changing the default value in the circuit 25, and the image is supplied to the imaging device 10 to take a picture. The starting horizontal line position of the desired image can be set freely.

 The size of the image to be taken is determined by the falling edge of the above-mentioned modulated trigger signal MT RIG indicating the image end evening t5 in FIG. That is, the period from the timing of the falling edge of the gate signal GATE to the falling edge of the modulated trigger signal MTRIG is the video size.

Here, for example, as shown in FIG. 27, the gate signal GATE If 100 lines are transferred during the period T3 and the video size is set to 100 lines, about 50 lines will be left untransferred at the time of video output, but during the next gate signal GAT #に Since the data is transferred in a form that overlaps the first 100 lines on Τ3, it does not affect the video signal of the part you want to shoot.

 In addition, the number of lines in which the transfer remainder generated at the time of the video output does not affect the video signal of the portion to be shot is determined by the number of transfer cycles in the period Τ3 of the gate signal GA Τ 、, and When transferring 100 lines during the period T3 of the signal GATE, the number of lines is up to 100 lines. That is, the video size can be reduced to 50 lines as shown in FIG.

 Therefore, by setting the pulse width of the modulated trigger signal MT RIG indicating the video end timing, the video size can be freely set in the range of 50 lines to 150 lines.

 On the other hand, the trigger cycle is determined by the vertical synchronization signal VD indicating the video end timing, and can be shortened immediately after the timing of the vertical synchronization signal VD. As shown in Fig. 29, if n = l, the imaging operation with a cycle of 1/5. 6 compared to the cycle in the standard television system (262.5 lines: EIA) with N = 47 lines It is possible to do so.

 The reason for setting two vertical synchronizing signals VD after the trigger is to match the operation of the actual integrated circuit due to the configuration problem of the sub-synchronous signal generator.

Also, in this imaging system, the frequency of the high-speed horizontal synchronization signal Hi-HD is varied as described above, so that the starting horizontal position of the video to be shot is obtained. Since the line position can be set freely, the subject 2 whose position L ≠ L 'on the screen fluctuates as shown in FIGS. 30A and 30B is shown in FIG. 31A. As shown in FIG. 31B, it is possible to automatically correct L = L ′ so that the video signal can always be output at the same timing.

 To do this, the high-speed horizontal synchronizing signal generator 3 25 of the imaging controller 3 20 is replaced with a setting circuit 2 52 that manually sets the preset value of the counter 25 1, as shown in FIG. A setting circuit 4 52 having a configuration as shown in FIG. 2 may be used.

 The setting circuit 4 52 shown in Fig. 32 consists of a sawtooth signal generator 471, a sample pulse generator 472, a sample and hold circuit 473, a voltage comparator 474, and an A / D converter. 4 7 5

As shown in FIG. 33, the sawtooth wave signal generator 471, the invertors 481, 482, the D flip-flop circuits 483, 484, 485, and the sawtooth wave generation circuit It is composed of 4 8 6. The sawtooth wave signal generator 471 resets the D-type flip-flop circuit 483 via a modulated trigger signal TRIG as shown in FIG. A vertical synchronizing signal VD "as shown in FIG. 34B is supplied to each of the clock terminals CK of the D flip-flop circuits 483 and 484. The synchronization signal VD "is supplied to each clock terminal CK of the D flip-flop circuit 485 via the inverter 482. In the D flip-flop circuits 483, 484, and 485, a logic “H” power is supplied to each data terminal D. The output terminal Q of the D flip-flop circuit 48 3 is connected to the reset terminal R of the D flip-flop circuit 4 84, and the D flip-flop The output terminal Q of the flip-flop circuit 4 8 4 is connected to the reset and the sort terminal R of the D flip-flop circuit 4 85 and the trigger terminal T of the sawtooth wave generating circuit 4 8 6. The output terminal Q of the circuit 485 is connected to the reset terminal R of the sawtooth wave generation circuit 186.

 In the sawtooth signal generator 471, having such a configuration, every time the modulation trigger signal MTRIG is supplied, the sawtooth wave signal generator 471, over the entire imaging period corresponding to the image size based on the vertical synchronization signal VD ", A sawtooth signal SW as shown in Fig. 34C is generated, and the sawtooth signal SW generated by the sawtooth signal generator 471 is supplied to the sample and hold circuit 473.

 Further, when a video signal as shown in FIG. 34D is supplied, the sample pulse generator 472 detects the edge of the video signal of the subject with respect to this video signal. A sample pulse SP is generated as shown in FIG. 34E, which indicates where in the frame of the captured image 20 is located. The sample pulse SP generated by the sample pulse generator 472 is supplied to the sample hold circuit 473.

 The sample hold circuit 473 samples and holds the sawtooth signal supplied from the sawtooth signal generator 471 with the sample pulse SP supplied from the sample pulse generator 472. You. The hold output from the sample and hold circuit 473 is supplied to the voltage comparator 474.

Further, the voltage comparator 474 compares the hold output of the sample hold circuit 473 with a reference voltage. The comparison output from the voltage comparator 475 is supplied to the A / D converter 475. Then, the A / D converter 475 converts the signal level of the comparison output from the voltage comparator 474 into an 8-bit digital value, and uses this digital value as a preset value in the high-speed operation. This signal is given to the counter 2 5 1 of the horizontal sync signal generator 3 2 5.

 In the setting circuit 452 having such a configuration, when the timing of the subject 302 is too early from the start of imaging, the voltage of the hold output by the sample-hold circuit 473 becomes low, and the voltage of the voltage comparator 4 The comparison output by 7 4 rises. The 8-bit digital signal value obtained by digitizing the signal level of the comparison output by the voltage comparator 474 by the A / D converter 475 as a preset value is used as the high-speed horizontal synchronization signal generator. By presetting to the count 25 of 25, the phase of the subject is delayed from the timing of the start of imaging, and approaches the saw-tooth waveform signal SW. Conversely, if the evening of the subject 302 is too late from the imaging start, the voltage of the hold output by the sample and hold circuit 473 becomes high, and the comparison output by the voltage comparator 474 is output. Drops. The 8-bit digital value obtained by digitizing the signal level of the comparison output by the voltage comparator 474 with the A / D converter 475 as a preset value is used as the preset value of the high-speed horizontal synchronizing signal generator 3. By presetting to the count 25 of 25, the phase of the subject approaches the timing of the start of imaging and approaches the timing of the sawtooth wave signal SW.

Therefore, by setting the reference voltage V _z to be applied to the voltage comparator 475 to a voltage obtained by the sensing of the sawtooth signal SW, the subject is always set to the video signal by the setting circuit. Can be brought to the center. In this way, a sampling pulse SP is created by using a part of the video signal, and the position of the subject 302 in the imaging unit is detected, whereby the high-speed horizontal synchronizing signal Hi 1 during the gate period T3 is detected. By controlling the HD frequency, it is possible to automatically correct the subject 2 so that it is always output at the same timing on the video signal.

Claims

The scope of the claims

1. A plurality of light-receiving elements that generate and accumulate charges corresponding to the amount of incident light and that are arranged in a matrix, and transfer the charge read from each light-receiving element in the light-receiving section. An imaging control method for an imaging apparatus provided with an inter-line transfer type solid-state imaging device, comprising: a vertical transfer section that performs transfer, and a horizontal transfer section that outputs electric charges transferred via the vertical transfer section. ,

 (a) generating a standard vertical synchronization signal and a standard horizontal synchronization signal conforming to the standard television system;

 (b) a step of generating a trigger signal having a period equal to or less than 1/2 of the standard vertical synchronization signal based on the standard vertical synchronization signal;

(c) All charges accumulated in the plurality of light receiving elements are eliminated as invalid charges at the first evening according to the trigger signal, and the second evening after a predetermined time from the first evening is reached. The charges accumulated in the plurality of light receiving elements are read out to the vertical transfer unit at the timing of the above, and the charge is read out to the vertical transfer unit over the first period from the second timing to the third timing. The transferred charge is vertically transferred at a first transfer rate, and the above-described charge is transferred over a second period from the third evening to the fourth timing that is the timing of the next trigger signal. By vertically transferring the charges of the vertical transfer section at a second transfer rate corresponding to the standard television system, which is slower than the first transfer rate, the cycle of the trigger signal is transmitted via the vertical transfer section every cycle of the trigger signal. To output one frame of image information Controlling an interline transfer solid-state image sensor; (d) a step of temporarily storing the image information output from the in-line transfer type solid-state imaging device during a plurality of cycles of the trigger signal;

 (e) reading out the stored image information of a plurality of frames as output image information of one frame at a speed based on the standard vertical synchronization signal and the standard horizontal synchronization signal;

 (f) adding a standard vertical synchronizing signal and a standard horizontal synchronizing signal of the standard television system to the read one frame of output image information;

 An imaging control method, comprising:

 2. In the above step (a), a standard vertical synchronizing signal and a standard horizontal synchronizing signal conforming to the CCIR (International Radio Consultative Committee) method are generated. In the above step (b), 1/11 of the standard vertical synchronizing signal is generated. 2. The imaging control method according to claim 1, wherein a trigger signal having two periods is generated.

 3. A plurality of light receiving elements that generate and accumulate electric charge according to the amount of incident light and that are arranged in a matrix, and transfer the electric charge read from each light receiving element of the light receiving element. An imaging control device for controlling an imaging device including an inline-line transfer type solid-state imaging device having a vertical transfer unit and a horizontal transfer unit that outputs charges transferred via the vertical transfer unit, ,

 Synchronizing signal generating means for generating a standard vertical synchronizing signal and a standard horizontal synchronizing signal conforming to a standard television system, and outputting the standard horizontal synchronizing signal to the imaging device;

Based on the standard vertical sync signal, less than 1/2 of the vertical sync signal Trigger signal generating means for generating a trigger signal of a lower cycle and outputting the trigger signal to the imaging device;

 All charges accumulated in the plurality of light receiving elements are eliminated as invalid charges at the first evening according to the trigger signal, and the second timing is performed a predetermined time after the first evening. Then, the electric charges accumulated in the plurality of light receiving elements are read out to the vertical transfer unit, and transferred to the vertical transfer unit for a first period from the second timing to the third timing. Vertically transferred at the first transfer rate, and the first charge is transferred over the second period from the third timing to the fourth timing, which is the timing of the next trigger signal. The vertical transfer of the charges of the vertical transfer unit at a second transfer speed corresponding to the standard television system, which is slower than the transfer speed of In order to output one frame of image information, Imaging device control means for controlling the transfer line solid-state imaging device;

 It has a storage capacity to store multiple frame images, and temporarily stores the image information output from the inline transfer type solid-state imaging device during a plurality of periods of the trigger signal. Reading means for reading image information of a plurality of frames stored in the storage means as output image information of one frame at a speed based on the standard vertical synchronization signal and the standard horizontal synchronization signal;

Output means for adding a standard vertical synchronizing signal and a standard horizontal synchronizing signal of the standard television system to one frame of output image information read by the reading means, and outputting the added information. Imaging control device.

4. The imaging device control means generates a sub-vertical synchronization signal for providing a second evening based on the timing of the leading edge of the trigger signal, and transmits the sub-vertical synchronization signal to the imaging device. A sub-synchronization signal generating means to be output, and a high-speed horizontal synchronization signal for generating a high-speed horizontal synchronization signal having a frequency twice as high as the standard horizontal synchronization signal in the first period and outputting the high-speed horizontal synchronization signal to the imaging device The imaging control device according to claim 3, further comprising a generation unit.

 5. The synchronizing signal generating means generates a standard vertical synchronizing signal and a standard horizontal synchronizing signal conforming to the CCIR method, and the trigger signal generating means generates a trigger signal having a half cycle of the standard vertical synchronizing signal. The imaging control device according to claim 3, wherein the imaging control device is generated.

6. A plurality of light-receiving elements that generate and accumulate electric charges according to the amount of incident light and that are arranged in a matrix, and transfer the electric charges read from each light-receiving element of the light-receiving elements. An imaging device including an inter-line transfer type solid-state imaging device having a vertical transfer unit, and a horizontal transfer unit that outputs charges transferred via the vertical transfer unit; and a standard vertical device conforming to a standard television system. A synchronizing signal generating means for generating a synchronizing signal and a standard horizontal synchronizing signal, and outputting the standard horizontal synchronizing signal to the image pickup apparatus; and A trigger signal generating means for generating a trigger signal having a period, and outputting the trigger signal to the imaging device; and storing the trigger signal in the plurality of light receiving elements at a first evening according to the trigger signal. The charge accumulated in the plurality of light receiving elements is read out to the vertical transfer unit at a second timing after a predetermined time from the first evening, and is read out to the vertical transfer unit. Third evening from timing The charge transferred to the vertical transfer unit is vertically transferred at a first transfer rate over a first period until timing, and the third trigger signal is the timing of the next trigger signal from the third timing. By vertically transferring the charges of the vertical transfer unit at a second transfer speed corresponding to the standard television system, which is slower than the first transfer speed, for a second period until the timing of 4, Image sensor control means for controlling the in-line transfer type solid-state image sensor so as to output one frame of image information via the vertical transfer unit for each cycle of the trigger signal; Storage means having a storage capacity for storing frame images, and for temporarily storing the image information output from the interline transfer type solid-state imaging device during a plurality of cycles of the trigger signal; When, Reading means for reading out the image information of a plurality of frames stored in the storage means as output image information of one frame at a speed based on the standard vertical synchronizing signal and the standard horizontal synchronizing signal, and the reading means. An imaging control device comprising: an output means for adding a standard vertical synchronizing signal and a standard horizontal synchronizing signal of the standard television system to one frame of output image information and outputting the same

 An imaging system comprising:

 7. The imaging device control means of the imaging control device generates a sub-vertical synchronization signal based on the trigger signal, and outputs the sub-vertical synchronization signal to the imaging device. High-speed horizontal synchronizing signal generating means for generating a high-speed horizontal synchronizing signal having a frequency twice as high as that of a standard horizontal synchronizing signal in the first period, and outputting the high-speed horizontal synchronizing signal to the imaging device. The imaging system according to claim 6.

8. The above-mentioned imaging control device uses the above-mentioned synchronization signal generating means to perform Generating a standard vertical synchronizing signal and a standard horizontal synchronizing signal compliant with the standard system, and generating a trigger signal having a half period of the standard vertical synchronizing signal by the trigger signal generating means. 6. The imaging system according to 6.

 9. A plurality of light-receiving elements that generate and accumulate electric charges according to the amount of incident light and that are arranged in a matrix, and transfer the electric charges read from each light-receiving element of the light-receiving elements. An interline transfer type solid-state imaging device including: a vertical transfer unit; and a horizontal transfer unit that outputs charges transferred via the vertical transfer unit.

 A standard synchronizing signal generating means for generating a standard vertical synchronizing signal and a standard horizontal synchronizing signal conforming to a standard television system;

 Trigger signal generating means for generating a trigger signal having a cycle equal to or less than 1/2 of the vertical synchronization signal based on the standard vertical synchronization signal;

All charges accumulated in the plurality of light receiving elements are eliminated as invalid charges at the first evening according to the trigger signal, and the second timing is performed a predetermined time after the first evening. The electric charges accumulated in the plurality of light receiving elements are read out to the vertical transfer unit at a time, and transferred to the vertical transfer unit over a first period from the second timing to the third timing. The charges are vertically transferred at a first transfer rate, and the first charge is transferred over a second period from the third timing to the fourth timing, which is the timing of the next trigger signal. By vertically transferring the charges of the vertical transfer unit at a second transfer speed that is slower than the transfer speed and corresponds to the standard television system, one cycle of the trigger signal is transmitted via the vertical transfer unit at each cycle of the trigger signal. In order to output the image information of the frame, - imaging element control means for controlling the line transfer type solid-state imaging device When,

 It has a storage capacity for storing images of a plurality of frames, and temporarily stores the image information output from the in-line transfer type solid-state imaging device during a plurality of periods of the trigger signal. Storage means for storing; read means for reading out image information of a plurality of frames stored in the storage means as output image information of one frame at a speed based on the standard vertical synchronization signal and the standard horizontal synchronization signal;

 Output means for adding a standard vertical synchronizing signal and a standard horizontal synchronizing signal of the standard television system to one frame of output image information read by the reading means, and outputting the added information. Imaging device.

 10. The image sensor control means generates a sub-vertical synchronization signal based on the trigger signal, outputs the sub-vertical synchronization signal to the imaging device, and outputs the standard horizontal synchronization signal. A high-speed horizontal synchronization signal generating means for generating a high-speed horizontal synchronization signal having a frequency twice as high as that of the signal in the first period, and outputting the high-speed horizontal synchronization signal to the imaging device. 9. The imaging device according to 9.

 1 1. The synchronizing signal generating means generates a standard vertical synchronizing signal and a standard horizontal synchronizing signal conforming to the CCIR method, and the trigger signal generating means has a cycle of 1/2 of the standard vertical synchronizing signal. 10. The imaging device according to claim 9, wherein the imaging device generates a trigger signal.

1 2. Generate and accumulate electric charge according to the amount of incident light. A light-receiving unit in which a plurality of light-receiving elements are arranged in a matrix, and transfer the electric charge read from each light-receiving element of the light-receiving unit. A vertical transfer unit, and a horizontal transfer unit that outputs charges transferred through the vertical transfer unit. A drive control method for a line transfer type solid-state imaging device, comprising:

 (a) generating a second trigger signal having a pulse width variably set by a user based on the first trigger signal;

(b) In the second timing based on the first timing, which is the timing of the leading edge of the second trigger signal, all charges accumulated in the plurality of light receiving elements are eliminated as invalid charges. Steps to

 (c) reading out the charges accumulated in the plurality of light receiving elements to the vertical transfer unit at a third timing after a predetermined time from the second timing;

 (d) a step of vertically transferring the charges transferred to the vertical transfer unit at a first transfer rate over a first period from the third timing to the fourth timing;

 (e) During the second period from the fourth evening timing to the fifth timing based on the trailing edge of the second trigger signal, the charge of the vertical transfer unit is transferred at the first transfer rate. Vertical transfer at a slower second transfer rate, and causing the horizontal transfer unit to output charges supplied to the horizontal transfer unit as effective charges during the second period. Drive control method of the imaging element to be performed.

 13. The request according to claim 1, wherein the step (a) further comprises a step of changing a pulse width of the second trigger signal by a user in order to change an image range to be output as the effective charge. Item 12. The drive control method for an image sensor according to Item 12.

14. The imaging method according to claim 12, wherein in the step (b), the second timing is the same as the first evening timing. Drive control method for image element.

 15 5. A light-receiving unit in which a plurality of light-receiving elements are arranged and arranged in a matrix in order to generate and accumulate electric charges according to the amount of incident light, and transfer the electric charges read out from each light-receiving element of the light-receiving elements. An interline transfer type solid-state imaging device, comprising: a vertical transfer unit that outputs electric charges transferred via the vertical transfer unit;

 Pulse width adjusting means for generating a second trigger signal having a pulse width variably set by a user based on the first trigger signal; and timing of a leading edge of the second trigger signal. In a second timing based on a certain first timing, all charges accumulated in the plurality of light receiving elements are eliminated as invalid charges, and a third timing after a predetermined time from the second timing is performed. Then, the charges accumulated in the plurality of light receiving elements are read out to the vertical transfer unit, and are transferred to the vertical transfer unit for a first period from the third timing to a fourth timing. The charges are vertically transferred at the first transfer rate, and the charges are vertically transferred over the second period from the fourth timing to the fifth evening based on the trailing edge of the second trigger signal. The charge of the vertical transfer unit is slower than the first transfer speed. By performing vertical transfer at a transfer rate of 2, the in-line transfer type solid-state imaging device outputs the charges supplied to the horizontal transfer portion during the second period as effective charges from the horizontal transfer portion. An imaging apparatus comprising: an imaging element control unit that controls an element.

16. The imaging device control means generates a standard vertical synchronization signal and a standard horizontal synchronization signal conforming to the standard television system, and outputs the standard horizontal synchronization signal to the in-line transfer type solid-state imaging device. A standard synchronization signal generating means, and a tie at the leading edge of the second trigger signal. A sub-vertical synchronization signal for providing a second timing based on the timing, and outputting the sub-vertical synchronization signal to the in-line transfer type solid-state imaging device; and the standard horizontal synchronization. 2. A high-speed horizontal synchronizing signal generating means for generating a high-speed horizontal synchronizing signal having a frequency higher than that of the signal over the first period and outputting the generated high-speed horizontal synchronizing signal to the inter-line transfer type solid-state imaging device. The imaging device according to 5.

 17. The imaging apparatus according to claim 16, wherein the sub-synchronization signal generating means generates a sub-vertical synchronization signal that gives the same second timing as the first timing.

 1 8. A plurality of light-receiving elements, each of which generates and accumulates a charge corresponding to the amount of incident light, are arranged in a matrix, and the effective charges read from each of the light-receiving elements in the light-receiving section are transferred. An in-line transfer type solid-state image pickup device having a vertical transfer section for transferring an effective charge transferred through the vertical transfer section, and an imaging signal based on the effective charge. An imaging control device that controls an imaging device including an imaging unit that performs

 Pulse width adjusting means for generating a second trigger signal having a pulse width variably set by a user based on the first trigger signal and supplying the generated second trigger signal to the imaging device;

In the second timing based on the first timing, which is the timing of the leading edge of the second trigger signal, all charges accumulated in the plurality of light receiving elements are excluded as invalid charges, and The charges accumulated in the plurality of light receiving elements are read out to the vertical transfer unit at a third timing after a predetermined time from the evening of the second, and the fourth evening is read out from the third timing. The charge transferred to the vertical transfer unit is vertically transferred at a first transfer rate over a first period until timing, and the trailing edge of the second trigger signal is output from the fourth timing. By vertically transferring the charges of the vertical transfer unit at a second transfer speed lower than the first transfer speed over a second period up to a fifth timing based on the second period, Imaging control means for controlling the in-line transfer type solid-state imaging device so as to output charges supplied to the horizontal transfer section as effective charges from the horizontal transfer section. Dress

19. The image sensor control means generates a standard vertical synchronizing signal and a standard horizontal synchronizing signal conforming to the standard television system, and outputs the standard horizontal synchronizing signal to the imaging device. Generating a sub-vertical synchronization signal for providing a second timing based on the timing of the leading edge of the second trigger signal, and outputting the sub-vertical synchronization signal to the imaging device; Generating means for generating a high-speed horizontal synchronizing signal having a frequency higher than that of the standard horizontal synchronizing signal over the first period, and outputting the high-speed horizontal synchronizing signal to the imaging device. 19. The imaging control device according to claim 18.

20. The imaging control device according to claim 19, wherein the sub-synchronization signal generating means generates a sub-vertical synchronization signal that gives the same second timing as the first timing. .

21. A storage unit for temporarily storing the image pickup signal output from the image pickup apparatus, and the image pickup signal is stored in the storage unit according to the second trigger signal, and the storage unit An output system for reading out the stored image signal from the storage means and outputting it as a still image signal. 19. The imaging control device according to claim 18, further comprising control means.

 2 2. A light-receiving unit in which a plurality of light-receiving elements are arranged and arranged in a matrix in order to generate and accumulate electric charges corresponding to the amount of incident light, and an effective charge read from each light-receiving element of the light-receiving element An in-line transfer type solid-state imaging device having a vertical transfer unit for transferring, a horizontal transfer unit for outputting the effective charge transferred via the vertical transfer unit, and an imaging signal based on the effective charge. An imaging device having an imaging unit for outputting, and a second trigger signal having a pulse width variably settable by a user based on the first trigger signal, and supplying the generated second trigger signal to the imaging device In the second timing based on the pulse width adjusting means and the first timing which is the timing of the leading edge of the second trigger signal, all the charges accumulated in the plurality of light receiving elements are invalid charges. As the above At a third evening after a predetermined time from the evening of the second, the charges accumulated in the plurality of light receiving elements are read out to the vertical transfer unit, and the charges from the third to the fourth timing are read out. The charge transferred to the vertical transfer unit is vertically transferred at a first transfer rate over a first period, and the fifth transfer is performed based on the trailing edge of the second trigger signal from the fourth timing. By vertically transferring the charges of the vertical transfer unit at a second transfer speed lower than the first transfer speed over a second period until the timing of the horizontal transfer, the horizontal transfer is performed during the second period. An image pickup control device comprising: image pickup device control means for controlling the above-mentioned line transfer solid-state image pickup device so as to output charges supplied to the section as effective charges from the horizontal transfer section;

An imaging system comprising:

23. The image sensor control means generates a standard vertical synchronizing signal and a standard horizontal synchronizing signal conforming to a standard television system, and outputs the standard horizontal synchronizing signal to the imaging device. Generating a sub-vertical synchronization signal for providing a second timing based on the timing of the leading edge of the second trigger signal, and outputting the sub-vertical synchronization signal to the imaging device; Generating means for generating a high-speed horizontal synchronizing signal having a frequency higher than that of the standard horizontal synchronizing signal over the first period, and outputting the high-speed horizontal synchronizing signal to the imaging device. The imaging system according to claim 22.

24. The imaging system according to claim 23, wherein said sub-synchronization signal generating means generates a sub-vertical synchronization signal giving the same second timing as said first timing.