WO1998019172A1 - Circuit pour la detection soumise a une hysteresis de la valeur seuil de la valeur de crete d'un signal d'entree periodique - Google Patents

Circuit pour la detection soumise a une hysteresis de la valeur seuil de la valeur de crete d'un signal d'entree periodique Download PDF

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Publication number
WO1998019172A1
WO1998019172A1 PCT/AT1997/000231 AT9700231W WO9819172A1 WO 1998019172 A1 WO1998019172 A1 WO 1998019172A1 AT 9700231 W AT9700231 W AT 9700231W WO 9819172 A1 WO9819172 A1 WO 9819172A1
Authority
WO
WIPO (PCT)
Prior art keywords
input signal
threshold value
output
input
threshold
Prior art date
Application number
PCT/AT1997/000231
Other languages
German (de)
English (en)
Inventor
Bernhard Rzepa
Original Assignee
Mikroprozessor Handels-Ges.Mbh & Co. Kg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mikroprozessor Handels-Ges.Mbh & Co. Kg filed Critical Mikroprozessor Handels-Ges.Mbh & Co. Kg
Publication of WO1998019172A1 publication Critical patent/WO1998019172A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
    • G01R19/1659—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 to indicate that the value is within or outside a predetermined range of values (window)
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/04—Measuring peak values or amplitude or envelope of ac or of pulses

Definitions

  • the present invention relates to a circuit arrangement for hysteresis-dependent threshold value detection of the peak value of a periodic input signal.
  • the input signal is rectified and sieved in order to receive an approximation signal for the temporal change in the peak value, which is fed to a Schmitt trigger, which generates the desired hysteresis behavior.
  • the time constant of the sieve element must be chosen to be sufficiently large, which increases the reaction time of the detection accordingly, so that a rapid drop in the peak value below the threshold value can only be detected with a delay, especially when the input voltage initially exceeds the threshold value.
  • the aim of the invention is to create a circuit arrangement of the type mentioned in the introduction with which the exceeding or falling below certain threshold values of the peak value can be quickly and reliably, i.e. while maintaining the hysteresis behavior of the known circuit arrangements.
  • This goal is achieved with a circuit arrangement which is characterized according to the invention in that the input signal is fed to a threshold value switch with a controllable threshold value, which is followed by a retriggerable timer with a time constant in the order of magnitude of the basic period of the input signal, the output of which is the output of the circuit arrangement forms and is fed to the control input of the threshold switch and reduces its threshold value in the triggered state.
  • the response time to a drop in the peak value is a maximum of the hold time of the timing element, which is of the order of the basic period of the input signal and thus clearly below the time constant of conventional filter elements.
  • a particularly advantageous embodiment of the invention which is intended for zero-line-symmetrical input signals, is characterized in that the threshold value switch is preceded by a full-wave rectifier and the time constant of the timing element is less than half the basic period of the input signal, which further reduces the response time.
  • the threshold switch preferably has a comparator, at one input of which the input signal and at the other input of which the output of a controllable reference voltage source is guided, which is controlled by the output of the timing element, which enables a particularly simple embodiment.
  • FIG. 1 shows the relationship between input and output signal in a conventional Schmitt trigger according to the prior art, which is controlled via a rectifier and a filter element
  • FIG. 2 shows a block diagram of the circuit arrangement according to the invention
  • FIG. 3 shows the relationship between input and output signal in the circuit arrangement of FIG. 2.
  • the uppermost curve in FIG. 1 shows a keyed input signal UN > whose keying represents the information content to be detected.
  • the middle curve shows the timing of an approximation signal Us for the peak value of the input signal Uj ⁇ which has been generated by conventional rectification and screening and is led to the input of a Schmitt trigger with the switch-on threshold Ug and the switch-off threshold U ⁇ .
  • the output signal UQTJT i st i n the lowermost curve shown. It can be seen that a drop in the peak value of UJN below the switch-off threshold value U ⁇ is only recognized after a delay time ⁇ T, which is determined by the time constant of the filter element used.
  • the circuit arrangement according to the invention for hysteresis-dependent threshold value detection of the peak value of a periodic input signal in succession has a full-wave rectifier 1, a threshold switch 2 and a timing element 3.
  • the threshold value U sw of the threshold switch 2 is controlled via a control input 4 by the output of the timing element 3, which at the same time forms the output U ou t of the circuit arrangement.
  • the threshold switch 2 essentially contains a comparator 5, at whose one input the rectified input signal U j 'and at the other input of which a controllable reference voltage source 6 is connected, which can be set via the control input 4.
  • the timing element 3 is of the retriggerable type and has a time constant .DELTA.t which is in the order of the basic period P of the input signal Uj ⁇ , preferably in the range of half the basic period.
  • the timing element 3 is preferably formed by a monoflop, but can also be an R / C element with a shortened charging time constant. The operation of the circuit is explained with reference to FIG. 3, which shows the timing of the voltage UJ_N a circuit input, the voltage UJN 'at the input of the threshold switch and the voltage UOTJT a circuit output one above the other. If the rectified input signal UJ .
  • N ' reaches the threshold value Usw of the threshold switch 2, this triggers the timing element 3 and the output signal U Q UT changes to the "high” state.
  • the "high" signal at the circuit output instructs the reference voltage source 6 to reduce the threshold value Usw for the threshold value switch 2 to a lower threshold value Usw ' z u.
  • the rising edges of the subsequent half-waves of the rectified input signal Uj ⁇ 'each time trigger the timer 3 again, as long as they exceed the reduced threshold value Usw'. If the peak value of the rectified input signal Uj N 'falls below the reduced threshold value U S ', the retriggering of the timing element 3 is omitted and the output signal UQ T falls after a delay time which corresponds to the time constant ⁇ t of the monoflop 3, return to "low".
  • a preferred application of the circuit arrangement is the use in a digital coupling element which is controlled with an alternating signal or works internally with one (e.g. for feeding an inductive transformer for galvanic input / output separation), the keying of the alternating signal being the digital information to be detected with hysteresis represents.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)

Abstract

L'invention concerne un circuit servant à la détection soumise à une hystérésis de la valeur seuil de la valeur de crête d'un signal d'entrée périodique. Le signal d'entrée (UIN, UIN') est conduit à un commutateur à valeur seuil (2) dont la valeur seuil (USW) peut-être commandée, en aval duquel est monté un organe temporisant (3) pouvant être redéclenché, présentant une constante de temps (Δt) de l'ordre de grandeur de la durée de la période fondamentale (P) du signal d'entrée (UIN, UIN') dont le signal de sortie constitue le signal de sortie (UOUT) du circuit, et est conduit à l'entrée de commande (4) du commutateur à valeur seuil (2) et, à l'état déclenché, réduit la valeur seuil (USW) dudit commutateur qui devient (USW').
PCT/AT1997/000231 1996-10-29 1997-10-28 Circuit pour la detection soumise a une hysteresis de la valeur seuil de la valeur de crete d'un signal d'entree periodique WO1998019172A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
AT1885/96 1996-10-29
AT188596A AT412600B (de) 1996-10-29 1996-10-29 Schaltungsanordnung zur hysteresebehafteten schwellwertdetektion des spitzenwertes eines periodischen eingangssignales

Publications (1)

Publication Number Publication Date
WO1998019172A1 true WO1998019172A1 (fr) 1998-05-07

Family

ID=3523127

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/AT1997/000231 WO1998019172A1 (fr) 1996-10-29 1997-10-28 Circuit pour la detection soumise a une hysteresis de la valeur seuil de la valeur de crete d'un signal d'entree periodique

Country Status (2)

Country Link
AT (1) AT412600B (fr)
WO (1) WO1998019172A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1187330A2 (fr) * 2000-08-29 2002-03-13 Alcatel Comparateur de tension pour l'enveloppe d'une tension alternative et méthode de comparaison
CN103472288A (zh) * 2013-08-30 2013-12-25 西北工业大学 峰值电压检测电路
US8921527B2 (en) 2002-02-14 2014-12-30 Chugai Seiyaku Kabushiki Kaisha Antibody-containing solution formulations

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3541457A (en) * 1966-12-14 1970-11-17 Bausch & Lomb Peak occurrence detector circuit
GB2100082A (en) * 1981-06-08 1982-12-15 Tektronix Inc Automatically detecting signal levels
DE4326538A1 (de) * 1993-08-07 1995-02-09 Rohde & Schwarz Analoger Spitzenwertmesser

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57111116A (en) * 1980-12-26 1982-07-10 Fujitsu Ltd Comparator having hysteresis
JPS63238566A (ja) * 1987-03-27 1988-10-04 Fuji Elelctrochem Co Ltd 交流入力電圧検出方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3541457A (en) * 1966-12-14 1970-11-17 Bausch & Lomb Peak occurrence detector circuit
GB2100082A (en) * 1981-06-08 1982-12-15 Tektronix Inc Automatically detecting signal levels
DE4326538A1 (de) * 1993-08-07 1995-02-09 Rohde & Schwarz Analoger Spitzenwertmesser

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1187330A2 (fr) * 2000-08-29 2002-03-13 Alcatel Comparateur de tension pour l'enveloppe d'une tension alternative et méthode de comparaison
EP1187330A3 (fr) * 2000-08-29 2004-02-25 Alcatel Comparateur de tension pour l'enveloppe d'une tension alternative et méthode de comparaison
US8921527B2 (en) 2002-02-14 2014-12-30 Chugai Seiyaku Kabushiki Kaisha Antibody-containing solution formulations
CN103472288A (zh) * 2013-08-30 2013-12-25 西北工业大学 峰值电压检测电路

Also Published As

Publication number Publication date
ATA188596A (de) 2004-09-15
AT412600B (de) 2005-04-25

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