WO1998014876A1 - Circuit comprenant un microprocesseur et une memoire a liste renversee - Google Patents

Circuit comprenant un microprocesseur et une memoire a liste renversee Download PDF

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Publication number
WO1998014876A1
WO1998014876A1 PCT/DE1997/002253 DE9702253W WO9814876A1 WO 1998014876 A1 WO1998014876 A1 WO 1998014876A1 DE 9702253 W DE9702253 W DE 9702253W WO 9814876 A1 WO9814876 A1 WO 9814876A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
register
stack
logical address
address space
Prior art date
Application number
PCT/DE1997/002253
Other languages
German (de)
English (en)
Inventor
Klaus Oberländer
Michael Baldischweiler
Stefan Pfab
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to JP10516148A priority Critical patent/JP2000503792A/ja
Priority to EP97910244A priority patent/EP1010081A1/fr
Priority to BR9712154-1A priority patent/BR9712154A/pt
Publication of WO1998014876A1 publication Critical patent/WO1998014876A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615—Address space extension
    • G06F12/0623—Address space extension for memory modules
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication

Definitions

  • Microprocessors require a stack memory in order to process programs to be executed by them.
  • the stack memory also called "stack"
  • the stack memory is used to hold a return address which he jumps back to after the end of the subroutine in order to continue executing the program at the same point from where he made the subroutine jump.
  • stack pointer which usually contains the address of the last entry in the stack and is incremented accordingly when a new entry is made in the stack. It is also common to store variables in the stack in addition to return addresses.
  • a program to be processed by the processor is loaded into a main memory of the processor, which is usually implemented by a RAM (Random Access Memory).
  • the main memory is located in a logical address space that can be directly addressed via the processor's address outputs.
  • the stack memory and the working memory share the available logical address space, the size of which is determined by the number of address outputs of the processor. With, for example, only eight address outputs, such as those found in type 8051 microcontrollers, this can be done directly via the address outputs of the controller addressable logical address space only 256 bytes in size.
  • the size for the required stack memory results.
  • the stack size is therefore directly dependent on the type of program to be processed. When manufacturing the microprocessor, however, it is usually not known what type of software it should ultimately process.
  • the stack memory is therefore usually of relatively large dimensions, so that even complex programs can be handled by the processor. For many other, less complex applications, however, the stack memory is then oversized.
  • the stack memory is usually arranged in the upper address area of the logical address space of the microprocessor.
  • the stack pointer is preset to the lowest address of the stack when the processor is started up or initialized. If data is subsequently stored in the stack, the stack pointer is incremented accordingly.
  • the main memory of the processor only the area from the beginning to the beginning of the stack is available in the logical address space.
  • the invention has for its object to provide a circuit arrangement with a microprocessor and a stack for the microprocessor, in which the largest possible area of the logical address space directly addressable by the processor via its address outputs for the main memory is available and the smallest possible part of the logi ⁇ 's address space occupied by the stack.
  • circuit arrangement according to claim 1 it is provided to arrange at least a part of the stack memory outside the directly addressable logical address space of the microprocessor.
  • the circuit arrangement has a first register in which information on the selection of one of the memory areas can be stored and a second register in which information on the selection of memory units contained in the respectively selected memory area can be stored.
  • This second register can advantageously correspond to a conventional stack pointer.
  • the storage units of each storage area can be used to hold one data word each. It is advantageous if there is a memory unit in each of the memory areas with the same address that can be stored in the second register or the stack memory. Which of these memory units is addressed with the same addresses is determined by the content of the first register and the resulting selection of the corresponding memory area.
  • the functioning of this exemplary embodiment of the invention is as follows: When the circuit arrangement is started up, the information for selecting the first memory area is stored in the first register.
  • the corresponding data (return addresses or variables) are first stored in succession in the memory units of the first memory area.
  • the content of the second register or the stack pointer is incremented accordingly. If all storage units of the first storage area are occupied with data, the content of the first register is incremented and the second storage area is thus selected. The contents of the second register are then used to fill its storage units with data, if necessary, and so on.
  • the invention enables the greatest possible part of the logical address space to be available for the working memory of the microprocessor by arranging as small a part of the stack memory in the logical address space as possible with little effort and with only a slight change from conventional circuit arrangements which have a microprocessor and a corresponding stack memory stands, whereby at the same time an arbitrarily large stack memory can be realized, the largest part of which is arranged outside the logical address space.
  • these two goals can be achieved in a particularly simple manner by selecting the number of storage units per storage area as low as possible and the number of storage areas of the stack memory as high as possible.
  • a further development of the invention provides that the circuit arrangement has a detection means which is used to detect when a limit of the stack memory has been exceeded when writing or reading data into the stack memory. If it is provided at the same time, depending on a result signal of the detection means in the event that an upper limit or is exceeded If the stack memory falls below a lower limit and the stack memory is at least partially emptied, malfunctions as a result of the overflow or underflow of the stack memory can be avoided.
  • An interrupt can advantageously be triggered by the result signal of the detection means, whereby the processor interrupts the execution of the respective program at the current position and jumps to a predetermined other program address.
  • the program instructions to be processed there can then cause the stack memory to be emptied by forcibly terminating the last started subroutines.
  • the interrupt makes sense if the interrupt generates a corresponding error message which indicates to a user of the processor that the stack memory is malfunctioning.
  • the circuit arrangement has a third register in which the number of
  • Memory areas are stored so that an overflow of the stack memory can be detected by means of the detection means by comparing the content of the third register with the content of the first register in which the address of the respectively selected memory area is stored.
  • FIG. 1 shows an embodiment of the invention.
  • FIG. 2 shows a detail from FIG. 1.
  • FIG. 1 shows a microprocessor 1 with a limited number of address outputs 2 for addressing a logical address space 3 via a corresponding address decoder 20.
  • the microprocessor 1 has eight address outputs 2. This is the case, for example, if the microprocessor 1 is a type 8051 microcontroller.
  • the binary addresses of storage units within the logical address space 3 can also be seen in FIG. 1.
  • the lowest address of the logical address space is 0000 0000.
  • the highest address is 1111 1111.
  • the storage units can be data words, each of which has the size of one or more bytes. Assume that the storage units are one byte in size. 256 bytes can then be addressed by means of the decoder 20 via the eight address outputs 2.
  • FIG. 1 there is a stack memory 4 which is divided into four memory areas 5 (page 1 to page 4) of equal size. Each of the memory areas 5 is divided into individually addressable memory units 9. The memory units 9 of each of the memory areas 5 can each be addressed via the same addresses present at the address outputs 2 of the processor 1. These correspond to the
  • a selection of one of the memory units 9, each with the same address, is made via a second decoder 30.
  • regions 5 can be selected via the second decoder 30 a SpeI ⁇ cher Schemee. 5
  • the first register 6 and the second decoder 30 determine in which of the memory areas 5 the memory unit with the corresponding address is selected .
  • Which of the memory units 9 is addressed by the processor 1 within the memory areas 5 is determined by the content of a second register 7, which corresponds to a conventional stack pointer or stack pointer.
  • the size of the remaining working memory 10 can be increased or decreased by a different number of memory units 9 within the memory areas 5.
  • the total size of the stack memory 4 can be increased by a larger number of memory areas 5 without the remaining working memory 10 being reduced.
  • the second register 7 or the stack is initially initialized.
  • the content of the second register 7 is initially preset to the lowest address of the memory units 9 of the stack memory 4, namely 1111 0000.
  • the content of the first register 6, which is not available in the prior art is also set such that the second decoder 30 is the first memory area advantage Page 1 selec ⁇ .
  • the first re gister ⁇ must have 6 only two bits for their addressing.
  • the number of address bits of the first register 6 is selected to be much larger and the number of selectable memory areas is also increased accordingly.
  • the memory requirement of the stack 4 is dependent on the number of subroutine branches and the variables to be stored in the stack 4.
  • Those memory areas 5 of the stack 4 which are arranged outside the logical address space 3 of the processor 1 can be arranged in one or more memories different from that in which the first memory area is arranged. It makes sense that these additional memories are located on the same integrated circuit as the first memory area 1 and the working memory 10. It is particularly favorable if the entire stack memory 4 and the working memory 10 are components of a common memory, of which only that part which contains the working memory 10 and the first memory area 1 in the logical address space which can be addressed directly by the address outputs 2 of the microprocessor 1 3 lie.
  • the invention now enables that as soon as the first memory area Page 1 is filled with data, that is to say the stack pointer 7 has the address 1111 1111, the address 1111 0000 in the stack pointer again passes over the last 4 bits of the stack pointer 7 is included. This is achieved in that the first four bits of the stack pointer 7 are set to 1111 in an unchangeable manner. At the same time, the overflow of the second register 7 is registered by the first register 6 and this is incremented accordingly, so that the memory unit 9 with the address 1111 0000 can now be addressed in the second memory area via the address outputs 2 of the processor 1. The same applies to the change to the other storage areas. Likewise, when reading data from the stack 4, the stack pointer 7 is decremented accordingly.
  • the top four bits of the stack pointer are fixed at 1111 and only the bottom four bits XXXX are variable. If the lower limit of one of the memory areas 5 with the address 1111 0000 has already been reached and a further date is read, the subtraction or decrementing results in a new counter reading of 1111 1111 in the second register 7. At the same time, the first register registers 6 this underflow and is decremented accordingly, whereupon the next lower memory area 5 can be selected via the second decoder 30.
  • the circuit arrangement has a third register 8, in which the number of usable memory areas 5 is stored.
  • the detection means 11 detects an overflow of the stack memory 4 by comparing the content of the first register with that of the third register 8 and sends a corresponding result signal to the processor 1. This in turn temporarily interrupts the processor Execution of the program to be executed and first performs an at least partial emptying of the stack 4, followed by a corresponding initialization of the first register 6 and the second register 7.
  • FIG. 1 also shows a data bus 40, via which the processor 1 can write data into the working memory 10 or the stack memory 4 and read them out again.
  • FIG. 2 again shows the first register 6 and the second register 7 from FIG. 1.
  • the process of incrementing and decrementing is to be explained once again with reference to FIG. 2.
  • the corresponding return address is stored in the stack 4 at the address which is determined by the content of the two registers 6 and 7.
  • the last 4 bits XXXX of the second register 7 are incremented by 1, so that the stack pointer 7 points to the next free storage unit 9 in the stack 4. If an overflow occurs, that is, the content of the second register 7 jumps from
  • this register 1111 1111 to 1111 0000, this registers a logic 60 and increments the content of the first register 6 by the value 1. Conversely, in the case of a return from a subroutine (Return), the corresponding return address is taken from the stack memory 4, and the last four bits XXXX of the stack pointer 7 are decremented by the value 1. If there is an underflow of the last four bits XXXX, this registers the logic 60 and decrements the content of the first register 6 by 1.
  • an increment or decrement value (for example 2) which deviates therefrom can also be provided. This depends on the scope of the data to be stored in the stack 4. In the exemplary embodiment described with reference to FIG. 1, in which the storage units have a size of one byte each, an increment or decrement of 2 each would have to be selected if the return addresses or variables to be stored have a size of two bytes.
  • FIG. 2 also shows a further logic 50, with which commands relative to the stack pointer 7 or modifying the stack pointer 7 can be implemented, as are customary in microprocessors.
  • the processor places a new address on the data bus by which the content of the stack pointer is to be increased or decreased in the circuit arrangements customary in the prior art.
  • a further logic 50 is provided which adjusts or adjusts the contents of the two registers 6, 7 to the correct values.
  • the invention has the advantage that a large working memory 10 and a large stack memory 4 can be implemented at the same time.
  • the circuit arrangement according to the invention is capable of executing the same stack instructions as conventional circuit arrangements.
  • the circuit arrangement according to the invention has the further advantage that it is only under a slight modification herkömm ⁇ Licher such circuit arrangements are realized.
  • a conventional microprocessor 1 with conventional data bus 40 and address outputs 2 and a conventional decoder 20 can be used.
  • the previously common stack pointer can only be modified to the extent that the desired number of bits cannot be changed.
  • the four uppermost bits in the stack pointer 7 are set unchangeably at 1111.
  • a memory is required which is larger than the logical address space 3 in order to accommodate the memory areas 5 of the stack memory 4 arranged outside this.
  • the circuit arrangement according to the invention requires the first register 6 and the second decoder 30 to select one of the memory areas 5 in each case.
  • the invention is particularly advantageous where only one processor 1 with a very small number of address outputs 2 is available, as is the case, for example, with the 8051 microcontroller. Especially with such a small available logical address space 3, it is absolutely necessary to keep the portion of the stack 4 in this logical address space 3 as small as possible. Although numerous processors with a larger number of address outputs are also known, by means of which a much larger logical address space can then be addressed, these processors are generally much larger than, for example, the 8051 microcontroller If one or more integrated semiconductor circuits have to be accommodated within a card-shaped plastic housing, it is important that the chip area is as small as possible, because the mechanical stresses in a chip card are very large, so that larger-area chips are easily destroyed.
  • circuit arrangement according to the invention is fully compatible with conventional stack memory commands, it is not necessary to adapt development tools for software applications to be executed by processor 1.
  • the circuit arrangement according to the invention enables an expansion of the address of the stack memory area without the directly addressable logical address space of the processor 1 having to be expanded.
  • Stack commands must be distinguished from all other commands. Therefore, only those addresses that are larger than 1111 0000 are transferred to the stack pointer 7 in a relative or modifying command. This can be checked using a simple comparator. For all other addresses, the selection lines of the second decoder 30 for selecting the memory areas 5 are deactivated.
  • first register 6 and the second register 7 are part of a single register, the first register 6 occupying the highest bits (MSBs, most significant bits) of this register and the second register 7 the lower ones. Then an overflow of the second results Registers 7 automatically incrementing and decrementing the first register 6 by an underflow.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)

Abstract

Le microprocesseur possède un espace adresse (3) logique directement adressable par des sorties d'adresses (2). La mémoire à liste renversée (4) est disposée au moins partiellement à l'extérieur de l'espace adresse (3) logique. Avantage: la mémoire de travail (10) restant dans l'espace adresse (3) logique peut être agrandie.
PCT/DE1997/002253 1996-09-30 1997-09-30 Circuit comprenant un microprocesseur et une memoire a liste renversee WO1998014876A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP10516148A JP2000503792A (ja) 1996-09-30 1997-09-30 マイクロプロセッサおよびスタックメモリを有する回路装置
EP97910244A EP1010081A1 (fr) 1996-09-30 1997-09-30 Circuit comprenant un microprocesseur et une memoire a liste renversee
BR9712154-1A BR9712154A (pt) 1996-09-30 1997-09-30 Disposição de circuito com um microprocessador e uma memória de pilha.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19640316.2 1996-09-30
DE19640316A DE19640316A1 (de) 1996-09-30 1996-09-30 Schaltungsanordnung mit einem Mikroprozessor und einem Stapelspeicher

Publications (1)

Publication Number Publication Date
WO1998014876A1 true WO1998014876A1 (fr) 1998-04-09

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ID=7807457

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Application Number Title Priority Date Filing Date
PCT/DE1997/002253 WO1998014876A1 (fr) 1996-09-30 1997-09-30 Circuit comprenant un microprocesseur et une memoire a liste renversee

Country Status (7)

Country Link
EP (1) EP1010081A1 (fr)
JP (1) JP2000503792A (fr)
KR (1) KR20000048754A (fr)
CN (1) CN1232564A (fr)
BR (1) BR9712154A (fr)
DE (1) DE19640316A1 (fr)
WO (1) WO1998014876A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100353335C (zh) * 2003-03-28 2007-12-05 联发科技股份有限公司 增加处理器中存储器的方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5391870B2 (ja) * 2009-06-26 2014-01-15 富士通株式会社 情報処理装置及びその方法
CN102193868B (zh) * 2010-03-10 2013-06-19 上海海尔集成电路有限公司 数据堆栈存储电路及微控制器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990012363A1 (fr) * 1989-04-10 1990-10-18 Cirrus Logic, Inc. Technique d'adressage permettant d'elargir de façon transparente l'espace d'adresse d'un systeme de traitement de donnees
US5107457A (en) * 1989-04-03 1992-04-21 The Johns Hopkins University Stack data cache having a stack management hardware with internal and external stack pointers and buffers for handling underflow and overflow stack
US5255382A (en) * 1990-09-24 1993-10-19 Pawloski Martin B Program memory expander for 8051-based microcontrolled system
GB2282470A (en) * 1993-09-23 1995-04-05 Motorola Israel Ltd Expanded memory management for multi-tasking environment.

Family Cites Families (5)

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Publication number Priority date Publication date Assignee Title
DE3726192A1 (de) * 1987-08-06 1989-02-16 Otto Mueller Stacksteuerung
JPH0215345A (ja) * 1988-07-04 1990-01-19 Hitachi Ltd データ処理装置
DE4340551A1 (de) * 1993-11-29 1995-06-01 Philips Patentverwaltung Programmspeichererweiterung für einen Mikroprozessor
US5666556A (en) * 1993-12-30 1997-09-09 Intel Corporation Method and apparatus for redirecting register access requests wherein the register set is separate from a central processing unit
DE69428881T2 (de) * 1994-01-12 2002-07-18 Sun Microsystems, Inc. Logisch adressierbarer physikalischer Speicher für ein Rechnersystem mit virtuellem Speicher, das mehrere Seitengrössen unterstützt

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5107457A (en) * 1989-04-03 1992-04-21 The Johns Hopkins University Stack data cache having a stack management hardware with internal and external stack pointers and buffers for handling underflow and overflow stack
WO1990012363A1 (fr) * 1989-04-10 1990-10-18 Cirrus Logic, Inc. Technique d'adressage permettant d'elargir de façon transparente l'espace d'adresse d'un systeme de traitement de donnees
US5255382A (en) * 1990-09-24 1993-10-19 Pawloski Martin B Program memory expander for 8051-based microcontrolled system
GB2282470A (en) * 1993-09-23 1995-04-05 Motorola Israel Ltd Expanded memory management for multi-tasking environment.

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100353335C (zh) * 2003-03-28 2007-12-05 联发科技股份有限公司 增加处理器中存储器的方法

Also Published As

Publication number Publication date
CN1232564A (zh) 1999-10-20
JP2000503792A (ja) 2000-03-28
EP1010081A1 (fr) 2000-06-21
BR9712154A (pt) 1999-08-31
DE19640316A1 (de) 1998-04-02
KR20000048754A (ko) 2000-07-25

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