WO1998006179A1 - Phase and frequency detector circuit - Google Patents

Phase and frequency detector circuit Download PDF

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Publication number
WO1998006179A1
WO1998006179A1 PCT/DE1997/001500 DE9701500W WO9806179A1 WO 1998006179 A1 WO1998006179 A1 WO 1998006179A1 DE 9701500 W DE9701500 W DE 9701500W WO 9806179 A1 WO9806179 A1 WO 9806179A1
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Prior art keywords
signal
phase
clock signal
frequency
oscillator
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PCT/DE1997/001500
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German (de)
French (fr)
Inventor
Reinhold Unterricker
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Siemens Aktiengesellschaft
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Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to EP97935430A priority Critical patent/EP0916189A1/en
Publication of WO1998006179A1 publication Critical patent/WO1998006179A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H03D13/005—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which one of the oscillations is, or is converted into, a signal having a special waveform, e.g. triangular
    • H03D13/006—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which one of the oscillations is, or is converted into, a signal having a special waveform, e.g. triangular and by sampling this signal by narrow pulses obtained from the second oscillation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/14—Preventing false-lock or pseudo-lock of the PLL
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0004—Initialisation of the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Definitions

  • phase locked loop is frequently used for clock synchronization, in which the clock phase of a local oscillator is compared with the phase position of a received data signal with the aid of a phase detector and readjusted. Since a phase locked loop does not engage if the frequency of the local oscillator deviates too much from the data rate, it must also be possible to correctly recognize and correct a frequency difference.
  • the magnitude of the sampled normal clock signal must be greater than the magnitude of the ternary output signal of the frequency detector circuit, and especially in the zero crossing of the sampled normal clock signal.
  • phase detector must therefore be designed with a very large slope at the zero crossing, so that a trapezoidal function with very steep edges is described as a function of the phase; the phase detector characteristic curve is then only linear in a very small range, which leads to poor transmission properties of the phase locked loop (PLL).
  • PLL phase locked loop
  • the invention shows a way to avoid such a disadvantage.
  • the invention relates to a phase and frequency detector circuit with a first phase detector in the form of a scanning and storage element which is loaded with a sinusoidal oscillator signal [normal clock signal] and clocked with the edges of a received signal, with a second phase detector in the form of such a with the oscillator signal [quadrature clock signal] delayed by 90 ° and with the edges of the received signal clocked scanning and storage element, and with a sampled quadrature clock signal forming the output signal of the second phase detector and with the output signal of the first Scanned normal clock signal forming frequency detector circuit, wherein the control signal for the oscillator is obtained in accordance with the sampled normal clock signal and the output signal of the frequency detector circuit - this phase and frequency detector is thereby according to the invention characterized in that the frequency detector circuit is formed with the same, with the sampled quadrature clock signal and clocked with the sampled normal clock signal, sampling and storage element, with the output signal of which the output signal of the first phase detector is blocked or released.
  • the output signal of the first phase detector is switched through or blocked by the output signal of the frequency detector in such a way that only the first one with a phase difference deviating by up to ⁇ ⁇ from 0 or another even multiple of ⁇ Phase detector is active, regardless of the frequency of the signals or their differences; the clear hysteresis behavior of the frequency detector reliably prevents the phase-locked loop from latching into place when the frequency detector is active.
  • the known circuit arrangement (DE 28 26 053 C2) should also make it possible to engage properly, but it appears problematic in this circuit arrangement to use the zero-voltage comparator to detect the difference between falling and rising zero crossings at low beat frequencies. since the frequency control starts in the vicinity of the zero crossing of the signal with a phase error of ⁇ ⁇ / 2, which may influence the phase control process.
  • the invention enables the implementation of a frequency-sensitive and at the same time linear phase detector in a wide range, in which an ambiguity of the phase detector characteristic curve, namely a falling characteristic curve, both with a phase error equal to an even multiple of ⁇ and with a phase error equal to an odd multiple of ⁇ , is excluded.
  • FIG. 1 shows a block diagram of a phase locked loop with a phase and frequency detector circuit according to the invention and FIG. 2 shows two associated signal characteristics; 3 shows waveforms therein, and
  • phase and frequency detector circuit 4 shows a circuit detail of the phase and frequency detector circuit
  • phase and frequency detector circuit which, together with a sinusoidal oscillator VCO and a 90 ° delay element T / 4, lies in a phase locked loop.
  • This phase and frequency detector circuit initially has a first phase detector in the form of a scanning and
  • phase and frequency detector circuit has a second phase detector in the form of a scanning and storage element PQ of the same type, which acts on its signal input oq with the 90 ° delayed sinusoidal oscillator signal [also referred to here as a quadrature clock signal] and also on its clock input is clocked with the edges of the received signal.
  • the phase and frequency detector circuit has a frequency detector circuit in the form of a Such sampling and storage element FD, which is scanned at its signal input with the sampled quadrature clock signal occurring at the output pq of the second phase detector PQ and clocked at its clock input with the sampled normal clock signal occurring at the output pn of the first phase detector PN.
  • the scanning and storage elements can be designed in a manner known per se (for example from IEEE J. of Solid-State Circuits, 27 (1992) 12, 1747 ... 1751, FIG. 3), so that there is no further explanation here - Requires advice.
  • the output signal (pn) of the first phase detector PN can be used as an actuating signal for the phase control of an oscillator (VCO in FIG. 1) in a phase locked loop, but does not in itself provide any information about the sign of a possible frequency offset of the oscillator, since pn (at the phase detector output a sinusoidal signal (pn in FIG. 2 and FIG. 3) without directional information occurs in FIG. 1) with both positive and negative frequency offsets of the oscillator signal.
  • the phase and frequency detector circuit provides the frequency detector circuit FD to which the sampled quadrature clock signal (pq) is applied and which is clocked with the sampled normal clock signal (pn). wherein the control signal for the oscillator VCO to be tracked if necessary in accordance with the sampled normal clock signal (pn in FIG. 2 and.) occurring at the output pn of the first phase detector PN 3) and the signal occurring at the output fd of the frequency detector circuit FD (fd in FIG. 3) is formed.
  • the frequency detector circuit FD is now formed with the same sampling and storage element as the two phase detectors PN and PQ, the frequency detector circuit FD being supplied with the sampled quadrature clock signal (pq) and clocked with the sampled normal clock signal pn (in FIG. 3) becomes; With its output signal fd (in FIG. 3), the output signal pn (in FIG. 3) of the first phase detector PN, which serves as a control signal for the oscillator to be tracked (VCO in FIG. 1), is then blocked or enabled.
  • the switch M (in FIG. 1) which blocks and enables the signal (pn in FIG. 3) can, for example, tiplication circuit, as shown in FIG 4 in bipolar differential ECL technology.
  • the differential stage T1 / T2 which is unlocked by the transistor T5
  • the transistor T6 unlocks the differential stage T3 / T4, which is controlled with a 0 V voltage difference, so that a differential voltage of 0 V also occurs at the output pfd.
  • phase detector signal is now available at the output pfd, which has a DC component with correct polarity for oscillator control when the oscillator frequency deviates from the data rate, as the following consideration shows:
  • the characteristic curves pn and pq are run through from left to right.
  • the - here positive - sampled quadrature clock signal (pq in FIG. 2) is taken over to the output fd (in FIG. 1) of the frequency detector circuit FD (and until the next zero crossing of the sampled normal clock signal (pn in FIG. 2)), the switch M being unlocked so that a negative half-wave of the phase detector signal pn reaches the output pfd.
  • the - here negative - sampled quadrature clock signal pq in FIG.
  • phase detector PN can therefore be designed as a linear scanning circuit with a relatively large linear range without the risk of forming an ambiguous characteristic.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

A phase and frequency detector circuit has a first phase detector shaped as a sensor and storage member which receives a sinusoidal oscillator signal (normal clock signal) and is clocked by the flanks of a reception signal. This circuit also has a second phase detector shaped as a similar sensor and storage member which receives the oscillator signal offset by 90° (quadrature clock signal) and is clocked by the flanks of the reception signal. A frequency detector circuit receives the sensed quadrature clock signal and is clocked by the sensed normal clock signal. The setting signal for the oscillator is derived from the sensed normal clock signal, which forms the output signal of the first phase detector, and from the output signal of the frequency detector circuit. The frequency detector circuit has a similar sensor and storage member which receives the sensed quadrature clock signal and is clocked by the sensed normal clock signal. The output signal of said frequency sensor and storage member locks or releases the output signal of the first phase detector.

Description

Beschreibungdescription
Phasen- und FrequenzdetektorschaltungPhase and frequency detector circuit
Zur Taktsynchronisation wird häufig eine Phasenregelschleife (PLL) eingesetzt, in welcher die Taktphase eines lokalen Oszillators mit Hilfe eines Phasendetektors mit der Phasenlage eines empfangenen Datensignals verglichen und nachgeregelt wird. Da eine Phasenregelschleife nicht einrastet, wenn die Frequenz des lokalen Oszillators zu stark von der Datenrate abweicht, muß auch eine Frequenzdifferenz richtig erkannt und ausgeregelt werden können.A phase locked loop (PLL) is frequently used for clock synchronization, in which the clock phase of a local oscillator is compared with the phase position of a received data signal with the aid of a phase detector and readjusted. Since a phase locked loop does not engage if the frequency of the local oscillator deviates too much from the data rate, it must also be possible to correctly recognize and correct a frequency difference.
In diesem Zusammenhang ist es (aus A. Pottbacker u.a. : "A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s", IEEE J. of Solid-State Circuits, vol. 27, No. 12, Dec.1992, S.1747 - 1751) bekannt, mittels zweier Phasen- detektoren sowohl die Normal- als auch die Quadraturkomponente (d.h. das um 90° verzögerte Signal) eines sinusförmigen lokalen Taktsignals bei jedem Zustandswechsel des Datensignals analog abzutasten, in einer dreier Schaltzustände fähigen Frequenzdetektorschaltung das abgetastete Quadratur-Takt- signal mit dem abgetasteten Normal-Taktsignal abzutasten, und durch Addition des abgetasteten Normal-TaktSignals und des ternären Ausgangssignals der Frequenzdetektorschaltung ein Stellsignal für den lokalen Oszillator zu gewinnen.In this context it is (from A. Pottbacker et al.: "A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb / s", IEEE J. of Solid-State Circuits, vol. 27, No. 12, Dec .1992, pp.1747 - 1751), by means of two phase detectors capable of sampling both the normal and the quadrature component (ie the signal delayed by 90 °) of a sinusoidal local clock signal in each of the three signal states in each switching state Frequency detector circuit to sample the sampled quadrature clock signal with the sampled normal clock signal, and to obtain an actuating signal for the local oscillator by adding the sampled normal clock signal and the ternary output signal of the frequency detector circuit.
Hierbei ergibt sich aus einer auch in der Umgebung von ungeradzahligen Vielfachen von π fallenden Kennlinie des Phasendetektors (vgl. auch FIG 2) insofern ein Problem, als die Regelschleife (statt nur bei geradzahligen Vielfachen von π) fälschlicherweise auch bei ungeradzahligen Vielfachen von π einzurasten vermag. Um dies zu vermeiden, muß der Betrag des abgetasteten Normal-Taktsignals größer sein als der Betrag des ternären AusgangsSignals der Frequenzdetektorschaltung, und zwar besonders im Nulldurchgang des abgetasteten Normal - Taktsignals. Man muß daher den Normalkomponenten-Phasendetektor mit einer sehr großen Steigung im Nulldurchgang auslegen, so daß eine Trapezfunktion mit sehr steilen Flanken als Funk- tion der Phase beschrieben wird; die Phasendetektorkennlinie ist dann aber nur in einem sehr kleinen Bereich linear, was zu schlechten Übertragungseigenschaften der Phasenregelschleife (PLL) führt.A problem arises from a characteristic curve of the phase detector (cf. also FIG. 2) that also falls in the vicinity of odd multiples of π insofar as the control loop (instead of only with even multiples of π) can erroneously lock into place even with odd multiples of π . To avoid this, the magnitude of the sampled normal clock signal must be greater than the magnitude of the ternary output signal of the frequency detector circuit, and especially in the zero crossing of the sampled normal clock signal. The normal component phase detector must therefore be designed with a very large slope at the zero crossing, so that a trapezoidal function with very steep edges is described as a function of the phase; the phase detector characteristic curve is then only linear in a very small range, which leads to poor transmission properties of the phase locked loop (PLL).
Die Erfindung zeigt demgegenüber einen Weg, einen solchen Nachteil zu vermeiden.In contrast, the invention shows a way to avoid such a disadvantage.
Die Erfindung betrifft einen Phasen- und Frequenzdetektorschaltung mit einem ersten Phasendetektor in Form eines mit einem si- nusförmigen Oszillatorsignal [Normal -Taktsignal] beaufschlagten und mit den Flanken eines Empfangssignals getakteten Ab- tast- und Speichergliedes, mit einem zweiten Phasendetektor in Form eines ebensolchen, mit dem um 90° verzögerten Oszillatorsignal [Quadratur-Takt- signal] beaufschlagten und mit den Flanken des Empfangssignals getakteten Abtast- und Speichergliedes, und mit einer mit dem das Ausgangssignal des zweiten Phasendetektors bildenden abgetasteten Quadratur-Taktsignal beaufschlagten und mit dem das Ausgangssignal des ersten Phasen- detektors bildenden abgetasteten Normal-Taktsignal getakteten Frequenzdetektorschaltung, wobei das Stellsignal für den Oszillator nach Maßgabe des abgetasteten Normal-Taktsignals und des Ausgangssignals der Frequenzdetektorschaltung gewonnenen wird,- dieser Phasen- und Frequenzdetektor ist erfindungsgemäß dadurch gekennzeichnet, daß die Frequenzdetektorschaltung mit einem ebensolchen, mit dem abgetasteten Quadratur-Taktsignal beaufschlagten und mit dem abgetasteten Normal -Taktsignal ge- takteten Abtast- und Speicherglied gebildet ist, mit dessen Ausgangssignal das Ausgangssignal des ersten Phasendetektors gesperrt bzw. freigegeben wird. Es sei an dieser Stelle bemerkt, dass (aus DE 28 26 053 C2) eine Schaltungsanordnung zur Regelung eines frei schwingenden Oszillators bekannt ist, die ebenfalls zwei Phasendetektoren aufweist, deren zweiter mit einem um 90° verzögerten Oszilla- torsignal beaufschlagt ist, wobei zwischen dem Ausgang des ersten Phasendetektors und einem Schleifenfilter bzw. dem Oszillator ein Analogschalter angeordnet ist, der vom Ausgang des zweiten Phasendetektors her über einen Null-Spannungs- Komparator und eine monostabile Kippstufe gesteuert wird. Da- bei dient der Schalter dazu, aus der am Ausgang eines Begrenzerverstärkers auftretenden Rechteckschwingung Phasen heraus- zuisolieren, um das Vorzeichen der Frequenzablage festzustellen. Das am Schalterausgang auftretende Frequenzablagesignal wird nach Tiefpasεfilterung wiederum zum Phasendetektorsignal des ersten Phasendetektors addiert .The invention relates to a phase and frequency detector circuit with a first phase detector in the form of a scanning and storage element which is loaded with a sinusoidal oscillator signal [normal clock signal] and clocked with the edges of a received signal, with a second phase detector in the form of such a with the oscillator signal [quadrature clock signal] delayed by 90 ° and with the edges of the received signal clocked scanning and storage element, and with a sampled quadrature clock signal forming the output signal of the second phase detector and with the output signal of the first Scanned normal clock signal forming frequency detector circuit, wherein the control signal for the oscillator is obtained in accordance with the sampled normal clock signal and the output signal of the frequency detector circuit - this phase and frequency detector is thereby according to the invention characterized in that the frequency detector circuit is formed with the same, with the sampled quadrature clock signal and clocked with the sampled normal clock signal, sampling and storage element, with the output signal of which the output signal of the first phase detector is blocked or released. It should be noted at this point that (from DE 28 26 053 C2) a circuit arrangement for regulating a freely oscillating oscillator is known, which likewise has two phase detectors, the second of which is acted upon by an oscillator signal delayed by 90 °, between the An output of the first phase detector and a loop filter or the oscillator, an analog switch is arranged, which is controlled from the output of the second phase detector via a zero voltage comparator and a monostable multivibrator. The switch is used to isolate phases from the square wave occurring at the output of a limiter amplifier in order to determine the sign of the frequency offset. The frequency offset signal occurring at the switch output is in turn added to the phase detector signal of the first phase detector after low-pass filtering.
Demgegenüber wird in der Schaltungsanordnung gemäß der Erfindung das Ausgangssignal des ersten Phasendetektors durch das Ausgangssignal des Frequenzdetektors in der Weise durchge- schaltet oder gesperrt, dass bei einer um bis zu ± π von 0 bzw. einem anderen geradzahligen Vielfach von π abweichenden Phasendifferenz nur der erste Phasendetektor aktiv ist, unabhängig von der Frequenz der Signale bzw. deren Differenzen; durch das eindeutige Hystereseverhalten des Frequenzdetektors wird ein fehlerhaftes Einrasten der Phasenregelschleife bei aktivem Frequenzdetektor zuverlässig vermieden.In contrast, in the circuit arrangement according to the invention, the output signal of the first phase detector is switched through or blocked by the output signal of the frequency detector in such a way that only the first one with a phase difference deviating by up to ± π from 0 or another even multiple of π Phase detector is active, regardless of the frequency of the signals or their differences; the clear hysteresis behavior of the frequency detector reliably prevents the phase-locked loop from latching into place when the frequency detector is active.
Ein richtiges Einrasten soll an sich auch die bekannte Schaltungsanordnung (DE 28 26 053 C2 ) ermöglichen, doch erscheint es in dieser Schaltungsanordnung als problematisch, mit dem Null-Spannungs-Komparator den Unterschied zwischen fallenden und steigenden Nulldurchgängen bei kleinen Schwebungsfrequen- zen zu detektieren, da in der Umgebung des Nulldurchgangs des Signals bereits bei einem Phasenfehler von ± π/2 die Frequenz- regelung einsetzt, was ggf. den Phasenregelvorgang beeinflussen kann. Die Erfindung ermöglicht die Realisierung eines frequenzsensitiven und zugleich in einem weiten Bereich linearen Phasendetektors, bei dem eine Mehrdeutigkeit der Phasendetektor- kennlinie, nämlich eine fallende Kennlinie sowohl bei einem Phasenfehler gleich einem geraden Vielfachen von π als auch bei einem Phasenfehler gleich einem ungeraden Vielfachen von π, ausgeschlossen ist.The known circuit arrangement (DE 28 26 053 C2) should also make it possible to engage properly, but it appears problematic in this circuit arrangement to use the zero-voltage comparator to detect the difference between falling and rising zero crossings at low beat frequencies. since the frequency control starts in the vicinity of the zero crossing of the signal with a phase error of ± π / 2, which may influence the phase control process. The invention enables the implementation of a frequency-sensitive and at the same time linear phase detector in a wide range, in which an ambiguity of the phase detector characteristic curve, namely a falling characteristic curve, both with a phase error equal to an even multiple of π and with a phase error equal to an odd multiple of π , is excluded.
Weitere Besonderheiten der Erfindung werden aus der nachfol- genden näheren Erläuterung an Hand der Zeichnungen ersichtlich. Dabei zeigenFurther special features of the invention will become apparent from the following detailed explanation with reference to the drawings. Show
FIG 1 ein Blockschaltbild einer Phasenregelschleife mit einer Phasen- und Frequenzdetektorschaltung gemäß der Erfindung und FIG 2 zwei zugehörige Signalkennlinien; FIG 3 zeigt Signalverläufe darin, und1 shows a block diagram of a phase locked loop with a phase and frequency detector circuit according to the invention and FIG. 2 shows two associated signal characteristics; 3 shows waveforms therein, and
FIG 4 zeigt ein schaltungstechnisches Detail der Phasen- und Frequenzdetektorschaltung4 shows a circuit detail of the phase and frequency detector circuit
FIG 1 zeigt schematiεch in einem zum Verständnis der Erfindung erforderlichem Umfang eine Phasen- und Frequenzdetektorschaltung, die zusammen mit einem Sinusoszillator VCO und einem 90°-Verzögerungsglied T/4 in einer Phasenregelschleife liegt. Diese Phasen- und Frequenzdetektorschaltung weist zu- nächst einen ersten Phasendetektor in Form eines Abtast- und1 shows schematically, to the extent necessary for understanding the invention, a phase and frequency detector circuit which, together with a sinusoidal oscillator VCO and a 90 ° delay element T / 4, lies in a phase locked loop. This phase and frequency detector circuit initially has a first phase detector in the form of a scanning and
Speichergliedes PN auf, das an seinem Signaleingang on mit dem sinusförmigen Oszillatorsignal [hier auch als Normal -Taktsignal bezeichnet] beaufschlagt und an seinem Takteingang d mit den Flanken eines Empfangssignals getaktet wird. Des weiteren weist die Phasen- und Frequenzdetektorschaltung einen zweiten Phasendetektor in Form eines ebensolchen Abtast- und Speichergliedes PQ auf, das an seinem Signaleingang oq mit dem um 90° verzögerten sinusförmigen Oszillatorsignal [hier auch als Quadratur-Taktsignal bezeichnet] beaufschlagt und an seinem Takteingang ebenfalls mit den Flanken des Empfangεsignals getaktet wird. Ferner weist die Phasen- und Frequenzdetekf/or- schaltung eine Frequenzdetektorschaltung in Form eines eben- solchen Abtast- und Speichergliedes FD auf, das an seinem Signaleingang mit dem am Ausgang pq des zweiten Phaεendetektors PQ auftretenden abgetasteten Quadratur-Taktsignal beaufschlagt und an seinem Takteingang mit dem am Ausgang pn des ersten Phasendetektors PN auftretenden abgetasteten Normal - Taktεignal getaktet wird. Die Abtast- und Speicherglieder können dabei in an sich (z.B. aus IEEE J. of Solid-State Circuits, 27(1992)12, 1747 ... 1751, Fig. 3) bekannter Weise ausgebildet sein, so daεε eε hier keiner weiteren Erläute- rungen dazu bedarf.Memory element PN, which is acted upon at its signal input on with the sinusoidal oscillator signal [also referred to here as a normal clock signal] and is clocked at its clock input d with the edges of a received signal. Furthermore, the phase and frequency detector circuit has a second phase detector in the form of a scanning and storage element PQ of the same type, which acts on its signal input oq with the 90 ° delayed sinusoidal oscillator signal [also referred to here as a quadrature clock signal] and also on its clock input is clocked with the edges of the received signal. Furthermore, the phase and frequency detector circuit has a frequency detector circuit in the form of a Such sampling and storage element FD, which is scanned at its signal input with the sampled quadrature clock signal occurring at the output pq of the second phase detector PQ and clocked at its clock input with the sampled normal clock signal occurring at the output pn of the first phase detector PN. The scanning and storage elements can be designed in a manner known per se (for example from IEEE J. of Solid-State Circuits, 27 (1992) 12, 1747 ... 1751, FIG. 3), so that there is no further explanation here - Requires advice.
Bei der Abtastung des Normal -Taktsignals (on) und des Quadra- tur-Taktεignalε (oq) mit den Flanken des Emp angsεignals (d) erhält man an den Ausgängen pn, pq der beiden Abtast- und Speicherglieder PN, PQ zwei Signale, die sinus- bzw. coεinuε- förmig von der Phaεendif erenz zwiεchen Takt- und Datensignal abhängen. Diese Signalabhängigkeit ist in FIG 2 dargestellt. Daε Auεgangεsignal (pn) des ersten Phasendetektors PN kann als Stellsignal für die Phasenregelung eines Oszillators (VCO in FIG 1) in einer Phasenregelschleife genutzt werden, liefert aber für sich allein keine Information über das Vorzeichen einer etwaigen Frequenzablage des Oszillators, da am Phasendetektorausgang pn (in FIG 1) sowohl bei positiver als auch bei negativer Frequenzabläge des Oszillatorsignalε ein Sinussignal (pn in FIG 2 und FIG 3) ohne Richtungsinformation auftritt .When the normal clock signal (on) and the quadrature clock signal (oq) are sampled with the edges of the received signal (d), two signals are obtained at the outputs pn, pq of the two sampling and memory elements PN, PQ depend sinusoidal or cosine-shaped on the phase difference between clock and data signal. This signal dependency is shown in FIG. 2. The output signal (pn) of the first phase detector PN can be used as an actuating signal for the phase control of an oscillator (VCO in FIG. 1) in a phase locked loop, but does not in itself provide any information about the sign of a possible frequency offset of the oscillator, since pn (at the phase detector output a sinusoidal signal (pn in FIG. 2 and FIG. 3) without directional information occurs in FIG. 1) with both positive and negative frequency offsets of the oscillator signal.
Um auch eine Information über die Richtung einer Frequenzablage zu gewinnen, ist in der Phasen- und Frequenzdetektor- Schaltung gemäß FIG 1 die mit dem abgetasteten Quadratur- Taktsignal (pq) beaufschlagte und mit dem abgetasteten Normal-Taktsignal (pn) getaktete Frequenzdetektorschaltung FD vorgesehen, wobei das Stellsignal für den erforderlichenfalls in seiner Taktfrequenz nachzuführenden Oszillator VCO nach Maßgabe des am Ausgang pn des ersten Phasendetektors PN auftretenden abgetasteten Normal -Taktsignals (pn in FIG 2 und FIG 3) und des am Ausgang fd der Frequenzdetektorschaltung FD auftretenden Signals (fd in FIG 3) gebildet wird.In order to also obtain information about the direction of a frequency offset, the phase and frequency detector circuit according to FIG. 1 provides the frequency detector circuit FD to which the sampled quadrature clock signal (pq) is applied and which is clocked with the sampled normal clock signal (pn). wherein the control signal for the oscillator VCO to be tracked if necessary in accordance with the sampled normal clock signal (pn in FIG. 2 and.) occurring at the output pn of the first phase detector PN 3) and the signal occurring at the output fd of the frequency detector circuit FD (fd in FIG. 3) is formed.
Dabei ist die Frequenzdetektorschaltung FD nun mit einem ebensolchen Abtast- und Speicherglied wie die beiden Phasendetektoren PN und PQ gebildet, wobei die Frequenzdetektorschaltung FD mit dem abgetasteten Quadratur-Taktsignal (pq) beaufschlagt und mit dem abgetasteten Normal -Taktsignal pn (in FIG 3) getaktet wird; mit ihrem Ausgangεsignal fd (in FIG 3) wird dann das als Stellsignal für den in seiner Takt- frequenz nachzuführenden Oszillator (VCO in FIG 1) dienende Ausgangεεignal pn (in FIG 3) des ersten Phasendetektors PN gesperrt bzw. freigegeben.The frequency detector circuit FD is now formed with the same sampling and storage element as the two phase detectors PN and PQ, the frequency detector circuit FD being supplied with the sampled quadrature clock signal (pq) and clocked with the sampled normal clock signal pn (in FIG. 3) becomes; With its output signal fd (in FIG. 3), the output signal pn (in FIG. 3) of the first phase detector PN, which serves as a control signal for the oscillator to be tracked (VCO in FIG. 1), is then blocked or enabled.
Dabei wird bei jedem Nulldurchgang des am Ausgang pn (in FIG 1) des ersten Phasendetektors PN auftretenden Signals (pn in FIG 2 und FIG 3) der gerade zu diesem Zeitpunkt erreichte positive oder negative Extremwert des am Ausgang pq (in FIG 1) des zweiten Phasendetektors PQ auftretenden Signals (pq in FIG 2) auf den Ausgang fd (in FIG 1) der Frequenzdetektorschaltung FD übernommen und bis zum nächsten Nulldurchgang des Signals (pn in FIG 2 und FIG 3) gehalten. Das Ausgangεsignal (fd in FIG 2) der Frequenzdetektorschaltung FD gibt indessen noch keine (Richtungs- ) Information über das Vorzei- chen der Frequenzablage, sondern zeigt, ausgehend von einem geradzahligen Vielfachen von π, mit einem negativen Vorzeichen (Signalzustand LOW) einen in einem Bereich zwischen ± π und ± 2π liegenden Phasenfehler an.With each zero crossing of the signal occurring at the output pn (in FIG. 1) of the first phase detector PN (pn in FIG. 2 and FIG. 3), the positive or negative extreme value of that at the output pq (in FIG. 1) of the second just reached at this point in time Phase detector PQ occurring signal (pq in FIG 2) on the output fd (in FIG 1) of the frequency detector circuit FD and held until the next zero crossing of the signal (pn in FIG 2 and FIG 3). The output signal (fd in FIG. 2) of the frequency detector circuit FD, however, does not yet give any (directional) information about the sign of the frequency offset, but instead, based on an even multiple of π, shows one in one with a negative sign (signal state LOW) Range between ± π and ± 2π phase errors.
Eine Richtungsinformation kann jetzt aber dadurch gewonnen werden, daß das Ausgangssignal (pn in FIG 2) des erεten Phasendetektors PN in denjenigen Phasenbereichen, in denen fd = LOW ist, unterdrückt wird und nur beim Signalzustand fd = HIGH zur Oszillatornachstellung freigegeben wird.However, directional information can now be obtained in that the output signal (pn in FIG. 2) of the first phase detector PN is suppressed in those phase ranges in which fd = LOW and is only released for oscillator adjustment when the signal state is fd = HIGH.
Der die Sperrung und Freigabe des Signals (pn in FIG 3) bewirkende Schalter M (in FIG 1) kann beiεpielsweise eine Mul- tiplikationsschaltung sein, wie sie in FIG 4 in bipolarer differentieller ECL-Technik dargestellt ist. In dieser Schaltung wird beim Signalzuεtand fd = HIGH über die dabei vom Transistor T5 her entriegelte Differenzstufe T1/T2 mit einer Verstärkung v = 1 daε Eingangssignal pn zum Ausgang pfd hin durchgeschaltet ; ist fd = LOW, so wird vom Transistor T6 her die mit 0 V Spannungsdifferenz angesteuerte Differenzstufe T3/T4 entriegelt, so daß auch am Ausgang pfd eine Differenz - Spannung von 0 V auftritt.The switch M (in FIG. 1) which blocks and enables the signal (pn in FIG. 3) can, for example, tiplication circuit, as shown in FIG 4 in bipolar differential ECL technology. In this circuit, when the signal state fd = HIGH, the differential stage T1 / T2, which is unlocked by the transistor T5, is switched through with an amplification v = 1 of the input signal pn to the output pfd; If fd = LOW, the transistor T6 unlocks the differential stage T3 / T4, which is controlled with a 0 V voltage difference, so that a differential voltage of 0 V also occurs at the output pfd.
Am Ausgang pfd steht nun ein Phasendetektorsignal zur Verfügung, das bei von der Datenrate abweichender Oszillatorfrequenz einen Gleichanteil mit richtiger Polarität zur Oszillatorregelung aufweist, wie die folgende Überlegung zeigt:A phase detector signal is now available at the output pfd, which has a DC component with correct polarity for oscillator control when the oscillator frequency deviates from the data rate, as the following consideration shows:
Ist die Oszillatorfrequenz zu hoch, so werden die Kennlinien pn und pq (in FIG 2) von links nach rechts durchlaufen. Bei einem Nulldurchgang in eine negative Halbwelle der Kennlinie pn wird daε - hier positive - abgetastete Quadratur-Taktsig- nal (pq in FIG 2) auf den Auεgang fd (in FIG 1) der Frequenzdetektorschaltung FD übernommen (und biε zum nächεten Null- durchgang des abgetaεteten Normal -Taktεignals (pn in FIG 2) gehalten) , wobei der Schalter M entriegelt wird, so daß eine negative Halbwelle des Phasendetektorignals pn zum Ausgang pfd gelangt. Beim nachfolgenden Nulldurchgang in die positive Halbwelle der Kennlinie pn wird das - hier negative - abgetastete Quadratur-Taktsignal (pq in FIG 2) auf den Ausgang fd (in FIG 1) der Frequenzdetektorschaltung FD übernommen (und bis zum nächsten Nulldurchgang des abgetasteten Normal -Takt- signals (pn in FIG 2) gehalten) , wobei der Schalter M gesperrt wird, so daß keine positive Halbwelle des Phasendetek- torsignals pn zum Ausgang pfd gelangt . Am Steuereingang des Oszillators VCO erhält man damit eine Folge von negativen Sinushalbwellen, deren negativer Gleichanteil eine Erniedrigung der Oszillatorfrequenz bewirkt. Ist umgekehrt die Oszillatorfrequenz zu niedrig, so werden die Kennlinien pn und pq (in FIG 2) von rechts nach links durchlaufen. Nunmehr wird bei einem Nulldurchgang in die positive Halbwelle der Kennlinie pn daε - hier positive - abge- tastete Quadratur-Taktsignal (pq = HIGH) auf den Ausgang fd (in FIG 1) der Frequenzdetektorschaltung FD übernommen (und bis zum nächsten Nulldurchgang des abgetasteten Normal- Taktsignalε (pn in FIG 2) gehalten) , wobei der Schalter M entriegelt wird, so daß eine positive Halbwelle des Phasen- detektorsignalε pn zum Auεgang pfd gelangen. Beim nachfolgenden Nulldurchgang in die negative Halbwelle der Kennlinie pn wird daε - hier negative - abgetastete Quadratur-Taktsignal (pq = LOW) auf den Ausgang fd (in FIG 1) der Frequenzdetektorschaltung FD übernommen (und bis zum nächsten Nulldurch- gang des abgetasteten Normal -Taktsignals (pn in FIG 2) gehalten) , wobei der Schalter M gesperrt wird, so daß keine negative Halbwelle des Phasendetektorsignals pn zum Auεgang pfd gelangt. Am Steuereingang des Oszillators VCO erhält man damit eine Folge von positiven Sinushalbwellen, deren positiver Gleichanteil eine Erhöhung der Oszillatorfrequenz bewirkt.If the oscillator frequency is too high, the characteristic curves pn and pq (in FIG. 2) are run through from left to right. In the event of a zero crossing into a negative half-wave of the characteristic curve pn, the - here positive - sampled quadrature clock signal (pq in FIG. 2) is taken over to the output fd (in FIG. 1) of the frequency detector circuit FD (and until the next zero crossing of the sampled normal clock signal (pn in FIG. 2)), the switch M being unlocked so that a negative half-wave of the phase detector signal pn reaches the output pfd. During the subsequent zero crossing into the positive half-wave of the characteristic curve pn, the - here negative - sampled quadrature clock signal (pq in FIG. 2) is applied to the output fd (in FIG. 1) of the frequency detector circuit FD (and until the next zero crossing of the sampled normal clock pulse - Signals (pn in FIG 2) held, the switch M being blocked so that no positive half-wave of the phase detector signal pn reaches the output pfd. At the control input of the oscillator VCO, a sequence of negative sine half-waves is thus obtained, the negative DC component of which causes the oscillator frequency to be lowered. Conversely, if the oscillator frequency is too low, the characteristic curves pn and pq (in FIG. 2) are run through from right to left. Now with a zero crossing into the positive half-wave of the characteristic curve pn daε - here positive - sampled quadrature clock signal (pq = HIGH) is taken over to the output fd (in FIG. 1) of the frequency detector circuit FD (and until the next zero crossing of the sampled normal - Clock signal (pn held in FIG. 2), the switch M being unlocked so that a positive half-wave of the phase detector signal pn reaches the output pfd. During the subsequent zero crossing into the negative half-wave of the characteristic curve pn, the - here negative - sampled quadrature clock signal (pq = LOW) is applied to the output fd (in FIG. 1) of the frequency detector circuit FD (and until the next zero crossing of the sampled normal - Clock signal (pn held in FIG 2), the switch M being blocked so that no negative half-wave of the phase detector signal pn comes to the output pfd. At the control input of the oscillator VCO, a sequence of positive sine half-waves is obtained, the positive DC component of which increases the oscillator frequency.
Stimmen Oεzillatorfrequenz und Datenrate überein, εo wird die Phaεe der Oszillatorschwingung stets nur in der Umgebung eines Nulldurchgangε deε Phasendetektorsignals pn geregelt, an welchem pq = HIGH ist, d.h. bei einer bei geradzahligen Vielfachen von π liegender Phasendifferenz. Ein Einrasten bei ungeradzahligen Vielfachen von π ist dagegen nicht möglich, da das Nachsteuersignal in der Umgebung solcher Punkte gesperrt ist. Der Phasendetektor PN lässt sich daher ohne Gefahr der Bildung einer mehrdeutigen Kennlinie als lineare Abtastschaltung mit einem relativ großem linearen Bereich auslegen. If the oscillator frequency and data rate match, the phase of the oscillator oscillation is only ever regulated in the vicinity of a zero crossing of the phase detector signal pn, at which pq = HIGH, i.e. with a phase difference lying at even multiples of π. On the other hand, it is not possible to lock in at odd multiples of π, since the readjustment signal is blocked in the vicinity of such points. The phase detector PN can therefore be designed as a linear scanning circuit with a relatively large linear range without the risk of forming an ambiguous characteristic.

Claims

PatentanspruchClaim
Phasen- und Frequenzdetektorschaltung mit einem ersten Phasendetektor in Form eines mit einem si- nusförmigen Oszillatorsignal [Normal -Taktsignal] (on) beaufschlagten und mit den Flanken eines Empfangsεignals (d) getakteten Abtast- und Speichergliedes (PN) , mit einem zweiten Phasendetektor in Form eines ebensolchen, mit dem um 90° verzögerten Oszillatorsignal [Quadratur-Takt - signal] (oq) beaufschlagten und mit den Flanken des Empfangs - signals (d) getakteten Abtast- und Speichergliedes (PQ) , und mit einer mit dem das Ausgangssignal (pq) des zweiten Phasendetektorε (PQ) bildenden abgetasteten Quadratur-Takt - εignal (pq) beaufεchlagten und mit dem das Ausgangssignal (pn) des ersten Phasendetektorε (PN) bildenden abgetaεteten Normal -Takt ignal (pn) getakteten Frequenzdetektorschaltung (FD) , wobei das Stellsignal für den Oszillator nach Maßgabe des abgetaεteten Normal-Taktεignalε und des Ausgangssignals (fd) der Frequenzdetektorschaltung gewonnenen wird, dadurch gekennzeichnet, daß die Frequenzdetektorschaltung mit einem ebensolchen, mit dem abgetasteten Quadratur-TaktSignal (pq) beaufschlagten und mit dem abgetasteten Normal -Taktεignal (pn) getakteten Abtast - und Speicherglied (FD) gebildet ist, mit dessen Ausgangssignal (fd) das Ausgangssignal (pn) des ersten Phaεendetektorε (PN) gesperrt bzw. freigegeben wird. Phase and frequency detector circuit with a first phase detector in the form of a scanning and storage element (PN) acted upon with a sinusoidal oscillator signal [normal clock signal] (on) and clocked with the edges of a received signal (d), with a second phase detector in the form the same, with the oscillator signal delayed by 90 ° [quadrature clock signal] (oq) and clocked with the edges of the received signal (d), the scanning and storage element (PQ), and one with which the output signal (pq ) of the sampled quadrature clock signal (pq) forming the second phase detector (PQ) and clocked frequency detector circuit (FD) with the sampled normal clock signal (pn) forming the output signal (pn) of the first phase detector (PN), the actuating signal is obtained for the oscillator in accordance with the sampled normal clock signal and the output signal (fd) of the frequency detector circuit, thereby nnzeich that the frequency detector circuit is formed with the same, with the sampled quadrature clock signal (pq) and with the sampled normal clock signal (pn) clocked sampling and memory element (FD), with its output signal (fd) the output signal (pn ) of the first phase detector (PN) is blocked or released.
PCT/DE1997/001500 1996-07-31 1997-07-16 Phase and frequency detector circuit WO1998006179A1 (en)

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EP0910897A1 (en) * 1996-07-08 1999-04-28 Maxim Integrated Products, Inc. Phase locked loop with improved phase-frequency detection
EP0910897A4 (en) * 1996-07-08 2000-02-02 Maxim Integrated Products Phase locked loop with improved phase-frequency detection
EP1116323A1 (en) * 1998-08-27 2001-07-18 Maxim Integrated Products Lock-in aid frequency detector
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EP1199804A2 (en) * 2000-10-19 2002-04-24 Nec Corporation Phase/frequency comparator
EP1199804A3 (en) * 2000-10-19 2004-01-07 Nec Corporation Phase/frequency comparator

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