WO1998004063A2

WO1998004063A2 - A method and an apparatus for recovery of the clock of a constant bit-rate service

Info

Publication number: WO1998004063A2
Application number: PCT/SE1997/001168
Authority: WO
Inventors: Sebastiano Lomuscio
Original assignee: Telefonaktiebolaget Lm Ericsson (Publ)
Priority date: 1996-07-19
Filing date: 1997-06-27
Publication date: 1998-01-29
Also published as: WO1998004063A3; SE9602823L; AU3563697A; SE9602823D0

Abstract

The present invention relates to a method, an apparatus and a network for recovery of the clock of a constant bit-rate service transported over a packet-switched network. The invention measures the inter-arrival time, Wn, between consecutive packages, filter the results through a noise reduction function (27, 52) and calculates a mean value (28) of the inter-arrival times. If the derivative (38) of the mean values is less than an error level (39) for a specified number of times (42), the frequency (18) with which the arrival buffer is polled is adjusted to comply with the frequency with which the CBR service is sent. Whenever the frequency (18) is adjusted a new period for the calculation of the mean values is started. To be able to react faster at start-up, the error level is reduced down to a specified minimum level (45) when the frequency is adjusted.

Description

A METHOD. AN APPARATUS AND A NETWORK FOR CLOCK RECOVERY FIELD OF THE INVENTION

The present invention relates to a method, an apparatus and a network for recovering the clock of a constant bit-rate service, which is transported over an packet-switched network.

BACKGROUND OF THE INVENTION

Through WO, Al , 95/33320 it is known to recover a clock signal by periodically sample a buffer fill level and adjusting a clock frequency to achieve a steady-state mean of the buffer fill level or its derivative.

Through WO, Al , 95/22233 it is known to submit to the first packet, of a sequence of packets, a predetermined delay after that the fill level of a delay buffer is monitored and subsequent packages are submitted to a variable delay to maintain the fill level of said buffer to minimise the risk of over- or underflow of said buffer.

In IEEE 1988 ref. CH2535-3/88/0000-1468 a time-averaging method and an optimal control method is presented.

SUMMARY OF THE INVENTION

To be able to transport a synchronous service with a CBR (Constant Bit-Rate) over an asynchronous packet-switched network there must exist some means to match the clock frequency at the receiving end to the clock frequency at the transmitting end. This is essential so that buffers on the receiving side does not drain or overflow. If the clock frequency at the receiving side is a fraction too fast the frequency with which the receiving buffer is emptied is greater than the frequency with which it is filled, which eventually will lead to a temporary stop of the CBR service. If, on the other hand, the receiving clock is too slow the receiving buffer will overflow and data will be lost. One way of achieving same clock frequency on both transmitting and receiving side is to supervise the periodic arrivals of the CBR traffic and adjust the receiving clock frequency accordingly. This is, however, not a straigh -forward task since each cell is submitted to individual delays, so called cell jitter.

The cell jitter is the result of the multiplexing and queuing in the packet-switched network. The cell queuing in a switch introduce a delay which is related to the traffic congestion the switch is experiencing. The traffic congestion, in turn, depends on the traffic from other sources and their inter-arrival time distributions. The delay introduced for multiplexing depends on the multiplexing policies of the switches the cell passes on its way to the receiver.

One major problem with transporting CBR services over packet- switched networks is therefore to find a stable and secure way of recovering the clock-signal at the receiving end.

Another problem which the present invention solves is to avoid excessive clock wander.

Another problem which this invention solves is to achieve rapid convergence times for the regulation of the clock frequency.

Another problem which the invention solves is to avoid destructive effects of cell-loss on the regulation.

The object with the present invention is to secure a safe transport of a CBR service over a packet-switched network.

Another objective with the present invention is to recover the clock of a CBR service transported over a packet-switched network.

The present invention solves the problem with recovering the clock signal of a CBR service which is transported over a packet-switched network by filtering the measured packet inter- arrival times, taking the mean-value of the result over a certain period, depending on the value of the derivative, or the value of several consecutive derivatives, of the mean-values adjusting the period used for taking the mean-values and depending on the value of the derivative adjusting the clock frequency for fetching cells from the receive buffer.

In more detail the proposed solution measures the time between two consecutive cell arrivals. By continuously measuring this time, and from each value subtract the expected inter-arrival time, a Series of samples, with the expected mean value of zero, is produced. This series of samples is passed through a filter in order to reduce the noise. From the filter the modified series is passed to a Mean estimator. The Mean estimator takes the mean-value, from a start sample and up to the current sample. That is, for every new sample the Mean estimator adds the value of the sample to a stored sum and takes the mean of this sum. This will result in a series of samples from the Mean estimator, this series is supplied to a Mean slope control block which takes the derivative of the supplied series and depending on the value of the derivative, or the value of several consecutive derivatives, resets the sum of the Mean estimator to zero and supplies information to adjust the clock frequency for fetching data from the receiving buffer.

The advantage with the invention is that it has a fast convergence time.

Another advantage is that the invention is not sensitive to rapid change in network traffic load.

Another advantage is that the invention is not sensitive to loss or misinserted cells. Another advantage is that the invention can be implemented on a IC (integrated Circuit) or with a DSP (Digital Signal Processing) device and only a few extra components.

The invention will now be described with help of preferred embodiments and with references to the supplied drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows the principal of sending CBR service over a packet-switched network.

Figure 2 shows a block diagram of the principals of receiving CBR data.

Figure 3 shows a block diagram of the clock recovery system in figure 2 according to the invention.

Figure 4 shows a flow diagram of the Mean slope control block in figure 3 according to the invention.

Figure 5 shows an implementation of the digital low-pass filter in figure 4 according to the invention.

Figure 6 shows buffer occupancy results from a simulation according to the invention.

Figure 7 shows clock frequency results from a simulation according to the invention.

Figure 8 shows output from the Mean estimator from a simulation according to the invention.

BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS

In figure 1 two Narrow Band Terminals 1 are sources of CBR services 5. They need to establish a virtual circuit to communicate with each other over the Packet-Switched Network 3. In most cases the Packet-Switched Network 3 will be an ATM (Asynchronous Transfer Mode) network. This is of course not always so and the Packet-Switched Network 3 can be of many other types, for instance X.25, Token Ring, Ethernet, etc. In this embodiment the Packet-Switched Network 3 is an ATM network.

Since the transmission and the switching in the ATM network introduces a variable transfer delay it is more suitable for transmission of bursty data than data from a CBR service 5. For this reason an adaptation for the transport of the CBR traffic 5 is performed by the CE (Circuit Emulation functionality) 2. The CE 2 performs necessary adaptations to emulate all the services of a Tl/El circuit that is virtually connected to the remote Narrow Band Terminal 1. If the ATM network 3 is seen as the future broadband network (B-ISDN, Broadband-Integrated Services Digital Network) and the Narrow Band Terminals 1 operates in the existing narrowband network (N-ISDN, Narrowband-Integrated Services Digital Network) the CE 2 can be seen as providing the integration, being a inter-working unit, between these two networks. The CE 2 interfaces, on the broadband side, the ATM cells and, on the narrowband side, the synchronous bitstream from the CBR signal 5. The CBR signal 5 is segmented, by the CE 2, into 376 bits units, which is equal to 47 octets and then mapped into the payload field of an ATM cell. The cell is then routed through the ATM network 3.

One of the services that shall be provided by the CE 2 is the recovery of the remote source clock information 4. This is essential to the proper delivery of the CBR service traffic since any frequency errors in the clock controlling the destination buffer operation results in buffer over- or underflow. Only little is known about the ATM cell jitter, caused by queuing and multiplexing of the ATM cells in the ATM network, also called CDV (Cell Delay Variation) , beyond that the average cell delay is constant, assuming that the cell loss probability is negligible. All previously known clock recovery methods start from this hypothesis. The present invention starts from a weaker hypothesis that allow it to be functional even if the cell loss probability is not negligible.

In figure 2 is a functional block diagram for the receiving side of a CE 2 shown. The ATM cells are received from the ATM network 11 through the ATM adapter 9 and processed in the AALl (ATM Adaptation Layer 1 ) 8. The AALl block 8 terminates the AALl protocol and extracts from each cell 47 octets which corresponds to 376 bits of the CBR service traffic. Each time a valid ATM cell is received in the AALl block 8 a signal 14 is sent to the Clock Recovery System 10. The output of the Clock Recovery System 10 is the clock 15 used to re-generate the CBR service traffic from the cells to the 2 Mbit/s line 16. This 2 Mbit/s stream is passed to the Narrowband Terminal through the Line I/F transceiver block 7.

In figure 3 is a detailed functional block diagram of the Clock Recovery System 10 in figure 2 shown. When a valid ATM cell is received in the AALl block 8 in figure 2 a signal is raised which arrives on line 22 in figure 3 and applied to a first 32- bit latch 21, a second 32-bit latch 23, an computation block 26 and a Digital low-pass filter 27. The clock source in this embodiment is a VCXO quartz voltage controlled oscillator 18 with frequency f_s 36. It has a high degree of stability in frequency in respect to the applied voltage and temperature. Its output frequency, f_s 36, can be assumed to be constant for a given input control voltage. The generated frequency f_s 36 is applied to a PLL (Phased Locked Loop) 19 used to multiply the VCXO frequency /, with a constant M . This multiplication is done to be able to measure the cell inter-arrival time with enough accuracy. The cell inter-arrival time is measured by applying the M x f_s clock to a free running 32-bit counter 20. The output of this counter 20 is latched from the first 32-bit latch 21 when a cell is received. The preceding value X_n_, 25 of the 32-bit counter 20 is stored in the second 32-bit latch 23 and is fed to the computation block 26 together with the current value X_π 24.

By letting M cells interarrival times be accumulated in the 32-bit counter the need for the PLL can be eliminated.

Let's call the unknown transmitter clock /, . Each cell is transmitted when 47 octets, corresponding to 47x8=376 bits, has been stored in the cell. Therefore the cell generation period is:

376 = ^■ f,

Let's suppose that the ATM network introduces a constant delay in the transport of each cell. With this assumption the cell inter-arrival time is constant and equal to T_c . In this case we can evaluate the number of counted periods w_π , which is directly corresponding to the inter-arrival time, that represent the T_c value :

^w„ =

The fractional residual part of the result is accumulated by the counter 20 and counted as a unit when a sufficient number of cells has been received. In this way the precision of the timing measurement is maintained and very low clock differences can be measured. If the two frequencies f. and /, are equal the expected value for w_n is: vv^= Mx376

To obtain a value that is equal to zero when j. and f_t are equal the following calculation is performed by the computation block 26 when a cell is received: y_n = *- ~ w_Λ = {x_n - *„_, )- (M x 376) The output y_n 53 from the computation block 26 is applied to a digital low-pass filter 27 with a sampling period equal to T_c .

The purpose of the digital low-pass filter 27 is to integrate the result of the previous blocks and to reduce the effect of the jitter in the CDV. The digital low-pass filter 27 accept a new sample and generates a new value z_n 30 when a new cell arrives .

Instead of using a μllR digital low pass filter, a FIR (Finite Impulse Respons) filter can be used. The FIR filter can be optimised to, in an adaptive way, have a certain amount of noise .

From the digital low-pass filter a clock signal 29 is supplied to the Mean estimator 28 and the Mean slope control block 33. Depending on the implementation of the digital low-pass filter 27 the clock signal 22 and the clock signal 29 can be different.

The output z_n 30 of the digital low-pass filter 27 is applied to a Mean estimator 28. This block performs the mean evaluation of the received z_n 30 producing a sequence of output values m_k 31 according to the following formula: k-\

Σ*. ^m- ⁼JX where s is a start position for the mean-value calculation. This block can be reset by zeroing the accumulated sum and setting s - k . The m_t sequence 31 is applied to the Mean slope control block 33 which is responsible for the decision on how many z„ 30 samples the Mean estimator block 28 must accumulate to obtain a good estimation of the mean cell inter-arrival time. The block also performs the evaluation of the correction value e. 54 to be applied to the control block 34. The value e, 54 is maintained stable until a new value is calculated and supplied to the Control block 34. The Control block 34 maintains a value d_t which is supplied to a D/A Converter 35 which converts the value d, to a voltage supplied to the VCXO clock 18. The Mean slope control block 33 also determines when to reset 32 the Mean estimator 28. When a new e_t 54 value is supplied to the Control block 34 a new d_t value is computed according to:

which new d. value will, through the D/A Converter 35, change the voltage and thereby the frequency of the VCXO clock 18.

In figure 4 a flow diagram of the Mean slope control block 33 in figure 3 is shown. When a new m_k value arrives 37, the derivative c_k 38 of the m_k sequence is computed according to:

A test 39 is performed on the value of c_k . If c_k is less than or equal to an error level, err , a counter, count , is increased 41. If c_k is greater than err , count is set to zero 40. If the test 42 count ≥ Maxcnt is true a new e_t value is computed 43 according to: e. = m_k x Gain and is applied 46 to the control block 34 in figure 3. The Mean estimator is also reset through 46.

By waiting Maxcnt number of times before computing a new e_t enough samples has been collected by the Mean estimator 28 to be able to calculate a good enough mean value. This in turn means that the m_k value used to calculate the e.. value will not fluctuate too much. This is in accordance with the asymptotic convergence property of the Mean estimator 28. This property is reflected by the slope of the m_k sequence that asymptotically tends to zero.

Every time an e. value is computed the err value is reduced 45 down to a predefined minimum error level, Minerr 44. This is to achieve rapid convergence at start-up and better precision when the system is stable. By resetting the Mean estimator 28 after each correction the effect of cell loss or misinsertion on the system convergence is removed.

Figures 6, 7 and 8 shows the results of simulations done according to the invention. The simulations has been executed by using a VERILOG system description. The following values has been used in the simulation:

Traffic inter-arrival time, mean value: 183.5937 μs Traffic inter-arrival time, variance: 20 μs Initial err value: IE^"3 Minerr value : IE^"6 M value : 8 VCXO frequency: 2 . 048 Mhz

1

The Gain value : 0.05 x [

376 x M x 2.048 J Maxcnt value: 16

The simulated traffic source is the output of an ATM switch with a load of 90% having an output speed of 155 Mbit/s.

Figure 6 represent the AALl buffer size. The figure qualify the behaviour of the invention, as can be seen the buffer size is stable.

Figure 7 represent the clock generated from the VCXO 18. While figure 8 shows the output of the Mean estimator 28. Note the asymptotic convergence of the m_k sequence. The invention is of course not limited to the above described and on the drawings shown preferred embodiments, but can also be modified in agreeement with the supplied claims.

Claims

1. A method for recovery of the clock frequency of a constant bit-rate service carried over a packet-switched network comprising storage means for temporarily storing the data at the receiving end, and a clock frequency (18) with which the data is polled out of said storage means, CHARACTERISED in that a first series of time differences, w_n, between consecutive packet arrivals is computed, that said series^' of time differences, w_n, is applied to a Mean estimator (28) wherein said Mean estimator comprises means to compute a series of mean values, m_k (31), from said series of time differences, w_n, that each sample in said series of mean values, m_k (31), is calculated over a period T_r, that said series of mean values is applied to a Mean slope control block (33), wherein said Mean slope control block comprises means for computing a series of derivatives, c_k (38), from said series of mean values and depending on the value of said derivative or the values of several consecutive derivatives adjust said clock frequency (18) and said period T_r.

2. A method according to claim 1, CHARACTERISED in that a second series of time differences, y_n, (53) is calculated by subtracting, from each sample in said first series of time differences, w_n, the expected mean value interarrival time.

3. A method according to claim 2, CHARATERISED in that before said Series of mean-values, m_k, (31) is calculated said first or second series of time differences, w_n or y_n (53), is passed through a noise reduction function (27) producing a third series of time differences, z_n (30).

4. A method according to claim 3, CHARACTERISED in that said noise reduction function is performed using a digital low pass filter (52) with a period equal to the expected interarrival time, T_c.

5. A method according to claim 3 , CHARACTERISED in that said noise reduction function is performed using a finite impulse response filter.

6. A method according to claim 5 , CHARACTERISED in that said finite impulse response filter is adaptively optimized for a specific noise level .

7. A method according to claim 3 , CHARACTERISED in that for each sample in the first series of time differences, w_n, a new sample of said second series of time differences, y_n, (53) is calculated, a new sample of said third series of time differences, z_n, (30) is calculated, a new sample of said series of mean values, m_k (31) , is calculated, and a new sample of said series of derivatives, c (38), is calculated.

8. A method according to claim 3, CHARACTERISED in that for each sample in the first series of time differences, w_n, a new sample of said second series of time differences, y_n (53), is calculated and that for a specific number of samples in the first series of time differences, w_n, a new sample of said third series of time diferences, z_n (30), is calculated, a new sample of said series of mean values, m (31), is calculated, and a new sample of said series of derivatives, c_k (38) , is calculated.

9. A method according to claim 8, CHARACTERISED in that said specific number of samples in said first time series, w_n, is eight.

10.A method according to claim 4, CHARACTERISED in that data passed to said digital low pass filter (52) is passed to a first low pass filter (47) , that data from the first low pass filter (47) is applied to a decimator (48), that data from said decimator (48) is applied to a second low pass filter (49) and that said decimator (48) supplies a clock signal (29, 51) to said Mean estimator (28) and to said Mean slope control block (33) .

11.A method according to claim 1, CHARACTERISED in that if the absolute value of a sample in said Series of derivatives, c_k (38), is less than, or equal to, an error level (39) a counter is increased (41) , that if said absolute value is greater than said error level (39) said counter is set to zero (40), that if said counter (39,40) is greater than a maxcounter level (42) the clock frequency (18) is adjusted and the period, T_r, over which said mean-values is calculated is adjusted.

12.A method according to claim 11, CHARACTERISED in that if said error level (39) is greater than or equal to a predefined minimum error level (44) said error level is decreased (45).

13.A method according to claim 1 or claim 11, CHARACTERISED in that said clock frequency (18) is adjusted by applying a sample value, c_k (38), of said calculated derivative multiplied by a gain value, Gain (43), to a control block

(34) wherein said control block holds a value, d , and adds said value, c_k*Gain (43), to said value, d_x, that said value, i, is applied to a digital/analog converter (35) and that the output of said digital/analog converter (35) is applied to the clock supplying said clock frequency (18) .

14.A method according to claim 1 or claim 11, CHARACTERISED in that each sample in said Series of mean-values, m (31) , is calculated by adding the current sample value to a sum, adding one to the number of received samples, and dividing the sum with the number of received samples and, depending of the value of said derivative, c_k (38), that said period, T_r, over which said mean values, m_k (31), is calculated is adjusted by setting said sum and said number of samples in said mean estimatior to zero.

15.A method according to claim 1, CHARACTERISED in that said time differences, w_n, is calculated by raising a signal (22) when a packet is received, that the value of a free-running counter (20) with a known frequency is stored (21) when said signal (22) is raised and, that the value, x-ι (25), for the previously arrived packet, of the free-running counter, is subtracted from the value, x_n (24), of the current packet.

16.An apparatus for recovery of the clock frequency of a constant bit-rate service carried over a packet-switched network comprising storage means for temporarily storing the data at the receiving end and a clock (18) arranged to determine the rate of polling data from said storage means, CHARACTERISED in said apparatus comprising means for computing time differences between two consecutive arriving packets (20, 21, 23, 26), means for noise reduction (27, 52), a Mean estimator (28) , a Mean slope control block (33) and means for adjusting the frequency (34, 35) with which said clock (18) operates.

17.An apparatus according to claim 16, CHARACTERISED in that said Mean slope control block (33) comprises means for calculating the derivative (38) of the input data, means for adjusting (32, 46) the period over which said Mean estimator (28) is provided for calculating mean values and means for supplying data (46) to said means for adjusting said clock frequency (34, 35) .

18.An apparatus according to claim 16, CHARACTERISED in that said means for noise reduction (27) is a digital low pass filter with a period equal to the expected inter-arrival time, T_c.

19.An apparatus according to claim 16, CHARACTERISED in that said means for noise reduction (27) is a finite impulse response filter.

20.An appartus according to claim 18, CHARACTERISED in that said digital low pass filter (27, 52) comprises a first low pass filter (47), a decimator (48) and a second low pass filter (49) and that said decimator (48) comprises means for supplying a clock signal (51) to said Mean estimator (28) and to said Mean slope control block (33) .

21.A packet-switched network comprising means for transmitting and receiving a constant bit-rate service between at least two nodes in said network, CHARACTERISED in that said means for transmitting and receiving a constant bit-rate service comprises means for recovery of the constant bit-rate clock (10), that said means for recovery of said clock further comprises means for computing time differences between two consecutive arriving packets (20, 21, 23, 26), means for noise reduction (27, 52), a clock arranged to determine the rate for receiving packets, means for adjusting the frequency of said clock, a Mean estimator (28) and a Mean slope control block (33) .

22.A packet-switched network according to claim 21, CHARACTERISED in that said Mean slope control block (33) comprises means for calculating the derivative (38) of the input data, said Mean slope control block (33) comprising means for adjusting (46) the period over which said Mean estimator (28) calculates mean values, and said Mean slope control block (33) comprising means for supplying (46) data to said means (34, 35) for adjusting said clock frequency (18) .

23.A packet-switched network according to claim 21, CHARACTERISED in that said means for noise reduction (27) is a digital low pass filter (27, 52) with a period equal to the expected inter-arrival time, T_c .

24.A packet-switched network according to claim 21, CHARACTERISED in that said means for noise reduction (27) is a finite impulse response filter.

25.A packet-switched network according to claim 23, CHARACTERISED in that said digital low pass filter (27, 52) comprises a first low pass filter (47) , a decimator (48) and a second low pass filter (49) and that said decimator (48) comprises means for supplying a clock signal (51) to said Mean estimator (28) and said Mean slope control block (33) .