WO1997041592A1 - Couches superposees dielectriques a faible permittivite constituees d'oxyde fluore pour couplage capacitif reduit - Google Patents

Couches superposees dielectriques a faible permittivite constituees d'oxyde fluore pour couplage capacitif reduit Download PDF

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Publication number
WO1997041592A1
WO1997041592A1 PCT/US1996/020485 US9620485W WO9741592A1 WO 1997041592 A1 WO1997041592 A1 WO 1997041592A1 US 9620485 W US9620485 W US 9620485W WO 9741592 A1 WO9741592 A1 WO 9741592A1
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WO
WIPO (PCT)
Prior art keywords
dielectric
oxide
dielectric layer
forming
dielectπc
Prior art date
Application number
PCT/US1996/020485
Other languages
English (en)
Inventor
Robert Dawson
Fred N. Hause
Basab Bandyopadhyay
Mark W. Michael
H. Jim Fulford
William S. Brennan
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO1997041592A1 publication Critical patent/WO1997041592A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to semiconductor device fabrication and more particularly to a low permittivity mterlevel dielectric structure and method for producing the same
  • An integrated circuit includes numerous conductors extending across the topography of a monolithic substrate.
  • a set of interconnect lines (.or conductors) which serve to electrically connect two or more components within a svstem is generally referred to as a "bus " .
  • a collection ot voltage levels are forwarded across the conductors to allow proper operation of the components.
  • a microprocessor is connected to memories and input output devices by certain bus structures.
  • busses There are numerous types of busses which are classified according to their operation. Examples of well-known types of busses include address busses, data busses, and control busses.
  • Conductors within a bus generally extend parallel to each other across the semiconductor topography.
  • the conductors are isolated from each other and from underlying conductive elements by a dielectric, a suitable dielectric being, for example, silicon dioxide ("oxide").
  • Conductors are thereby lithography patterned across the semiconductor topography, wherein the topography comp ⁇ ses a substrate with a dielectric placed thereon.
  • the topography can also include one or more layers of conductors which are sealed by an upper layer of dielectric mate ⁇ al Accordingly, the layers of conductors overlaid with a dielectric present a topography upon which a subsequent layer of conductors can be patterned.
  • Conductors are made from an electrically conductive material, a suitable material includes Al. Ti. Ta, W, Mo. polysilicon. or a combination thereof.
  • Substrate includes any type of material which can retain dopant ions and the isolated conductivity regions brought about by those ions.
  • substrate is a silicon-based mate ⁇ al which receives p-type or n-type ions.
  • interconnect lines are fashioned upon the topography and spaced above an underlying conductor or substrate by a dielectric of thickness T d
  • Each conductor is dielectncally spaced from other conductors within the same level of conductors by a distance T ,.
  • mterlevel capacitance C L S i.e., capacitance between conductors on different levels
  • Cn imralevel capacitance between conductors on the same level
  • ⁇ is the permittivity ofthe dielectric material (the dielectric material between the conductor and substrate or the dielectric mate ⁇ al between conductors)
  • W is the conductor width.
  • T c is the conductor thickness, and L is the conductor length. Resistance ofthe conductor is calculated as follows:
  • Propagation delay is an important characteristic of an integrated circuit since it limits the speed (frequency) at which the circuit or circuits can operate The sho ⁇ er the propagation delay, the higher the speed of the circuit or circuits It is therefore important that propagation delay be minimized as much as possible within the geometric constraints ofthe semiconductor topography
  • Equation 4 shows that the propagation delay of a circuit is proportional to the parasitic capacitance values (C LL ) between laterally spaced conductors, and parasitic capacitance values (C LS ) between vertically spaced conductors or between a conductor and the underlying subsrrate. As circuit density increases, lateral spacing and vertical spacing between conductors decrease and capacitance Q [ increases.
  • planarization mandates to some extent a decrease in vertical spacing Shallow trench processing, recessed LOCOS processing, and multi- layered interlevel dielectrics can bring about an overall reduction in ve ⁇ ical spacing and therefore an increase m C LS
  • C LL or C L s can reduce the performance ofthe device Integrated circuits which employ narrow interconnect spacings thereby define C LL as a predominant capacitance, and integrated circuits which employ thin interlevel dielectrics define C L s as a predominant capacitance.
  • the problems outlined above are in large part addressed by a dielectric fabrication process that produces a low permittivirv dielectric between the interconnect lines arranged within the same elevation level C'intralevel permittivity ') and between interconnect lines within two separate planes or levels ("interlevel permittivirv"')
  • a patterned laser of conductive material which forms a first interconnect level is formed on a semiconductor substrate
  • a first dielectric is formed on the substrate and the first interconnect level
  • the first dielect ⁇ c preferablv comprises S ⁇ 0 2 formed from a silane or TEOS source in a plasma enhanced chemical vapor deposition chamber at approximately 375° C
  • the first dielect ⁇ c laver is 100 to 1000 angstroms thick
  • a second dielectric laver is then formed upon the first dielectric iayer
  • the permittivity of the second dielectric is lower than the permittivirv of the first dielectric
  • the second dielectric layer is preferablv comprised of a CVD o ⁇ de into which fluorine is inco ⁇ orated
  • the atomic percentage of fluorine incorporated into the second dielectric layer in one embodiment is between 4% and 10% and the thickness ofthe second dielectric layer is preferablv greater than 1000 angstroms
  • a th ⁇ d dielectric preferably a non-fluo ⁇ nated CVD oxide formed from a silane or TEOS source, is then formed upon the second dielect ⁇ c to provide a thermodynamicaily stable capping layer for the second dielectric layer in one embodiment, the third dielect ⁇ c is preferably between 500 to 3500 angstroms in thickness Formation ofthe third dielect ⁇ c layer can be followed by a plana ⁇ zation step preferably achieved with a chemical mechanical polish
  • the dielectric "stack (comprised of the first, second, and third dielectric layers) has a dielect ⁇ c constant that is preterably less than 3 5 (compared to conventional CVD oxides which have dielect ⁇ c constants in the range of 3.8 to 4 5)
  • the dielectric stack is formed in a single deposition step with the fluorine bemg mcorporated in s-itu during an intermediate portion ofthe deposition cycle
  • the third dielectric layer is provided because it is believed that fluorinated oxides may become unstable in air when the percentage of fluorme incorporated mto the film exceeds approximately six to eight percent
  • the present invention contemplates an interlevel dielectric compnsmg a first dielect ⁇ c layer formed on a topography cooperatively defined by a semiconductor substrate and a patterned first interconnect level formed on the semiconductor substrate
  • the first dielectric layer comprises CVD oxide formed from a silane or TEOS source
  • the lower permittivity ofthe second dielectric layer is achieved by inco ⁇ orating fluorine into a CVD oxide in an atomic concentration ot approximately four to ten percent.
  • a third dielectric layer is formed on the second dielectric layer.
  • the present invention further contemplates a method of forming an interlevel dielectric on a substantially planar first set of interconnects that is formed on an upper surface of a semiconductor substrate.
  • a first dielectric layer preferably a CVD oxide, is formed on the topography defined by the first set of interconnects and the semiconductor substrate.
  • a second dielectric layer is then formed on the first dielectric ia>er
  • the dielectric constant ofthe second dielect ⁇ c layer is lower than the dielectric constant of the first dielectric layer
  • the second dielectric layer is preferably an oxide deposited in a CVD chamber using a TEOS or silane source coupled with a fluorinating material to produce an oxide layer having an atomic concentration of fluorine of approximately four to ten percent.
  • a third dielect ⁇ c is then formed on the second dielect ⁇ c layer
  • the present invention still further contemplates a method of forming a interlevel dielectric comprising forming a lower, intermediate, and upper sections in a single CVD process wherein a fluorinating mate ⁇ al. such as SiF 4 , is introduced into the chamber during an intermediate stage ofthe deposition
  • the present invention still further contemplates an interlevel dielectric comprising an oxide formed on a topography cooperatively defined by a semiconductor substrate and a first level interconnect, wherein the oxide comprises lower, intermediate, and upper regions, the intermediate region containing an approximately four to ten percent atomic concentration of fluorine.
  • Fig. 1 is a partial cross-sectional view of a semiconductor substrate upon vvhich a first level of interconnects and an oxide layer have been formed;
  • Fig. 2 is a processing step subsequent to that shown in Fig. 1 in which a second dielectric layer has been formed on the first dielectric layer, the second layer having a lower permittivity than the first dielectric;
  • Fig. 3 is a processing step subsequent to that shown in Fig. 2 in which a third dielectric has been formed on the second dielectric;
  • Fig.4 is a processing step subsequent to that shown in Fig. 3 in which an upper surface ofthe third dielectric has been plana ⁇ zed to produce a substantially planar upper surface;
  • Fig. 5 is a processing step subsequent to that shown in Fig. 4 in which a contact has been formed through the third, second, and first dielectrics to the first interconnect level: and Fig 6 is a processing step subsequent to that shown in Fig 5 in which the contact has been filled with a conductiv e material and a second level of interconnect has been formed on the third dielect ⁇ c
  • Fig 1 shows semiconductor substrate 100.
  • Substrate 100 is tv picallv comprised of a single crvstal silicon water into which transistors and isolation regions are formed through a series ot processing steps well known in the an
  • An upper surface ot substance 100 mav include a dielect ⁇ c for isolating first interconnect level 102 from the underlvmg transistor regions This dielectric typically has a plurality of contact openings for selectively coupling first interconnect level 102 to the transistor regions
  • First level interconnect 102 comp ⁇ ses a pluraiitv of interconnect lines that connect the underlying transistors in a specified manner
  • First interconnect level 102 is typically formed through a physical vapor deposition step using an aluminum target After first inierconncct level 102 is deposited, photoresist is deposited on the first interconnect level 102 and patterned in a photolithography step Individual interconnect lines are then formed in an etch step After formation of first inter
  • Fig 2 shows a processing step subsequent to that shown in Fig 1 in which a second dielectric 106 has been formed on first dielectric 104
  • Second dielectric 106 has a dielectric constant K 2 which is less than the dielect ⁇ c constant K
  • first dielectric 104 is approximately 100 - 1000 angstroms m thickness while second dielectric 106 is approximately 3,000 - 10,000 angstroms thick Like first dielectric 104.
  • second dielectric 106 is preferably formed in a CVD chamber with a TEOS or a silane source To achieve a lower permittivity film however, one embodiment inco ⁇ orates a fluorinating material into the CVD chamber during formation of second dielectric 106
  • the fluorinating material can be S ⁇ F 4 , CF 4 , or C 2 F 6 in various embodiments Inco ⁇ orating fluorme mto second dielectric 106 is believed to result in a lower permittivity dielectric.
  • Second dielectric 106 is controlled such that the atomic concentration of fluorine in second dielectric 106 is preferably between 4% and 10% While inco ⁇ orating higher percentages of fluorme mto second dielectric 106 is believed to result in a lower permittivity film it is also believed that the fluorinated oxide may become thermodynamically unstable at fluorine concentrations greater than approximately 6-8% Accordingly , a first embodiment of second dielectric 106 has a low concentration of fluorine, low concentration being defined as less than 6% The low concentration embodiment might have the advantage of not requiring a third dielect ⁇ c formed on top of the fluorinated film as discussed below In a high concentration embodiment (where high concentration is defined as greater than 6%), second dielectric 106 mav require formation of a passivatmg film on top as disclosed below
  • Fig 3 shows a processing step subsequent to Fig 2 in which third dielectric 108 has been formed on > second dielectric 106
  • Third dielectric 108 is preterably formed m a CVD chamber with a TEOS or silane source, wherein the chamber has been purged of fluorinating material
  • Third dielectric 108 has an upper surface 1 10 which may be plana ⁇ zed using a chemical mechanical polish or a resist etchback process to achieve a substantially planar upper surface 1 10 as shown in Fig 4
  • third dielect ⁇ c 108 provides a thermodvnamicallv stable capping layer for fluorinated oxide 106
  • fluorinated film 106 has a concentration of 0 fluorine below six percent third dielectric 108 mav be optionallv eliminated
  • First dielectric 104, second dielectric 106 and third dielectric 108 can be formed in a single CVD deposition process in which a fluorinating material is introduced into the CVD chamber du ⁇ ng an intermediate stage of the deposition
  • interlevel dielectric 107 is formed compnsmg lower region 107a, j intermediate region 107b, and upper region 107c wherein intermediate region 107b has a fluorine concentration of approximately 4% to 10%
  • a processing step subsequent to that of Fig 4 is shown in which contact via 1 12 has been etched mto third dielectric 108, second dielectric 106 and first dielectric 104 to first interconnect level 102 0
  • the formation of contact via 1 12 is preferably accomplished with a plasma etch process
  • Formation of contact via 1 12 exposes region 1 14 of second dielectric 106
  • Passivatmg film 1 16 can be comprised of S ⁇ 0 2 formed in a CVD chamber void of 5 fluorinating material After formation of contact via 1 12 and the optional formation of passivatmg layer 1 16, contact via 1 12 is filled with a conductive material 1 18 Conductive material 1 18 is commonly formed in a CVD process with a tungsten source After deposition of conductive material 1 18, a mechanical polish can be performed to remove conductive material 1 18 from regions exterior to contact via 1 12 Subsequentlv. a second interconnect level can be formed, preferably from a PVD aluminum, and patterned as shown in Fig 6 0
  • the present invention discloses a novel and useful method of inco ⁇ orating a low permittivity dielectric into an interlevel structure of a semiconductor device
  • the embodiments shown are merely exemplary of a single form of numerous forms Vanous modifications and changes may be made to the configurations shown as would be obvious to a person 5 skilled in the an havmg the benefit of this disclosure It is intended that the following claims be inte ⁇ reted to embrace all such modifications and changes and accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne une structure intercouche à faible permittivité comprenant un diélectrique formé sur la topographie d'un substrat semi-conducteur. Ce diélectrique comporte une région inférieure voisine du substrat semi-conducteur, une région intermédiaire constituée d'un oxyde dans lequel du fluor a été incorporé en une concentration atomique d'approximativement quatre à dix pour cent, et une région supérieure. Un procédé pour former la structure diélectrique consiste à former un premier niveau d'interconnexion sur un substrat. Une première couche diélectrique, de préférence un oxyde formé par dépôt chimique en phase vapeur, est formé sur la topographie définie par le premier niveau d'interconnexion et le substrat. Une deuxième couche diélectrique, présentant une constante diélectrique inférieure à la première couche diélectrique, est ensuite formée sur cette dernière. Une troisième couche diélectrique est formée sur la deuxième couche diélectrique. La deuxième couche diélectrique est de préférence formée dans une chambre de dépôt chimique en phase vapeur à partir d'une source de silane ou de TEOS et d'un matériau de fluoration tel que le SiF4.
PCT/US1996/020485 1996-05-02 1996-12-20 Couches superposees dielectriques a faible permittivite constituees d'oxyde fluore pour couplage capacitif reduit WO1997041592A1 (fr)

Applications Claiming Priority (2)

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US64215496A 1996-05-02 1996-05-02
US08/642,154 1996-05-02

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WO1997041592A1 true WO1997041592A1 (fr) 1997-11-06

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001054190A1 (fr) * 2000-01-19 2001-07-26 Advanced Micro Devices, Inc. Formation dielectrique pour l'obturation de porosite de materiaux graves a faible constante dielectrique
EP1123991A2 (fr) * 2000-02-08 2001-08-16 Asm Japan K.K. Matériaux à faible constante diélectrique et procédés
WO2001071794A1 (fr) * 2000-03-17 2001-09-27 Advanced Micro Devices, Inc. Reparation de film a charpente si-o
US6905981B1 (en) 2000-11-24 2005-06-14 Asm Japan K.K. Low-k dielectric materials and processes

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5334552A (en) * 1991-12-04 1994-08-02 Nec Corporation Method for fabricating a semiconductor device having a multi-layered interconnection structure
US5429995A (en) * 1992-07-17 1995-07-04 Kabushiki Kaisha Toshiba Method of manufacturing silicon oxide film containing fluorine
EP0706216A2 (fr) * 1994-10-03 1996-04-10 Sony Corporation Couche intermédiaire diélectrique pour un dispositif semi-conducteur

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5334552A (en) * 1991-12-04 1994-08-02 Nec Corporation Method for fabricating a semiconductor device having a multi-layered interconnection structure
US5429995A (en) * 1992-07-17 1995-07-04 Kabushiki Kaisha Toshiba Method of manufacturing silicon oxide film containing fluorine
EP0706216A2 (fr) * 1994-10-03 1996-04-10 Sony Corporation Couche intermédiaire diélectrique pour un dispositif semi-conducteur

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IDA J ET AL: "REDUCTION OF WIRING CAPACITANCE WITH NEW LOW DIELECTRIC SIOF INTERLAYER FILM FOR HIGH SPEED/LOW POWER SUB-HALF MICRON CMOS", SYMPOSIUM ON VLSI TECHNOLOGY. DIGEST OF TECHNICAL PAPERS, HONOLULU, JUNE 7 - 9, 1994, no. SYMP. 14, 7 June 1994 (1994-06-07), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 59/60, XP000498582 *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001054190A1 (fr) * 2000-01-19 2001-07-26 Advanced Micro Devices, Inc. Formation dielectrique pour l'obturation de porosite de materiaux graves a faible constante dielectrique
EP1123991A2 (fr) * 2000-02-08 2001-08-16 Asm Japan K.K. Matériaux à faible constante diélectrique et procédés
EP1123991A3 (fr) * 2000-02-08 2002-11-13 Asm Japan K.K. Matériaux à faible constante diélectrique et procédés
US6733830B2 (en) 2000-02-08 2004-05-11 Asm Japan K.K. Processes for depositing low dielectric constant materials
US7144620B2 (en) 2000-02-08 2006-12-05 Asm Japan K.K. Process for depositing low dielectric constant materials
US7544827B2 (en) 2000-02-08 2009-06-09 Asm Japan K.K. Process for depositing low dielectric constant materials
WO2001071794A1 (fr) * 2000-03-17 2001-09-27 Advanced Micro Devices, Inc. Reparation de film a charpente si-o
US6420193B1 (en) 2000-03-17 2002-07-16 Advance Micro Devices, Inc. Repair of film having an SI-O backbone
KR100819188B1 (ko) * 2000-03-17 2008-04-04 어드밴스드 마이크로 디바이시즈, 인코포레이티드 손상된 막을 보수하는 방법 및 반도체 칩을 생산하는 시스템
US6905981B1 (en) 2000-11-24 2005-06-14 Asm Japan K.K. Low-k dielectric materials and processes

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