WO1997040576A1 - Multiplicateur de frequences - Google Patents

Multiplicateur de frequences Download PDF

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Publication number
WO1997040576A1
WO1997040576A1 PCT/US1997/006367 US9706367W WO9740576A1 WO 1997040576 A1 WO1997040576 A1 WO 1997040576A1 US 9706367 W US9706367 W US 9706367W WO 9740576 A1 WO9740576 A1 WO 9740576A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
reference signal
input
frequency
output signal
Prior art date
Application number
PCT/US1997/006367
Other languages
English (en)
Inventor
Charles A. Miller
Original Assignee
Credence Systems Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Credence Systems Corporation filed Critical Credence Systems Corporation
Publication of WO1997040576A1 publication Critical patent/WO1997040576A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2200/00—Indexing scheme relating to details of oscillators covered by H03B
    • H03B2200/006—Functional aspects of oscillators
    • H03B2200/0088—Reduction of noise
    • H03B2200/009—Reduction of phase noise

Definitions

  • the present invention relates in general to frequency multipliers and in particular to a frequency multiplier producing output signals by logically combining taps of a delay locked loop.
  • FIG. 3 illustrates a common prior art frequency multiplier employing a ring oscillator 100 formed by a set of inverters 110 connected end-to-end to form a loop.
  • a signal pulse circulates through ring oscillator 100 with a frequency proportional to the switching speed of inverters 110.
  • a phase comparator 120 receives an input reference signal A and the output B of a counter 130.
  • Counter 130 counts pulses of an oscillator output signal C appearing at the output of one of inverters 110 and pulses its output signal B after every Nth pulse of the inverter output signal C.
  • Phase comparator 120 drives its output signal D high when signal B lags signal A and drives its output signal D low when signal A lags signal B.
  • a loop filter 140 integrates the comparator output signal D to produce a signal E supplying power to inverters 110.
  • the switching speed of inverters 110, and therefore the frequency of signal C increases with the magnitude of signal E.
  • Feedback provided by comparator 120, counter 130 and filter 140 adjusts the magnitude of supply signal E so that the frequency of oscillator output signal C is N times that of the input reference signal A.
  • One problem with this circuit is phase jitter, a second order oscillation in frequency of the oscillator output signal C.
  • a frequency multiplier in accordance with the present invention includes a set of substantially identical inverters connected in series for successively delaying an input periodic reference signal to produce a set of inverter output signals.
  • a phase controller adjusts the delay provided by each inverter so that the output signal of a last inverter of the series is phase locked to a reference signal supplied a ⁇ input to the first inverter of the series.
  • the inverter outputs are evenly distributed in phase with pulse edges evenly dividing the period of the reference signal.
  • a set of XOR gates logically combine selected inverter output signals to produce periodic output signals of frequencies which are even multiples of the reference signal . It is accordingly an object of the invention to provide a frequency multiplier for producing an output signal having a frequency that is a multiple of the frequency of an input reference signal .
  • FIG. 1 is a block diagram illustrating a frequency multiplier in accordance with the present invention
  • FIG. 2 is a timing diagram illustrating operation of the frequency multiplier of FIG. 1;
  • FIG. 3 is a block diagram of a prior art frequency multiplier.
  • Frequency multiplier 10 includes a variable delay line 12 formed by a set of eight identical logic elements (suitably inverters) G1-G8, a phase comparator 14 and a loop filter 16.
  • Inverters G1-G8 are connected in series and produce a set of eight output tap signals T1-T8 progressively shifted in phase from a periodic reference TO supplied as input to the first inverter GI of the series.
  • the amount of delay provided by each inverter stage is determined by a control signal VDLL supplying power to inverters G1-G8.
  • VDLL Since the magnitude of VDLL controls the rate at which a pulse of the TO signal propagates through inverters G1-G8 to the input of phase comparator 14, the VDLL signal controls the amount of phase shift provided by each inverter stage.
  • the TO reference signal and the tap signal output T8 of the last inverter G8 of the series provide inputs to phase comparator 14.
  • the loop filter 16 integrates an output signal COMP produced by phase comparator 14 and supplies its resulting output signal as the control signal
  • Phase comparator 14 drives its output signal COMP high when tap T8 lags the TO reference signal and drives its output signal COMP low when the TO reference signal lags tap T8.
  • Feedback provided by phase comparator 14 and filter 16 adjusts the magnitude of VDLL to phase lock tap T8 to the TO reference signal.
  • the TO reference and T8 tap signals are represented in FIG . 2 by the same waveform because tap signal T8 is phase locked to the TO reference signal.
  • frequency multiplier 10 also includes a set of exclusive OR (XOR) gates X1-X3.
  • XOR gate XI receives the TO reference signal and the T2 output signal a ⁇ its inputs and produces a multiplier output signal Al .
  • the A l output signal has a frequency twice that of TO .
  • XOR gate X2 receives taps Tl and T3 as its inputs and produces a multiplier output signal A2 also having a frequency twice that of TO but shifted in phase from Al by 1/4 cycle.
  • the A l and A2 signals provide inputs to XOR gate X3 producing an output signal A3.
  • output signal A3 Since A2 is 1/4 cycle out of phase with Al, output signal A3 has a frequency twice that of Al and A2 and four times that of the TO signal.
  • frequency multiplier 10 produces output signals of frequency two and four times that of the input reference signal TO.
  • the output signals exhibit little jitter because the feedback provided by comparator 14 and filter 16 tightly couples the tap signals T1-T8 to TO.
  • the frequency multiplier circuit of the present invention could produce frequency multiplied output signals having other than 50% duty cycle when we choose other combinations of tap signals as XOR gate inputs. For example, if we choose taps Tl and T2 as an input to an XOR gate, the output of that XOR gate would also be twice the frequency of the reference signal TO but would have a 25% duty cycle.
  • a frequency multiplier having 16 inverter stages producing sixteen output tap signals T1-T16 and employing seven XOR gates X1-X7 interconnected in a hierarchical manner produces output signals of frequencies 2, 4 and 8 times that of TO. Suitable interconnections for such a multiplier are listed below in Table I.
  • the first line of Table I indicates that XOR gate XI has delay signals TO and T4 as its inputs and would produces an output signal Al of frequency twice that of TO.
  • the last line of Table I indicates XOR gate X7 receives output signals A3 and A4 of XOR gates X5 and X6 and produces an output signal A7 having a frequency eighth times that of TO .
  • a frequency multiplier with a tapped delay line having 2 N inverter stages and a hierarchy of N! suitably interconnected XOR gates can produce a set of output signals having frequencies that are power of two multiples of the input reference signal TO belonging to the set ⁇ 2, 4 ... 2 N_1 ⁇ .
  • inverter stages G1-G8 could be implemented by other types of adjustable delay elements such as buffers or logic gates.
  • the inverter stages and XOR gates may also be implemented by differential logic elements.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

L'invention porte sur un multiplicateur de fréquence comprenant un ensemble d'inverseurs (G1-G8) sensiblement identiques reliés en série retardant avec succès un signal (T0) périodique d'entrée de référence pour produire un ensemble de signaux d'inversion de sortie. Un régulateur de phase (14, 18) ajuste le retard de chacun des inverseurs afin que le signal de sortie du dernier inverseur (T8) de la série soit verrouillé en phase avec un signal de référence fourni comme signal d'entrée au premier inverseur de la série. Les différents signaux de sortie des inverseurs sont ainsi régulièrement distribués en phase, les bords de leurs impulsions divisant régulièrement la période du signal de référence. Un jeu de portes OU exclusif (X1-X3) combine de manière intelligente les signaux de sortie sélectionnés d'inverseurs pour produire des signaux de sortie périodiques de fréquences multiples paires du signal de référence.
PCT/US1997/006367 1996-04-25 1997-04-16 Multiplicateur de frequences WO1997040576A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US63824196A 1996-04-25 1996-04-25
US08/638,241 1996-04-25

Publications (1)

Publication Number Publication Date
WO1997040576A1 true WO1997040576A1 (fr) 1997-10-30

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1997/006367 WO1997040576A1 (fr) 1996-04-25 1997-04-16 Multiplicateur de frequences

Country Status (1)

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WO (1) WO1997040576A1 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2337881A (en) * 1998-05-29 1999-12-01 Hyundai Electronics Ind Clock phase correction circuits
WO1999067882A1 (fr) * 1998-06-22 1999-12-29 Xilinx, Inc. Boucle a retard de phase avec circuit de dephasage du signal d'horloge
EP1345317A2 (fr) * 2002-03-08 2003-09-17 Sirific Wireless Corporation Générateur de signaux d'oscillateur local et son utilisation dans un récepteur à conversion directe
US6784707B2 (en) * 2002-07-10 2004-08-31 The Board Of Trustees Of The University Of Illinois Delay locked loop clock generator
US7038519B1 (en) 2004-04-30 2006-05-02 Xilinx, Inc. Digital clock manager having cascade voltage switch logic clock paths
US7046052B1 (en) 2004-04-30 2006-05-16 Xilinx, Inc. Phase matched clock divider
US7157951B1 (en) 2004-04-30 2007-01-02 Xilinx, Inc. Digital clock manager capacitive trim unit
US7564283B1 (en) 1998-06-22 2009-07-21 Xilinx, Inc. Automatic tap delay calibration for precise digital phase shift

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5120989A (en) * 1991-02-04 1992-06-09 The United States Of America As Represented By The Secretary Of The Army Simplified clock distribution in electronic systems
US5260608A (en) * 1990-02-06 1993-11-09 Bull, S.A. Phase-locked loop and resulting frequency multiplier
US5463337A (en) * 1993-11-30 1995-10-31 At&T Corp. Delay locked loop based clock synthesizer using a dynamically adjustable number of delay elements therein
US5514990A (en) * 1993-12-27 1996-05-07 Kabushiki Kaisha Toshiba Frequency multiplier circuit
US5600273A (en) * 1994-08-18 1997-02-04 Harris Corporation Constant delay logic circuits and methods

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5260608A (en) * 1990-02-06 1993-11-09 Bull, S.A. Phase-locked loop and resulting frequency multiplier
US5120989A (en) * 1991-02-04 1992-06-09 The United States Of America As Represented By The Secretary Of The Army Simplified clock distribution in electronic systems
US5463337A (en) * 1993-11-30 1995-10-31 At&T Corp. Delay locked loop based clock synthesizer using a dynamically adjustable number of delay elements therein
US5514990A (en) * 1993-12-27 1996-05-07 Kabushiki Kaisha Toshiba Frequency multiplier circuit
US5600273A (en) * 1994-08-18 1997-02-04 Harris Corporation Constant delay logic circuits and methods

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6137328A (en) * 1998-05-29 2000-10-24 Hyundai Electronics Industries Co., Ltd. Clock phase correction circuit
GB2337881B (en) * 1998-05-29 2001-09-26 Hyundai Electronics Ind A clock phase correction circuit
GB2337881A (en) * 1998-05-29 1999-12-01 Hyundai Electronics Ind Clock phase correction circuits
US6775342B1 (en) 1998-06-22 2004-08-10 Xilinx, Inc. Digital phase shifter
WO1999067882A1 (fr) * 1998-06-22 1999-12-29 Xilinx, Inc. Boucle a retard de phase avec circuit de dephasage du signal d'horloge
US6289068B1 (en) 1998-06-22 2001-09-11 Xilinx, Inc. Delay lock loop with clock phase shifter
US6587534B2 (en) 1998-06-22 2003-07-01 Xilinx, Inc. Delay lock loop with clock phase shifter
US7564283B1 (en) 1998-06-22 2009-07-21 Xilinx, Inc. Automatic tap delay calibration for precise digital phase shift
EP1345317A2 (fr) * 2002-03-08 2003-09-17 Sirific Wireless Corporation Générateur de signaux d'oscillateur local et son utilisation dans un récepteur à conversion directe
EP1345317A3 (fr) * 2002-03-08 2004-06-16 Sirific Wireless Corporation Générateur de signaux d'oscillateur local et son utilisation dans un récepteur à conversion directe
US6784707B2 (en) * 2002-07-10 2004-08-31 The Board Of Trustees Of The University Of Illinois Delay locked loop clock generator
US7038519B1 (en) 2004-04-30 2006-05-02 Xilinx, Inc. Digital clock manager having cascade voltage switch logic clock paths
US7046052B1 (en) 2004-04-30 2006-05-16 Xilinx, Inc. Phase matched clock divider
US7157951B1 (en) 2004-04-30 2007-01-02 Xilinx, Inc. Digital clock manager capacitive trim unit

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