WO1997036280A1

WO1997036280A1 - Improved performance delta triad color pixel matrix and method of making the matrix

Info

Publication number: WO1997036280A1
Application number: PCT/US1997/004900
Authority: WO
Inventors: Scott H. Holmberg; Edward J. Boling
Original assignee: Image Quest Technologies, Inc.
Priority date: 1996-03-27
Filing date: 1997-03-26
Publication date: 1997-10-02

Abstract

Improved delta triad color pixel active matrix displays, including a first improvement of splitting the offset color subpixels in the delta triad matrix (150, 190). The split subpixel (165) allows the elimination of the offset column lines with straight dual interconnected column lines (156) and addressing the split subpixels in parallel from the dual column lines. The split subpixels and straight dual column lines provide an increased active pixel area and an increased yield by providing for a backup column line. The split subpixels also can be coupled together to allow for crossover or transistor short removal, also increasing the yield of the resulting matrix. A further improvement in liquid crystal display applications is simplification of producing a dual domain configuration with one domain (240, 242) on each split subpixel (194, 196) leading to higher performance when using this dual domain configuration.

Description

IMPROVED PERFORMANCE DELTA TRIAD COLOR PIXEL MATRIX AND METHOD OF MAKING THE MATRIX

TECHNICAL FIELD

The present invention pertains to an improved performance delta triad color pixel matrix and method of making the matrix. More particularly, the present

invention is directed to a method of making a delta triad color pixel matrix with

straight row and column lines to increase the active area and the yield of the matrix devices.

BACKGROUND ART

In recent years there has been growing interest in thin film transistors

(TFT's) and matrix devices incorporating such thin film transistors, such as memory

arrays, all types of integrated circuits and replacements for mechanical switches and relays. For example, reed relays can fatigue and MOS switches exhibit too much leakage current.

A specific exemplary use of the thin film matrix transistor is in flat panel

displays, such as those which employ liquid crystals, electrochromic or electroluminescense, as replacements for conventional cathode ray tubes (CRT's). The flat panel displays promise lighter weight, less bulk and substantially lower power consumption than CRT's. Also, as a consequence of their mode of operation, CRT's nearly always suffer from some distortion. The CRT functions by projecting an electron beam onto a

phosphor-coated screen. The beam will cause the spot on which it is focused to glow with

an intensity proportional to the intensity of the beam. The display is created by the constantly moving beam causing different spots on the screen to glow with different

intensities. Because the electron beam travels a further distance from its stationary source to the edge of the screen than it does to the middle, the beam strikes various points on the

screen at different angles with resulting variation in spot size and shape (i.e. distortion). Flat panel displays are inherently free of such distortion, because each pixel is photolithographically patterned on the substrate as opposed to being defined by where

the CRT electron beam strikes the phosphor on the screen. In the manufacture of the flat

panel displays the circuit elements are deposited and patterned, generally by photolithography, on a substrate, such as glass. The elements are deposited and etched in

stages to build a device having a matrix of peφendicular rows and columns of circuit control lines with a pixel contact and control element between the control line rows and columns. The pixel contact has a medium thereon which is a substance that either glows (emissive) or modulates the transmission of ambient light (non-emissive) when a threshold

voltage is applied across the medium control element. The medium can be a liquid crystal,

electroluminescent or electrochromic materials such as zinc sulfide, a gas plasma of, for example, neon and argon, a dichroic dye, or such other appropriate material or device as will luminesce or otherwise change optical properties in response to the application of

voltage thereto. Light is generated or other optical changes occur in the medium in

response to the proper voltage applied thereto. The optically active medium on each contact is generally referred to as a picture element or "pixel".

The circuitry for a flat panel display is generally designed such that data is generally shifted in on all the column lines each to a predetermined voltage. One row is

then energized to turn on all the transistors in that row (one row is written at a time). That row is then shut off and the data for the next row is shifted into 11 the column lines and then the second row is energized and written. This process is repeated until all the rows

have been addressed. All the rows are generally written in one frame period, typically

about l/60th of a second or about 16.7 ms. Then voltages representing the data are supplied selectively to particular columns to cause selected pixels to light up or change

optical properties as the row is written. The pixels can be made to change intensity by applying a large voltage or current or a longer pulse of voltage or current. Utilizing liquid crystal display (LCD's) with twisted nematic active material, the display is substantially

transparent when not activated and becomes light absorbing when activated or vice versa

depending upon polarizer orientation. Thus, the image is created on the display by sequentially activating the pixels, row by row across the display matrix. The geometric distortion described above with respect to CRT's is not a factor in flat panel displays since

each pixel location is photolithographically determined and fixed.

One of the major problems that arises with respect to the prior art method of manufacturing structures for active matrix displays (e.g. those employing thin film transistors at each pixel) is that they generally suffer production yield problems similar to

those of integrated circuits. That is, the yields of devices produced are generally not 100%

and the yield (percentage of devices with no defects) can be 0% in a worst case. High quality displays will not tolerate any defective transistors or other components. Also, larger size displays are generally more desirable than smaller size displays. Thus, a manufacturer is faced with the dilemma of preferring to manufacture larger size and/or higher resolution displays, but having to discard the entire product if more than a few

transistors and hence if more than a few pixels are defective. In other words, the manufacturer suffers a radically increased manufacturing cost per unit resulting from

decreasing usable product yield. Color images can be generated in active matrix displays by forming a color

pixel which includes forming a subpattern of differently colored subpixels, typically red,

green and blue, and activating them appropriately. With an LCD color pixels can be

formed by filtering the external light source into these three colors with patterned filter materials. Different patterns of red, green and blue filters can be formed depending on the requirements of the display. Typically arrangements of the color filters are three vertical

or horizontal side-by-side stripes, three diagonal color stripes which form an L-shaped color pixel, four square or rectangular color subpixels (one color is repeated or white cells are used for the fourth subpixel) or offset diagonal stripes known as a delta triad. The delta triad arrangement is often a preferred method to obtain a high quality color image on

a liquid crystal display. The fabrication of a delta triad color pixel configuration requires twice as many row lines and one and one half as many column lines as a non-color display with the same number of pixels. It is also necessary to position color subpixels in adjacent rows with an offset along the column lines.

Another major problem with color LCD displays in particular arises when

the delta triad configuration is utilized. The offset of the color subpixels from one row to the next makes the efficient design of pixels very difficult. The column lines in this

configuration are required to be staggered. Such a stagger of the column lines reduces the

active pixel area and hence reduces the light transmitted by the display. A brighter

external light source then must be utilized, which increases the power consumption of the

resulting display system.

One of the major drawbacks to the use of a twisted nematic liquid crystal

cell is the existence of one poor viewing direction due to the fixed orientation or alignment

of the liquid crystal molecules with respect to the display, polarizer, and analyzer. This

poor viewing direction is characterized by low contrast and poor image quality. The direction of this poor viewing angle can be set during the manufacture of the liquid crystal

display, but can not be changed during operation. One method to reduce or eliminate the

appearance of this poor viewing angle is to fabricate the liquid crystal display with several

different regions of orientation or alignment in different portions of the display. In this

manner there is never a poor viewing direction for the entire display. If these different

regions of the display are very close and very uniform in response, the image will appear

much more uniform in the previously poor viewing directions. When two different such

orientations are used on one display, the configuration is known as a dual domain cell.

The use of a dual domain liquid crystal configuration is not without it's own

problems. The major difficulty is to provide a uniform response for the two different

domains. The prior art typically causes one pixel cell to be divided and processed into two or more regions that are not identical. The result is a compromise of the viewing angle

performance and the persistence of a poor viewing angle to some degree.

These problems of decreased yield, reduced transmission and dual domain

performance are dramatically improved in d e present invention by providing a method of manufacturing delta triad color pixel matrix displays with an increased yield, increased transmission and improved domain matching.

DISCLOSURE OF INVENTION

There is provided improved methods of making delta triad color pixel matrix displays. A first improvement is accomplished by splitting the offset color subpixels in the

delta triad matrix. This split allows the elimination of the offset column lines with dual interconnected column lines and addressing the split subpixels in parallel from the dual column lines. The elimination of the offset provides for an increased active pixel area and an increased yield by providing for a backup column line. The split subpixels also can be coupled together to allow for crossover or transistor short removal, also increasing the

yield of the resulting matrix. A further improvement in liquid crystal display applications is simplification of producing a dual domain configuration on the split subpixel leading to higher performance when using this dual domain configuration.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a plan view schematic representation of one regular active matrix

display of a prior application;

FIG. 2 is a cross-section of one embodiment of an inverted gate transistor of the

prior application;

FIG. 3 is a second cross-section of the transistor embodiment of FIG. 2;

FIG. 4 is a plan view schematic representation of a prior art delta triad color

pixel matrix;

FIG. 5 is a plan view schematic representation of one embodiment of a delta triad color pixel matrix of the present invention;

FIG. 6 is a plan view schematic representation of a preferred embodiment of a delta triad color pixel matrix of the present invention;

FIG. 7 is a plan view of a prior art dual domain pixel; and FIGS. 8 A and 8B are plan views of dual domain pixel embodiments of the

present invention.

BEST MODES FOR CARRYING OUT THE INVENTION

As before mentioned, numerous devices can be formed utilizing thin film transistors (TFT's), one particular utilization is in active matrix liquid crystal displays

(AMLCD 's) and the present invention will be described as a portion of an AMLCD.

Referring to FIG. 1, a schematic representation of an AMLCD which can incoφorate the present invention is designated generally by the reference numeral 10.

The AMLCD 10 is illustrated including a set of optional outer shorting bars 12, 14, 16 and 18, which are more fully described in copending application Serial No.

08/497,372, entitled ACTIVE MATRIX ESD PROTECTION AND TESTING SCHEME, filed July 31, 1995 and incoφorated herein by reference. The outer shorting bars 12, 14,

16 and 18 are removed during processing by breaking them away along a scribe line 20, as more fully described in Serial No. 08/497,372.

The AMLCD 10 also is illustrated including a set of inner shorter bars 22, 24,

26 and 28. The inner shorting bars 22, 24, 26, and 28 also are utilized during processing, as more fully described in Serial No. 08/497,372. However, the inner shorting bars 22,

24, 26 and 28 preferably only are electronically disconnected from the AMLCD 10 along

a line 30, but remain a physical part of the AMLCD 10.

The AMLCD 10 is deposited on a substrate 32, commonly formed from a glass

panel, which is broken away along the scribe line 20. The substrate 32 also can be formed

from other types of insulating materials, including a metallic panel with an insulative coating. The AMLCD 10 is formed with a plurality of row lines 34 and a plurality of

column lines 36 foπning a large matrix, only a small portion of which is illustrated. The

row lines 34 include one of a plurality of driver contact pads 38 connected to each line 34

and the column lines 36 also include one of a plurality of driver contact pads 40 connected

to each line 36.

The AMLCD 10 includes a plurality of identical pixels formed between the row

lines 34 and the column lines 36, therefor only one pixel 42 will be described in detail.

At each matrix crossover point 44, where a row line 34 and a column line 36 cross, a TFT

46 is formed to connect both lines to a pixel contact 48. The active liquid crystal medium

is deposited at least over the contact 48, which medium will change properties in response

to the combined voltage or current at the crossover point 44. The medium on the pixel 42

will generally appear as a square, rectangle or dot in the overall matrix of the AMLCD 10.

The actual size of the transistor 46 and the contact 48 are not drawn to scale, but are

shown schematically for illustration only.

It should be noted that there is no theoretical limit on the number of row lines

34 and column lines 36 that can be employed or on the outside dimension of an AMLCD

10. The processing equipment provides a practical limit on the outside dimension, which

limit is continually changing as the equipment is improved.

The problem encountered with manufacturing AMLCD' s is that if the AMLCD

10 contains defective TFT's or other circuit elements causing one or more pixels to be inoperative, the display generally must be discarded. One optional technique of masking

defective pixels 42, is to employ an additional transistor 49 with the pixel 42 coupling the pixel 42 to an adjacent row Rl . Then, when row Rl is written the data is applied not only to the previous pixel 42', but also through the transistor 49 into the pixel 42. When row R2 then is written the data for the pixel 42 is written over the data from the previous pixel

through the transistor 46. If, however, the transistor 46 is defective, the pixel 42 will not show as inoperative, but instead will retain the data from the previous row Rl . This masks

the fact that the pixel 42 is not operating correctly.

As another option, the pixel 42 also can include a storage capacitor 50 coupled to the row Rl which maintains and stabilizes the voltage written into the pixel 42 during

each frame.

The TFT 46 and the AMLCD 10 are formed to enhance the yield of active

pixels. One preferable structure for the TFT 46 and manufacturing thereof will be described with reference to FIGS. 2 and 3. The TFT 46 is fully described in copending application Serial No. 08/497,371, entitled IMPROVED PERFORMANCE MATRIX

TFT, METHOD OF MAKING AND MATRIX DISPLAYS INCORPORATING THE

TFT, filed July 31, 1995 and incoφorated herein by reference. The TFT 46 is formed as an inverted gate TFT with a gate 52 being deposited first as the row line 34. The completed TFT 46 is illustrated in FIGS. 2 and 3, while the various process steps are best

illustrated and described in Serial No. 08/497,371. Although the various layer thicknesses are not critical to the TFT 46, preferable thicknesses and materials are described to form

a preferred embodiment of the TFT 46 and the AMLCD 10.

The gate 52 preferably is formed of two layers of metal, a first layer of

aluminum, preferably an aluminum/copper alloy, is deposited and patterned to form a line

element 54. To form a redundant row line 34, a second gate layer of tantalum is deposited

over the aluminum element 54 and patterned to form a line element 56 which covers the

element 54 . The element 56 also has fingers 58 which form the actual gates for the

individual TFT's 46. The line element 54 preferably is formed from aluminum or an

aluminum alloy. Aluminum is utilized for long lines because of its high conductivity, but

is not critical for small displays and can be eliminated from small displays if desired. The

aluminum is deposited to about 1200 Angstroms to provide conductivity, but still be thin

enough to prevent step coverage problems over the element 54. The tantalum element 56

or other anodic refractory metal preferably is deposited separately for redundancy to about

2000 Angstroms. The fingers 58 which form the gates for the TFT 46 do not require the

aluminum layer and typically are formed only of tantalum.

A first gate insulator layer 60 is then formed by anodizing the exposed the

tantalum element 56, which is hard anodized to form the insulator layer 60 from tantalum

oxide, Ta₂O₅. A hard anodization can be performed by utilizing a solution of 0.1 to 4.0

percent citric acid in deionized water. A voltage of about sixty (60) volts can be utilized

which will form a very precise and uniform oxide layer 60 to about fifteen (15) Angstroms per volt or about a thickness of 900 Angstroms. The pads 38 and 40 can be covered with photo resist to prevent anodization of the pads or can be anodized and then later etched.

Alternatively, the first gate insulator 60 can be formed by a deposited dielectric

layer. A second or redundant gate insulator 62 then is deposited, preferably silicon nitride, Si₃N₄, to a thickness of about 3000 Angstroms. Two additional layers sequentially are deposited, a layer of amoφhous silicon 64 and then a layer of N+ doped amoφhous

silicon 66. The N+ layer 66 and amoφhous silicon layer 64 selectively are etched to leave discrete areas 70 over the gate portions 58 on the nitride layer 62. The amoφhous silicon layer 64 is deposited to a thickness of about 1500 Angstroms and the N+ layer 66

is deposited to a thickness of about 300 Angstroms. After patterning the remaining N +

layer forms the ohmic contact portions 68.

A reanodization can be performed before the next metal layer is deposited to

prevent potential shorts, especially at any point that the drain or source metal overlies the gate metal. The reanodization is performed at a voltage at least twice the maximum voltage normally present between the source and gate lines. The reanodization will form a new oxide in the tantalum or underlying aluminum layer to prevent a later deposited

metal from shorting to the gate line through a pinhole which exposed the gate metal. A source-drain (S-D) layer 72 then is deposited, preferably formed from a

plurality of metal layers for large displays. For small displays, the layer 72 can be a single metal layer, such as aluminum or molybdenum. A preferable large device multilayer 72 is formed by depositing a first barrier layer of molybdenum to a thickness on the order of

500 Angstroms. A second conductivity enhancing layer of aluminum or aluminum alloy

then is deposited to a thickness of about 5000 Angstroms. A third barrier layer of molybdenum or molybdenum alloy then is deposited to a thickness of about 300 Angstroms. Alternatively, only the first two layers are required to be deposited.

The S-D layer 72 then is patterned to form a source portion 74, a drain portion

76 and a top capacitor contact portion 78. A transistor channel region 80 then is formed between the source and drain portions 74 and 76 by removing the N+ doped layer between the contact portions 68; which remain under the S-D metal portions 74 and 76. At this

point the transistor 46 is electrically functional. The storage capacitor 50 also now is electrically functional and is formed by the contact portion 78 and the underlying portions

of the nitride layer 62, the oxide layer 60 and the gate 52. Both the transistor 46 and the capacitor 50 can now be electrically tested, as desired.

A first passivation layer 82 then is deposited, preferably formed of Si₃N₄ to a thickness of about 7000 Angstroms. This dielectric layer also could be formed from

deposited SiO₂, spin on glass (SOG) or other organic dielectric materials. The layer 82

is patterned to form a drain contact opening 84 and a capacitor contact opening 86. When a redundant column line is to be formed, vias 88 are formed to provide contacts to the underlying column line 36.

A pixel ITO layer 90 then is deposited and patterned to form the drain contact at the opening 84, the capacitor contact at the opening 86, the redundant column line by contacting through the vias 88 (where applicable) and the pixel 48. The pixel 48 is not shown to scale and the section is offset to include both the transistor 46 and the

capacitor structure 50, which are staggered from one another. The section does not fully illustrate the electrical separation between the column ITO and the pixel ITO 48 (see FIG. 1). The additional transistor 49 (FIG. 1) is not illustrated, but can be formed in the same manner as the transistor structure 46.

The TFT structure 46, then is completed by forming a final passivation layer 92. The passivation layer 92 is formed to a thickness of about 2000-3000 Angstroms in the

same manner as the layer 82. The layer 92 could also be formed on the color filter substrate or can be formed on both. If the AMLCD 10 is to be utilized as a color active matrix display, thin color filters are formed to cover the individual color subpixel contacts 48 in the desired format.

The conventional utilized colors are red (R), blue (B) and green (G). Referring to FIG.

1 a stripe format could be formed by utilizing a repeating group of color subpixels of R, B and G, for example the respective contact subpixels 100, 102, 104; 106, 108, and 110; and 112, 114 and 116. In the stripe format, the subpixels 100, 106 and 112 form a R - 17 - column or stripe, the subpixels 102, 108 and 114 form a B column or stripe and the

subpixels 104, 110 and 116 form a G column or stripe. The color pixels also could be

orientated as horizontal color stripes or diagonal stripes. Another type of format is an L-

shaped color pixel. In the L-shaped color pixel, the subpixel 100 would be B, the subpixel

102 would be R and the subpixel 106 would be G. The second L-shaped pixel would

include the subpixel 104 G, the subpixel 108 B and the subpixel 110 R.

The stripe format can be utilized for alpha-numeric displays, the L-shaped

format can be utilized for low quality delta pixel simulation, but for high specialty (non-

alphanumeric) televisional type displays, a true delta triad color pixel matrix is required.

One prior art delta triad color pixel matrix 120 is illustrated in FIG. 4.

A plurality of row lines 122 are formed in a conventional manner and include

contact pads 124. A plurality of column lines 126 also are formed including contact pads

128. The column lines 126 are functionally the same as the column lines 36 in the

AMLCD 10, however the column lines 126, include portions 126' which are offset

horizontally due to the offset delta triad format.

A first color delta triad pixel 130 is formed by three color subpixels, a R

subpixel 132, a G subpixel 134 and a B subpixel 136. A second adjacent color delta triad pixel 140 is inverted and again formed by three color subpixels, a B subpixel 142, a R subpixel 144 and a G subpixel 146. The subpixels are coupled to the row and column control lines 122 and 126 by a control element preferably a TFT 148, such as the TFT 46.

The delta triad color pixel matrix 120 provides the optimum color image quality

for non-alphanumeric display, but offers a lower than desired yield and aperture ratio. The low yield and low aperture ratio are caused by the offset column line portions 126' . The offset portion 126' is required because of the offset of the subpixels from one another, such

as the subpixel 136 from the subpixels 132 and 134. This offset results in a region

adjacent the offset portion 126' and adjacent each crossover point 149 where the column line 126' is parallel with the row line 122. It is undesirable to place large areas of the row line 122 on top of the column line portion 126' , because a large capacitance would be produced. Thus the two lines must be laterally separated, which reduces the available active pixel area. Further, since it is undesirable to place the subpixel contacts on top of the column line portions 126', the subpixels must be further reduced in size. The reduction in subpixel area reduces the

performance of the matrix 120. In particular, in the case of a liquid crystal material as the optically active pixel material, the transmission of the external light source through the

panel will be reduced. The apparent brightness of the display panel will be reduced, or

it will be necessary to increase the brightness of the external light source. - 19 - Referring now to FIG. 5, a plan view schematic representation of a first delta

triad color pixel matrix embodiment 150 of the present invention is illustrated. The matrix 150 includes a plurality of row lines 152 and row contact pads 154. In an effort to increase the yield and aperture ratio of the delta triad devices, applicants discovered that

each of the color subpixels could be split and straight dual column lines 156 then could be

utilized. The dual column line 156 includes a contact pad 158 and a first line 160 connected to a second parallel line 162 by at least one connector 164. Preferably a plurality of connectors 164 are formed along the length of the dual column line 156.

A delta triad color pixel 165 now includes a pair of R subpixel contacts 166, 168

and a pair of G subpixel contacts 170, 172 and a pair of B subpixels contacts 174, 176. The R contacts 166, 168 are coupled to the row lines by separate TFT's 178 and 180. The TFT 178 couples the R contact 166 to the row line 152 and the column line 160, while the

TFT 180 couples the second R contact 168 to the row line 152 and the parallel column line 162. In a like manner, the G contacts 170, 172 are coupled to a second set of dual column lines 160' and 162' by respective TFT's 182 and 184. To provide the delta pixel offset,

the B contacts 174 and 176 are also coupled to the second set of column lines 160' and

162' by respective TFT's 186 and 188, but on the opposite sides of the lines 160' and 162' from the contacts 170 and 172.

Referring now to FIG. 6, a plan view schematic representation of a preferred delta triad color pixel matrix embodiment 190 of the present invention is illustrated. The preferred delta triad color pixel matrices 190 is very similar to the first matrix embodiment

150 and the same column and line numbers are utilized. However, the embodiment 150

will require one extra column line due to the subpixel offset inside of the first dual column

line 156. In contrast, the matrix 190 offsets the subpixels outside of the first dual column line 156 and hence eliminates the extra column line.

The matrix 190 again includes a plurality of row lines 152 and row contact pads

154. Each of the color subpixels again are split and straight dual column lines 156 are

A delta triad color pixel 192 includes a pair of R subpixel contacts 194, 196 and a pair of G subpixel contacts 198, 200 and a pair of B subpixels contacts 202, 204. The

R contacts 194, 196 are coupled to the row lines by separate TFT's 206 and 208. The

TFT 206 couples the R contact 194 to the row line 152 and the column line 160, while the

TFT 208 couples the second R contact 196 to the row line 152 and the parallel column line 162. In a like manner, the G contacts 198, 200 are coupled to a second set of dual column

lines 160' and 162' by respective TFT's 210 and 212. To provide the delta pixel offset,

the B contacts 202 and 204 are also coupled to the first set of column lines 160 and 162

by respective TFT's 214 and 216, but on the opposite sides of the lines 160 and 162 from

the contacts 194 and 196. The addition of the additional transistors and column lines still provides an

increase in the resulting device aperture ratio. The split contacts with the additional

column line and TFT also provide a spare or redundant aspect to the delta triad color

pixels 165 and 192. The offset column line 126' of the prior art and the area consumed by the line and required spacing are eliminated. Also, the connectors 164 can be made

very small in width, applied only periodically, or applied only at the top and bottom of the

active matrix array 150. In addition, because of the multiple electrical paths formed by

the dual column lines 160 and 162, these lines can also be reduced in width. The result

is a color pixel triad matrix configuration which has a higher yield and better performance

than the prior art.

The dual column line and the split color subpixels also have particular utility in

a dual domain matrix configuration. As previously described in the background, it is

sometimes desired to produce a twisted nematic liquid crystal matrix utilizing a dual

domain configuration. The domain refers to the orientation of the liquid crystal molecules

with respect to the solid surfaces of the liquid crystal device. Referring now in particular

to FIG. 7, a plan view schematic representation of an active matrix twisted nematic dual

domain liquid crystal prior art pixel 220 is illustrated.

The pixel 220 is one color subpixel of a color display matrix. A row line 222

and a column line 224 are coupled to a pixel contact 226 by a TFT 228. The contact 226

is split or divided into a pair of regions or domains 230, 232. The first domain 230 has liquid crystal molecules which align in the direction of a first arrow 234. The second

domain 232 has the liquid crystal molecules aligned in the direction of a second arrow 236. These alignments or orientations typically will be 180 degrees apart. The conventional

method is to rub the surface of the thin dielectric layer on top of the contact areas 230 and

232, separately in the direction of the arrows 234 and 236. The domain shape can be of variations configurations. The two domains 230 and 232 are separated by a domain wall 238, which wall 238 generally causes an undesirable optical appearance. Again, conventionally the wall 238 is optically covered, such as by an opaque material.

There are a number of difficulties in fabricating the dual domain pixel 220. One difficulty is obtaining uniform optical behavior from the two domains 230, 232. Because of the TFT 228, the process to produce the two domains 230, 232 can be somewhat

different. The presence of the domain wall 238, which must be covered, also is a problem

since it reduces the aperture ratio of the resulting device.

Referring now to FIG. 8 A, a dual domain configuration is applied to a color subpixel of the present invention, for example the R color subpixel. The R subpixel

includes the two split pixel contacts 194,196 coupled by the separate TFTs 206 and 208 to the connected parallel column lines 160, 162. The two different domains are applied

to the two different contacts 194, 196 orientated as shown by arrows 240, 242. The two

domains 194, 196 are structurally similar and are separated by the column line 160. This results in a better optical separation and match between the two domains. The domain wall will be substantially coexistent with the column line 160, which already is optically

covered. Therefore, there is no additional loss in the transmission/aperture ratio.

Optionally, the two domain contacts 194 and 196 can both be coupled to the

column line 160 by the TFT 206 and a TFT 244, as illustrated in HG. 8B. This configuration can have some processing advantage in forming the dual domain pixel.

One problem encountered by the prior art method of manufacturing delta triad

color pixel matrices is that if the devices contain any defective pixel transistors or other circuit elements experience a failure, a pixel can become inoperative. In addition, some defects, such as an interruption in the continuity of a row line or a column line, or an electrical connection of a row line and a column line, will cause a line of pixel defects to

appear. In either event, if the defects are excessive, the device must be repaired or discarded.

A repair process utilizing a laser beam to remove excess conductive electrode material is possible. The removal of excess material from the row line, column line,

transistor or pixel contact is straightforward, and is accomplished by heating and vaporizing excess material with a focused spot of laser energy as small as 2 micrometers in diameter. The replacement of missing conductive material is much more difficult. There are processes which can deposit conductors by means of ion beams in a vacuum system or local decomposition of chemical compounds with a laser beam. These processes

require complex, expensive equipment and sometimes do not produce reliable repairs. It would be desirable to have a process to replace missing conductive material which does not rely on the deposition of conductors. Several such methods now exist. One method involves the driving of the row line or column line from both ends of the row

line or column line of the device instead of from one side only. This has the advantage of

allowing one interruption to appear in row line or column line without the complete interruption of signal. It has the disadvantage of requiring an additional set of drive control circuits for each row line or column line. In addition, an interruption in the row line or column line may still produce a visible defect or discontinuity in the display image

since the signal paths are different for the two now separate sections of line. Another metiiod of replacing missing conductive material is to use an alternative

path which connects the two ends of the interrupted line together and allows one drive control circuit to drive both ends of the line. A disadvantage of this method is that it cannot practically be fabricated for all the row line and column lines at the time of initial

manufacture of the flat panel display. In practice a limited number of lines are available

around the periphery which can be connected if needed. The connection process requires the production of a short circuit between two layers which are normally insulated by a dielectric layer. This short circuit can be produced by a similar process to that used for removal of excess material. The disadvantage of this process is that it is still more difficult

and less reliable than the removal of excess material.

What is required is a process or method which is very unlikely to produce interruptions in the row lines and column lines, even when excess material is removed.

The present invention provides such a method.

Referring again to FIG. 8A, the R subpixel includes the additional column line 162 connected in parallel with the dual column line 160 by the connector 164. This

structure forms a second subpixel element 196 which presents the same signal to the

optically active material as the pixel contact 194 through the switching element 206. In

this embodiment, the interconnected lines formed by the column line 160, column line 162 and connection line 164 are very difficult to interrupt electrically, since there are two

parallel electrical paths. A single defect cannot cause an open in the combined dual

column lines 160 and 162. In addition, a single crossover defect occurring in one of the

connectors 164 generally can be repaired by removing one or more sections of column line

160 or column line 162 by a laser process. This repair process will not create an

interrupted column line 160 or column line 162, since there is a second electrical path

formed by in the interconnected column line 160, column line 162, and connection line

164. Therefore, a defect caused by an interruption of column line 160 or column line 162

will not cause a visible defect, and a defect caused by a connection between column line

160 or column line 162 and row line 152 can be repaired completely without the need to

deposit conductive material. A significant improvement in yield can be expected on panels even without the repair process because of the insensitivity of the column line 160 and

column line 162 to interruption. In addition, a significant improvement of the yield of the repair process can be expected since there is no need for a process to deposit conductive material .

Another defect which can occur in manufacturing the delta color pixel triad displays, is a short in a TFT such as the TFT 206 or 208. A short between the column and

the row line results in a bright spot on the display, which is a particularly undesirable effect. As before stated, a shorted TFT or crossover for example the TFT 206, can be isolated by cutting one of the column lines 160 adjacent to the short and one of the adjacent

connectors 164, if required. This however still results in a partial defect, since the contact

166 now is inoperative. A further defect connector 246 can be utilized to mask this type of defect. The connector 246 is connected between the contacts 194 and 196. Thus, if one of the contacts has a short and it's TFT is cut off, the contact will still be activated through

the connector 246. The R subpixel will not operate as efficiently, however, the defect will

be substantially masked.

Referring again to FIG. 8B, this configuration as mentioned can have advantages in processing uniform devices over the configuration of FIG. 8A. In particular, the

configuration of FIG. 8B is less sensitive to misalignment of processed layers than that of FIG. 8A, especially if the connector 246 is utilized. Referring now to FIG. 5, it can be

seen that a subpixel in the first row such as the split pair of contacts 166 and 168 will be

affected differently by shift in patterns to the right or left than will a subpixel in the second

row such as the split pair of contacts 174 and 176. If the subpixel configuration of FIG. 8B is utilized in the pixel array of FIG. 5, the subpixels in each row are affected the same

by a shift in patterns to the right or left.

Many modifications and variations of the present invention are possible in light

of the above teachings. Although, the delta triad color pixel matrix of the present

invention is described utilizing an inverted gate TFT, any non-linear control device can be

utilized, such as a thin film diode, MIM or TFT. Further, the configuration can be utilized

in other non-thin-film structures. It is therefore to be understood that within the scope of

the appended claims, the invention may be practiced otherwise than as specifically

described.

Claims

CLAΪMSWhat is claimed is:

1. A method of manufacturing improved active delta triad displays,

including a plurality of color pixels each having a red, a blue, and a green subpixel, characterized by: dividing each color subpixel into two separate but substantially identical

contacts; forming a plurality of row lines and a plurality of dual column lines, each dual column line having a first and a second spaced parallel connected line; a first color subpixel, a first contact coupled by a first control device to

a first row line and a first dual column line and a second contact coupled by a second control device to said first row line and said first dual column line; a second color subpixel having a first contact coupled by a first control

device to said first row line and a second adjacent dual column line, a second contact

coupled by a second control device to said first row line and said second dual column line;

and a third color subpixel having a first contact coupled by a first control

device to a second adjacent row line and said second dual column line opposite said first contact of said second subpixel and a second contact of said third color subpixel coupled

by a second control device to said second row line and said second dual column line

opposite said second contact of said second subpixel.

2. The method as defined in claim 1 including electrically connecting each

of said subpixel divided contacts.

3. The method as defined in claim 1 including forming a dual domain on

each of said color subpixels, including forming a first domain on one of said separate

contacts and forming a second domain on the second one of said contacts.

4. The method as defined in claim 1 including said first and second contacts

of each of said color subpixels coupled to the same line of said dual column lines.

5. The method as defined in claim 1 including said first and second contacts

of each of said color subpixels coupled to different lines of said dual column lines.

6. The method as defined in claim 1 including interconnecting each of said

first and second dual column lines in a plurality of locations along the length of said

column lines.

7. The method as defined in claim 1 including foirning each of said control

devices as a thin film transistor.

8. An improved active delta triad display, including a plurality of color pixels each having a red, a blue, and a green subpixel, characterized by:

each color subpixel divided into two separate but substantially identical

contacts;

a plurality of row lines and a plurality of dual column lines, each dual

column line having a first and a second spaced parallel connected line;

a first color subpixel, a first contact coupled by a first control device to

a first row line and a first dual column line and a second contact coupled by a second

control device to said first row line and said first dual column line;

a second color subpixel having a first contact coupled by a first control

device to said first row line and a second adjacent dual column line, a second contact coupled by a second control device to said first row line and said second dual column line;

and

a third color subpixel having a first contact coupled by a first control

opposite said second contact of said second subpixel.

9. The display as defined in claim 8 including each of said subpixel divided

contacts electrically connected.

10. The display as defined in claim 8 including a dual domain formed on

each of said color subpixels, including a first domain on one of said separate contacts and a second domain on the second one of said contacts.

11. The display as defined in claim 8 including said first and second contacts

12. The display as defmed in claim 8 including said first and second contacts of each of said color subpixels coupled to different lines of said dual column lines .

13. The display as defined in claim 8 including each of said first and second

dual column lines interconnected in a plurality of locations along the length of said column

lines.

14. The display as defined in claim 8 including each of said control devices being a thin film transistor.

15. A method of manufacturing improved active delta triad displays, including a plurality of color pixels each having a red, a blue, and a green subpixel, characterized by: dividing each color subpixel into two separate but substantially identical

contacts; forming a plurality of row lines and a plurality of dual column lines, each dual column line having a first and a second spaced parallel connected line;

a first color subpixel, a first contact coupled by a first control device to a first row line and a first dual column line and a second contact coupled by a second control device to said first row line and said first dual column line;

a second color subpixel having a first contact coupled by a first control

and a third color subpixel having a first contact coupled by a first control

device to a second adjacent row line and said first dual column line opposite said first contact of said first subpixel and a second contact of said third color subpixel coupled by a second control device to said second row line and said first dual column line opposite

said second contact of said first subpixel.

16. The method as defined in claim 15 including electrically connecting each

of said subpixel divided contacts.

17. The method as defined in claim 15 including forming a dual domain on each of said color subpixels, including forming a first domain on one of said separate

contacts and forming a second domain on the second one of said contacts.

18. The method as defined in claim 15 including said first and second

contacts of each of said color subpixels coupled to the same line of said dual column lines.

19. The method as defined in claim 15 including said first and second

contacts of each of said color subpixels coupled to different lines of said dual column lines.

20. The method as defined in claim 15 including interconnecting each of said

column lines.

21. The method as defined in claim 15 including forming each of said control

devices as a thin film transistor.

22. An improved active delta triad display, including a plurality of color

pixels each having a red, a blue, and a green subpixel, characterized by:

each color subpixel divided into two separate but substantially identical

contacts;

a plurality of row lines and a plurality of dual column lines, each dual

column line having a first and a second spaced parallel connected line;

a first color subpixel, a first contact coupled by a first control device to

control device to said first row line and said first dual column line;

a second color subpixel having a first contact coupled by a first control

and a third color subpixel having a first contact coupled by a first control device to a second adjacent row line and said first dual column line opposite said first

contact of said first subpixel and a second contact of said third color subpixel coupled by

a second control device to said second row line and said first dual column line opposite

said second contact of said first subpixel.

23. The display as defined in claim 22 including each of said subpixel divided contacts electrically connected.

24. The display as defmed in claim 22 including a dual domain formed on

25. The display as defmed in claim 22 including said first and second

26. The display as defined in claim 22 including said first and second

27. The display as defined in claim 22 including each of said first and second

lines.

28. The display as defined in claim 22 including each of said control devices being a thin film transistor.