WO1997036245A1

WO1997036245A1 - Serial interface module and method

Info

Publication number: WO1997036245A1
Application number: PCT/US1997/005025
Authority: WO
Inventors: Alan Hendrickson
Original assignee: Advanced Micro Devices, Inc.
Priority date: 1996-03-25
Filing date: 1997-03-25
Publication date: 1997-10-02

Abstract

A serial communication system including a serial communication port structure for starting and stopping an internal clock. This internal clock is designed, in operation, to generate a clock output signal to be transmitted to a device external to the system in which the serial communication port is incorporated. By emitting a clock output pulse train of predetermined length, the serial communication port can effectively control the passage of time as sensed by the external device. The location of data boundaries relative to the clock phase is programmable such that the data boundaries coincide with active clock edges.

Description

SERIAL INTERFACE MODULE AND METHOD Background of the Invention

The present invention relates to systems for communicating between microcontrollers and other devices and, more particularly, to systems implementing a serial interface for communicating between an on-chip microcontroller and external devices

Both serial and parallel interfaces are well known to those skilled in the art Serial interfaces involve time-sequential processing of the individual parts as a whole, such as the bits of a character, the characters of a word, and so on, using the same facilities for successive parts. Parallel interfaces, on the other hand, involve the simultaneous processing of the individual parts of a whole, using separate facilities for the various parts.

The present invention relates to serial interfaces such as those that can allow an on-chip microcontroller to talk to a number of industry standard external devices, such as serial electrically erasable/programmable read-only memories (EEPROM's). Traditionally, such interfaces have been formed relying heavily upon software to control the ports of the microcontroller. Some efforts have been made to construct serial interfaces with dedicated hardware; however, these efforts have not produced a simple, low-cost, and flexible alternative to software-intensive serial interfaces. Furthermore, the prior art is capable of locating transmit output boundaries, or reception input boundaries, only on negative-going clock edges, but not on positive-going clock edges. Thus, prior art serial interfaces have been incompatible with some external devices.

Based upon the foregoing, it is clear that it has been a shortcoming and deficiency ofthe prior art that no one has developed a simple, low-cost, and flexible interface module for an integrated circuit (IC), which interface is made primarily of hardware, and which interface allows serial communication between on-chip microcontrollers and receptive external devices. Summary of the Invention

To overcome the shortcoming and deficiency of the prior art mentioned above, the present invention provides a method and apparatus for serial communication, including a serial communication port structure for starting and stopping an internal clock. This internal clock is designed, in operation, to generate a clock output signal to be transmitted to a device external to the system in which the serial communication port is incorporated. The location of data boundaries relative to the clock phase are programmed so that the data boundaries coincide with active, either positive or negative, clock edges.

Therefore, the present invention includes a serial input/output port for a microcontroller, which serial input/output port is operable to send data and clock signals to an external device. The serial input/output port includes means for determining a select number of data bits to send to the external device, means for producing only enough clock pulses to send the determined select number of data bits, means for beginning production of clock pulses to send the determined select number of data bits, means for stopping production of clock pulses immediately upon production of only enough clock pulses to send the determined select number of data bits, and means for programming the location of data boundaries relative to the clock phase so that the data boundaries coincide with active clock edges.

In another feature of the present invention, a simple, low-cost, and flexible serial port can interface with a wide variety of external devices.

Another object of the present invention is to provide an interface module for an IC made primarily of hardware and which allows serial communication between on-chip microcontrollers and receptive external devices.

Brief Description of the Drawings

Fig. la is a block diagram of a serial interface according to the teachings of the present invention;

Fig. lb is a timing diagram describing the operation of the serial interface of

Figs. 2a and 2b are a block diagram of an integrated circuit including the serial interface of Fig. la; Fig. 3 is a block diagram of a cordless telephone terminal unit into which the integrated circuit of Fig. 2 is incorporated; and

Fig 4 is a block diagram of a cordless telephone base station into which the integrated circuit of Fig. 2 is incorporated

Fig 5 is a block diagram of a Mode Register, also known as SIOMODE. that may be employed in embodiments of the present invention,

Fig. 6 is a block diagram of a Transmit Buffer Register that may be employed in embodiments of the present invention;

Fig. 7 is a block diagram of a Receive Buffer Register that may be employed in embodiments of the present invention;

Fig. 8 is a block diagram of an Transmit Length Register that may be employed in embodiments of the present invention;

Fig. 9 is a block diagram of an Status Register that may be employed in embodiments of the present invention;

Fig. 10 is a block diagram of a Interrupt Mask Register that may be employed in embodiments of the present invention;

Fig. 11 is a block diagram of a Interrupt Source Register that may be employed in embodiments of the present invention; and

Fig. 12 is a block diagram of a Clock Speed Register that may be employed in embodiments of the present invention.

Description of the Preferred Embodiments

Referring now to Fig. la, the serial port interface module 12 is a combination of four serial channels designed to provide communication with frequency synthesizers (such as the Fujitsu MB1501 Frequency Synthesizer), an LCD controller (such as the NEC mιcroPD7225 LCD Controller), and an EEPROM (such as a S-2914AR/1 EEPROM). A common set of transmit, receive, and clock logic is used to support the synthesizer, LCD, and EEPROM. Hereinafter, this combined set of hardware is referred to as the serial I/O or SIO interface.

Before describing the SIO hardware used to implement the various requirements placed upon it, the operational requirements placed upon the SIO interface by the various external devices it is required to communicate with will be discussed. These operational requirements arise based upon the synthesizer interface, the LCD interface, and the EEPROM interface.

With respect to the synthesizer or LCD interface, communication between the IC and the synthesizer or LCD chip is unidirectional, from the IC to the synthesizer or LCD. Two interface signals, serial data output, also known as SDOUT, and shift clock, also known as SCLK, are required. In actual operation, data is transmitted most significant bit ("MSB") first, on the rising or falling edge, the "active ^" edge, of the clock, as determined by the programming of a particular bit For the SCLK signal a 50% duty cycle clock can be used. This allows programmable speed, e.g., 288 kbps, 144 kbps, 72 kbps, and 36 kbps. In actual operation, the clock is active only when data is being sent, and is held inactive, either high or low, as determined by two control bits, the rest of the time that the module is enabled.

The EEPROM interface is bidirectional, and is compatible with 8- and 16-bit devices that (1) are receptive to incoming data that changes on the active edge of the clock, or (2) cause their output data to change on the active edge of the clock. Three interface pms, an SDOUT, a serial data input, also known as SDIN, and a SCLK, are supported. Data is transmitted MSB first, on the active edge of the clock. The word length is from one to eight bits long. Words longer than eight bits can be transmitted in two or more increments. For example, an eleven bit word can be transmitted as one byte followed by three bits, a seven-bit and a four-bit word, or even eleven one-bit words. The SDIN pin is for serial data input, of eight or sixteen bit words, MSB first.

With respect to the SCLK pm, data is transmitted synchronously to the active edge of a 50% duty cycle clock. When multiple byte words are transmitted, the clock output is held high between transmission of parts of the same word. Data is received from the EEPROM on the active edge of this same clock. Clock speed is programmable, with 288 kbps, 144 kbps, 72 kbps, and 36 kbps being possible selections For write operations, the clock is active only when data is being transmitted. It is held inactive when stopped For read operations, the clock continues to run after the transmit part of the sequence until either eight or sixteen eight or sixteen bits are received-as specified in the Mode Register, discussed further below.

The serial port interface module 12 includes a transmit buffer shift register 13, an EEPROM receive buffer 14, a clock generator and mode select register 15, and a programmable length counter 16.

The transmit buffer shift register 13 is loaded by software with data, the data being from one to eight bits in length. The number of bits actually loaded corresponds to the number of bits programmed in the Transmit Length Register. Data is transmitted MSB first with data bus bit seven loading the MSB of the shift register. When fewer than eight bits are loaded, software locates the bits to be transmitted in the least significant bit positions of the shift register. Transmission begins when the buffer is written if a reception is not in progress, otherwise transmission starts automatically after the read operation is completed.

Software loads data into the buffer only when transmission is not in progress. No error indication is generated if the microcontroller attempts to write to the buffer during transmission. Data is shifted out of the buffer on the active edge of the shift clock. The output pin is held inactive when the SIO interface is enabled and data is not being transmitted.

A status bit is set in the Status Register whenever the transmit shift register is empty. The status bit is cleared when there is data in the shift register. A maskable interrupt is generated whenever this bit is set. Under normal conditions, the software will enable the interrupt only when data has been loaded into the shift register 13. This causes an interrupt to be generated as soon as the last bit has left the shift register, at the end of the last bit time, indicating that a new word can be loaded.

The receive buffer 14 is a single-byte double-buffered register, where data is shifted serially into one half of the buffer pair, and is then automatically transferred into the second half if it is empty. This allows for a double buffer in the case of 8-bit wide EEPROMs, and single buffering when 16-bit wide EEPROMs are used. Data is read from the second half of the buffer pair, also known as the Receive Buffer Register, by the microcontroller.

- o A status bit is set in the Status. Register whenever there is at least one byte of data in the buffer. The bit is cleared when the register is empty. A maskable interrupt is generated whenever the bit is set.

The SIO clock generator 15 produces the correct clock output for each of the modes of operation. The master input clock to the SIO clock generator 15 comes from the clock generator module 40 (see Fig. 2a). The data rate is programmed in the Clock Speed Register located in the clock generator module 40. Possible data rates include 288 kHz, 144 kHz, 72 kHz, and 36 kHz. The input clock, also known as the SIO clock, is present only when the serial port is enabled, and is held low when the serial port module is disabled.

Two outputs from the SIO clock generator 15 are CLOCK REF and CLOCK INVERT, which are inputs to an exclusive-OR gate 17, which serves as a means for programming the location of data boundaries relative to the clock phase such that the data boundaries coincide with active clock edges. The CLOCK INVERT signal also alters, or inverts, the inactive clock level that is defined in bit three, and the receive clock edge which is defined in bit two, of Fig. 5.

The SCLK output is gated off, low, in the disabled state in order to protect external circuitry supplied by an alternate power source. The alternate power source may be powered down during telephone idle operation, to conserve battery power. When active, the output wave form and number of cycles is dependent on the mode of the serial port, as discussed immediately below.

The output of the exclusive-OR gate 17 is an input to an AND gate 18. Thus, regarding the transmit mode, the SCLK pin 19 has a signal on it which follows either the CLOCK REF signal or an inverted version of it when enabled. The CLOCK REF signal is generated by the transmit length counter such that only the desired number of clock pulses are produced for each word to be transmitted. When multiple byte words are transmitted, the clock output is held inactive between transmission of parts of the same word. Transmission starts when the transmit buffer is written if a reception is not in progress.

With regard to the receive mode, the clock output is the same as in the transmit mode except that if the read/write bit in the Mode Register is sampled as "read" at the completion of the transmit operation, the clock output is left running until the programmed number of bits has been shifted in.

The transmit buffer shift register 13 contains a transmit length counter, which orders the transmission in sections of from one to eight bits at a time The number of bits in a section is programmed into the Transmit Length Register prior to loading the transmit buffer The Transmit Length Register does not need to be reprogrammed if successive sections have the same length.

Regarding the received word length counter, received words can be eight or sixteen bits in length. The desired length is programmed by software into the Mode Register.

Based upon what has been said above, it should be clear that software specifies the various interface formats in the Mode Register. It should also be clear that the received word length, i.e., eight or sixteen bits, and the edge on which that data is received are also programmed in this register.

Referring to Fig. lb, data bits T_m, T_m _, etc., T_ and T₀ are serially transmitted on a single wire, SDOUT, which is the serial data output line. The index m has a value ranging from zero to seven, and is controlled by the Transmit Length Register. The Transmit Buffer Register determines the values of the data

The output of the clock generator may take one of many permutations, as shown by the SCLK waveforms in Fig. lb. Software configures these control bits to best accommodate the interface specification of the device to which the chip is connected. SCLK waveforms numbers one through four describe the clock output when the port is used only as an output (Mode Register bit number zero is zero). Mode Register bits number three and four control the inactive clock state and the clock edge on which the data bits change. The first SDIN waveform depicted m Fig lb indicates that the receive data, SDIN, is irrelevant in the output-only mode

SCLK waveforms numbers five through eight depict clock waveforms typical of specifications for serial EEPROM devices in which the latency between application of the last of the address bits in the T₀ bit location, and the availability of data corresponding to the applied address (i.e. the lookup time from the end of T₀ to the center of the first output bit from the EEPROM device) is one bit time For these waveforms, the sampling points in the serial port receiver, identified by arrows in Fig. lb. are located in the center of the expected receive data periods. The receive data bit timing is shown as the second SDIN waveform.

SCLK waveforms numbers nine through twelve depict clock waveforms typical of specifications for serial EEPROM devices m which the latency is one-half bit, or any integer plus one-half bit, with sampling instants located at the center of the expected receive data bit periods. Each pair of SCLK timing waveforms (1,2), (3,4), (5,6), (7,8), (9,10), and (11,12) demonstrate the waveform with the apphcation of the control bit Mode Register bit number four, the effect of which is to logically invert the clock signal to accommodate a greater variety of interface specifications. The receive data bit timing is shown as the third SDIN waveform.

Referring back to Fig. la, the serial port interface module 12 further includes an SDOUT pin 20 and a SDIN pin 21. The SDOUT pin 20 is for the data output of the serial port interface module 12. Data is transmitted MSB first, on the active edge of the clock. When the module is disabled, or when the IC is in reset, the SDOUT pin 20 is held low. The SDIN pin 21 is for data input for the serial port interface module 12. Data is programmably clocked in on the active edge of the clock. The SCLK pin 19 is for clock output. The clock is a gated clock that produces the correct number of transitions for the programmed operation. Thus, it is not free running. When the module is disabled, or when the IC is in reset, the SCLK pm 19 is held low.

The serial port interface module 12 contains seven user visible registers. These registers include the Mode Register 15, the Transmit Buffer Register, the Receive Buffer Register 14, the Transmit Length Register 13, as well as a Status Register, an Interrupt Mask Register, and an Interrupt Source Register.

Referring now to Fig. 2, because the integrated circuit shown in Fig. 2 is discussed at length in a case related hereto, and which has been incorporated by reference herein, the various elements shown in Fig. 2 will not be discussed in detail. The digital cordless telephone baseband transceiver depicted in Fig. 3 provides control and signal processing to conduct a radio telecommunication link for voice applications. Referring now to Fig.2a, in the part of the transceiver depicted by the block 22, labeled PLL. Burst Timing, and Frame Formatter, the transceiver performs transmission and reception of serial voice data between the radio and the CODEC, the function of which is to convert between digitized voice and analog voice. The serial port interface module 12 interfaces with the programmable synthesizer 42 in the radio, which selects the radio frequency of transmission and reception. The serial port interface module 12 also interfaces with an LCD driver module 44, which reports information to the user, such as call progress and dialing numbers. The serial port interface module 12 also interfaces with a serial EEPROM 46, which may contain data such as speed dialing numbers or identification numbers that are used with a cordless telephone.

Fig. 2b depicts other elements of the transceiver, including a microcontroller 28 for controlling the operations of the transceiver, a keypad scanner 30 for receiving user input, including dialing information, a watchdog timer 32 for recovery from software or hardware errors, and several output ports for various control functions.

Referring now to Figs. 3 and 4, the IC shown in Fig. 2 plays a prominent role in both the terminal and base station portions of the cordless telephone depicted. The various input and output signals to the serial port interface module 12 with external elements to the IC within the cordless telephone.

Now, by way of example only, set forth below are details regarding the various user visible registers of the present invention. The Mode Register 15, the Transmit Buffer Register, the Receive Buffer Register 14, the Transmit Length Register 13, as well as a Status Register, an Interrupt Mask Register, an Interrupt Source Register, and a Clock Speed Register are each discussed below and depicted in Figs. 5-12, respectively.

Mode Register

Address: FF30

Size: 4 bits

Default: XXXX0000

Access Mode: Read/write

Set by: Software

Cleared by: Software, reset

This register specifies for operating modes of the serial port interface module Note that the SIO enable is an input to the serial port interface module 12. This register is depicted in Fig. 5.

BITS 7-5 Reserved-Write operations must write zeros. Reads return an indeterminate value. A read-modify-write operation can write back the read value.

BIT 4 Clock Invert -- This bit when set inverts the clock signal 10 defined by

BIT 3 Clock Level Select-Used to select the state of the clock pin when the SIO port is enabled and the clock is inactive. When the bit is set, the clock is held low. When the bit is cleared, the clock is held high. This facility adds flexibility insofar as it facilitates working with different parts.

BIT 2 Receive Clock Edge Selection -- When set, the data is received on the rising edge of the SCLK signal. When cleared, the data is received on the falling edge of the SCLK signal.

Bit 1 Receive Length Selection- When set, 8-bit words are received.

When cleared, 16-bit words are received.

Bit 0 Read/Write Selection-This bit is sampled at the end of every transmit operation. If it is set, the hardware will keep the clock running for reception of a data word. If it is cleared the clock will be stopped without producing pulses for reception. Note that data can be transmitted with this bit in either state.

Transmit Buffer Register

Address: FF31 Size: 8 bits Default: Don't care Access mode: Write Set by: Software Cleared by: N.A.

The Transmit Buffer Register is depicted in Fig. 6.

BITS 7-0 Transmit Data-Data written into this register is transmitted MSB first (register bit 7 corresponds to bit 7 on the data bus). When a word length of less than 8 bits is programmed in the Transmit Length Register, the bits to be transmitted must be loaded into the least significant bit positions of this register.

Receive Buffer Register

Address FF32 Size: 8 bits Default: Don't care Access mode: Read Set by: Hardware Cleared by: Software read The Receive Buffer Register is depicted in Fig. 7.

Transmit Length Register

Address FF33

Size 3 bits

Default XXXXXOOO

Access mode: Read/write

Set by: Software

Cleared by: Software, reset

This register, depicted in Fig. 8, specifies the length of the transmit word.

BITS 7-3 Reserved-Write operations must write zeros. Reads return an indeterminate value. A read-modify-write operation can write back the read value.

BITS 2-0 Word Length-Software writes these bits with a code to specify the length of the word to be transmitted. If multiple words of the same length are to be transmitted, software does not need to re-write this register.

BITS 210 WORD LENGTH

000 8

001 1

010 2

011 3

100 4

101 5

110 6

111 7

Status Register Address - FF37

Size. 2 bits

Default 00 hex

Access mode: Read

Set by. Hardware

Cleared by: Hardware, reset

This register, depicted in Fig. 9, contains status bits for the SIO interfaces

BITS 7-2 Reserved-Reads return zeros for this revision of the IC Future revisions of the IC could implement a function that would result in one or more of these bits being read as a one. Software should be written to take this into account. BIT 1 Transmit Buffer Empty-This bit is set whenever the transmit buffer is empty. It is cleared when data is present in the buffer. BIT 0 Receive Data Available-This bit is set when there is a full byte of data in the user accessible portion of the SIO double buffered receive data register. The bit is cleared when the user accessible portion of the buffer is empty and there is not a complete byte in the shift register portion of the buffer to be passed to the user accessible portion.

Interrupt Mask Register

Address: FF38

Size: 2 bits

Default: XXXXXX00

Access mode: Read/write

Set by: Software

Cleared by: Software, reset

This register, depicted m Fig. 10, contains interrupt enable bits corresponding to the bits in the Status Register. BITS 7-2 Reserved-Wπte operations must write zeros Reads return an indeterminate value. A read-modify-write operation can write back the read value. BIT 1 Transmit Buffer Empty-When set, this interrupt is enabled. When cleared, the interrupt is masked. BIT 0 Receive Data Available-When set, this interrupt is enabled When cleared, the interrupt is masked.

Interrupt Source Register

Address: FF39

Size: 2 bits

Default: 00 hex

Access mode: Read

Set by: Hardware

Cleared by: Hardware, reset

This register, depicted m Fig. 11, reports the source of SIO interrupt requests to the microcontroller. The descriptions of the bits assumes that the interrupts are not masked.

BITS 7-2 Reserved-Reads return zeros for this revision of the IC. Future revisions of the IC could implement a function that would result in one or more of these bits being read as a one. Software should be written to take this into account. BIT 1 Transmit Buffer Empty-This bit is set whenever the transmit buffer becomes empty. It is cleared when data is loaded into the buffer. Software should only enable this interrupt once data has been loaded into the shift register and there is another byte of data to transmit. BIT 0 Receive Data Available-This bit is set when a byte of data is transferred mto the user accessible portion of the double buffered receive data register. The bit is cleared when the user accessible portion of the buffer becomes empty and there is not a complete byte in the shift register-portion of the buffer to be passed to the user accessible portion.

Clock Speed Register

Address FFED

Default XXXXXXOO

Access mode: Read/write

Set by: Software

Cleared by: Software, reset

This register, depicted in Fig. 12, specifies the frequency of the clock signal when active.

BITS 7-2 Reserved-Write operations must write zeros. Reads return an indeterminate value. A read-modify-write operation can write back the read value.

BITS 1-0 Clock Speed -- These bits control the frequency of the emitted SCLK signal.

BITS SCLK 10 Clock Rate, kHz

00 36

01 72

10 144

11 288

Those skilled in the art should now fully understand and appreciate the structure, operation, and advantages of the present invention. In essence, the present invention provides a serial communication system including a serial communication port structure for startmg and stopping an internal clock. The internal clock is designed, in operation, to generate a clock output signal to be transmitted to a device external to the system in which the serial communication port is incorporated. By emitting a clock output pulse train of predetermined length, the serial communication port can effectively control the passage of time as sensed by the external device. Therefore, the present invention provides a simple, low-cost, and flexible serial interface, made primarily of hardware.

Obviously, numerous modifications and variations are possible in view of the teachings above. Accordingly, within the scope of the appended claims, the present invention may be practiced otherwise than as specifically described hereinabove.

Although illustrative embodiments of the invention have been shown and described, a wide range of modification, change, and substitution is contemplated in the foregoing disclosure and in some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.

Claims

Claims:W at is claimed is:

1. A serial input/output port for a microcontroller, the serial input/output port operable to send data and clock signals to an external device, the serial input/output port comprising: a. means for determining a select number of data bits to send to the external device; b. means for producing only enough clock pulses to send the determined select number of data bits; c. means for beginning production of clock pulses to send the determined select number of data bits; d. means for stopping production of clock pulses immediately upon production of only enough clock pulses to send the determined select number of data bits; and e. means for programming the location of data boundaries relative to the clock phase such that the data boundaries coincide with active clock edges.

2. A serial input/output port as recited in claim 1, wherein the means for determining a select number of data bits to send to the external device comprises a transmit length counter.

3. A serial input/output port module for a microcontroller, the serial input/output port operable to send data and clock signals to an external device, the serial input/output port module comprising: a. an internal clock; b. means for starting the internal clock; c. means for transmitting a predetermined number of data bits to the external device while the clock is running; d. means for stopping the internal clock immediately upon completion of transmission of the predetermined number of bits: and e. means for programming the location of data boundaries relative to the clock phase such that the data boundaries coincide with active clock edges.

4. A serial input/output port module as recited in claim 3, wherein the internal clock generates a clock signal during operation, and wherein the serial input/output module further compns.es means for transmitting the clock signal to the external device.

5. A serial input/output port module as recited in claim 4, wherein the means for transmitting a predetermined number of data bits to the external device while the clock is running comprises a transmit length counter and a clock divider.

6. A serial input/output port module as recited in claim 5, wherein the transmit length counter generates a control signal, wherein the clock divider generates a clock output signal, and wherein the means for transmitting a predetermined number of data bits to the external device while the clock is running further comprises means for ANDing the clock output signal with the control signal.

7. A method for transmitting data from a microcontroller to an external device over a serial input/output port, the method comprising the steps of: a. sending a predetermined amount of the data simultaneously with a clock signal to the external device; b. determining whether to stop the clock signal high or low, and c. stopping the clock signal high or low immediately upon transmission of the last of the predetermined amount of data; wherein the location of data boundaries relative to the clock phase are programmable such that the data boundaries coincide with active clock edges.

8. A method as recited in claim 7, further comprising the step of determining whether to stop the clock signal high or low, and wherein the step of stopping the clock signal comprises the step of stopping the clock signal high or low, as determined during the step of determining, immediately upon transmission of the last of the predetermined amount of data.

9. A method as recited in claim 7, further comprising the step of counting the data to determine when the predetermined amount is transmitted, this step of counting producing a control signal.

10. A method as recited in claim 9, further comprising the step of generating a clock output signal.

11. A serial input/output port for a microcontroller, the serial input/output port operable to receive data from an external device, the serial input/output port comprising: a. means for determining a select number of data bits to receive from the external device; b. means for producing only enough clock pulses to receive the determined select number of data bits; c. means for beginning production of clock pulses to receive the determined select number of data bits; d. means for stopping production of clock pulses immediately upon production of only enough clock pulses to receive the determined select number of data bits; and e. means for programming the location of data boundaries relative to the clock phase such that the data boundaries coincide with active clock edges.

12. A serial input/output port as recited in claim 11, wherein the means for determining a select number of data bits to receive from the external device comprises a receive word length counter.

13. A serial input/output port for a microcontroller, the serial input/output port operable to send data and clock signals to an external device, and the serial input/output port also operable to receive data from an external device, the serial input/output port comprising: a. means for determining a select number of data bits to send to the external device; b. means for producing only enough clock pulses to send the determined select number of data bits; c. means for beginning production of clock pulses to send the determined select number of data bits; d. means for stopping production of clock pulses immediately upon production of only enough clock pulses to send the determined select number of data bits; e. means for determining a select number of data bits to receive from the external device; f. means for producing only enough clock pulses to receive the determined select number of data bits; g. means for beginning production of clock pulses to receive the determined select number of data bits; h. means for stopping production of clock pulses immediately upon production of only enough clock pulses to receive the determined select number of data bits; and i. means for programming the location of data boundaries relative to the clock phase such that the data boundaries coincide with active clock edges.

14. A serial input/output port as recited in claim 13, further comprising means for determining whether to stop clock pulses high or low.

15. A serial input/output port as recited in claim 14, wherein the means for determining whether to stop clock pulses high or low comprises a bit in a serial port mode register.