Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/40—Bus structure
  • G06F13/4004—Coupling between buses
  • G06F13/4027—Coupling between buses using bus bridges
  • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
  • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses

Definitions

• This invention relates to a data transfer assembly comprising two busses, (from now referred to as the primary and secondary bus) for electronic, digital data signals adapted to a predetermined standard, e.g. a PCI local bus, at least two electronic memory devices of any known type connected to said primary bus for storing and down-loading of the electronic data, and to said secondary bus for trans ⁇ mitting the downloaded data.
• a predetermined standard e.g. a PCI local bus
• VMEbus which is a standard used for interconnecting diffe ⁇ rent types of apparatus, e.g. for data acquisition and pro ⁇ cessing.
• the different electronic devices are built as modules adapted to specific physical and electrical require- ments, and communicating with each other using the VME bus. Thus the different modules may be bought from different vendors, and still work together.
• Each module in this system may in its turn comprise modules according to another standard, the PMC (PCI Mezzanine Cards) .
• PCI (Peripheral Component Interconnect) local bus is a data bus provided by Intel ® also comprising protocols for communication between different components in a system.
• the PCI local bus has a peak bandwidth of 132 Mbytes/second. It is also meant to provide "Plug & Play" operation for add-in boards.
• a main object to this invention is to provide a system for handling data in applications with high bandwidth requirements, using a PCI local bus. Examples of such app ⁇ lications may be transmitting signals received from a camera to be stored on one or more disks, or digitized data from a A/D (analog to digital) converter to a filtering device.
• A/D analog to digital
• a suggested solution in a data acquisition system has been the use of two memories being loaded and emptied of data in an alternating fashion, by loading one of the memories while at the same time unloading the other and switching at convenient intervals, and thus making a so called “swinging buffer".
• This has the advantage of allowing varying data transfer rates, as well as giving room for data processing on continuous streams of data.
• Known systems using this technique comprises a first I/O module receiving data and transmitting these data to a first memory. When the first memory module has been filled the data passing the I/O module is transmitted to the second memory module, and at the same time the data in the first memory is transmitted to a second I/O module which may for ⁇ ward the data e.g. to a processor.
• VME bus and/or VSB VME Sub-system Bus
• an assembly characterized that it also comprises at least two control devices, e.g. a i960 ® RP processor from Intel ® , adap- ted to said standard, each said control device having three ports of which the first port is connected to a block of memory devices for alternately loading and unloading of data to and from said memory block, the second and third ports are connected to said primary bus and secondary bus and are capable of communication with said primary bus and secondary bus using said standard, each control device being capable of loading data received from the primary bus, and transmitting downloaded data to the secondary bus, the said second and third port in each of the said control devices comprising communication bridge, e.g.
• the predetermined standard is PCI local bus or equivalents and the assembly comprises a first and a second control device, each having a third port connected to a memory device, said primary port of the first control device being connected to said primary bus and said secondary port being connected to the secondary bus, said primary port of the second control device being connected to said secondary bus and said secondary port being connected to the primary bus.
• This embodiment provides a symmetric circuit for equally good communication both ways through the assembly.
• Figure 1 is a diagram showing the structure according to the present invention.
• Figure 2 is a diagram showing an application example; a data recorder with multiple SCSI disks.
• Figure 3 is a diagram showing a second application example; a data acquisition system with DSP.
• Figure 1 gives a schematic view of the invention, having two blocks of memory devices 3 each coupled to a third port on a control device 4,5.
• the block of memory devices may be built from any available random access memory device such as DRAM and SRAM. Typical memory sizes for each of the two memory blocks starts at 4MB, with an upper limit defined by the available technology, currently 1GB.
• the control devices 4,5 comprise three ports, one being connected to the memory block 3 and the other two 4P,4S,5P,5S being connected to the primary 1 and secondary 2 busses, respectively.
• the control devices are adapted to loading and unloading the memory block with data to and from devices 6,7 connected to the primary and secondary busses, to and from the memory block connected to the third port of each control device.
• the control devices 4,5 also each comprises a bridge between the second and third ports providing communication between the two ports 4P,4S,5P,5S as well as a possibility to process the data, and to synchronize and control the data flow.
• the communication bridges each comprise a primary 4P,5P and a secondary 4S,5S port.
• control devices 4,5 may preferrably also comprise a micro-processor core, memory controller, means of address translation, messaging unit, DMA controllers and other peripheral interfaces.
• the control devices 4,5 may also comprise means for communication with each other using the PCI local bus, in order to co-ordinate the loading and unloading of data from the memory devices 3 and optimize the data transfer through the assembly. In this way the control devices may choose to switch from loading to unloading and vice versa before the memory devices are full or empty, depending on the data and control signals transmitted from other circuits 6,7 in the system in which the invention is used.
• the other circuits 6,7 connected to the busses may be using a data bus of any suitable kind.
• the data bus will, however, preferably be a PCI local bus or a related standard for communication between different electronic circuits.
• the interfaces are adapted for transmitting signals to and from the circuit according to the invention.
• Figure 2 and 3 present diagrams of configurations in which the invention may be used.
• Figure 2 shows a system where digital data is received from a camera 8 and is transferred to one of the memo blocks 3 by one PMC module 6, using the primary PCI b 1.
• Multiple SCSI controller PMC modules 7a,7b,7c connecte* to the secondary PCI bus moves the data from the memory to multiple SCSI disks 9a,9b,9c.
• SCSI is a widely used standard for storage devices such as hard disks.
• An assembly according to the invention 3,4,5 is used to control the flow of data to the disks 9a-9c.
• the example in figure 3 shows a data acquisition system where analog data from e.g.
• a sonar is digitized in an external A/D converter 12, and fed into one memory block 3 through a parallel input PMC module 6 connected to the primary bus 1, using the PCI bus protocol.
• a PMC module 7 with a DSP performs an initial filtering of the data which is transmitted to a main DSP engine 11.
• the A/D converter 12, the card comprising the assembly according to the invention and the main DSP engine 11 may all be connected to a VME bus, which typically is used for communication between the data acquisition system and a host processor also connected to the VMEbus.
• - Storage controller (chips and modules) for e.g. SCSI.

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• Engineering & Computer Science (AREA)
• General Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Information Transfer Systems (AREA)
• Bus Control (AREA)

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Cited By (3)

Citations (3)

• 1996
  • 1996-03-28 NO NO961248A patent/NO961248D0/no unknown
• 1997
  • 1997-01-10 DE DE19781663T patent/DE19781663T1/de not_active Withdrawn
  • 1997-01-10 AU AU23111/97A patent/AU2311197A/en not_active Abandoned
  • 1997-01-10 WO PCT/NO1997/000007 patent/WO1997036244A1/en active Application Filing

Patent Citations (3)

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