WO1997033226A1

WO1997033226A1 - Programmable controller

Info

Publication number: WO1997033226A1
Application number: PCT/JP1996/000534
Authority: WO
Inventors: Futoshi Nakai
Original assignee: Matsushita Electric Works, Ltd.
Priority date: 1996-03-06
Filing date: 1996-03-06
Publication date: 1997-09-12

Abstract

Before starting the first execution scanning, a CPU (10) compiles the source codes of a user program on a RAM (12) into codes which are executable at a high speed in an address space for compilation by executing a program for compilation on a ROM (11). After the compilation, the CPU (10) performs input-output I/O refreshing operation, and then sets '1' in a device selecting register (13). When the CPU (10) accesses a specific address space, an address decoding circuit (14) selects the RAM (12) instead of the ROM (11) and the address space for compilation of the RAM (12) is mapped instead of the specific address space. The CPU (10) performs arithmetic processing by executing codes in the address space for compilation of the RAM (12). Therefore, the executing codes of a large-volume user program can be stored in the RAM (12) and the codes can be executed.

Description

Specification

Programmable controller

Technical field

The present invention relates to a programmable controller. Technology

Conventionally, a programmable controller that compiles and executes a user program into an execution code such as a machine code capable of calculating at a high speed is used as shown in FIG. The address decode circuit is configured so that ROM1 for the system program and RAM2 for the system work user and the program storage RAM during system execution are fixedly arranged in the address space X ドレス accessible to the CPU. Was. Disclosure of the invention

With the above configuration, the capacity of ROM1 and RAM2 could not be expanded beyond address space X accessible by the CPU used. Therefore, a programmable controller with a larger capacity user program could not be created.

There is a CPU that can have an address space that can be accessed as data separately from the address space that stores the executable code that can be executed by the CPU. Must be allocated to the address space of the RAM that stores the executable code that can be executed by the CPU, and the address space that is occupied by the ROM that stores the system program can be executed by the CPU. Since the space subtracted from the address space for storing the code is only released to the user program, It was not possible to use a user program with a large capacity, or to use a ROM that stored a system program with a large capacity.

The present invention has been made in view of the above problems, and has as its object to use a large-capacity user program that can effectively use an address space in which a CPU can access an execution code. To provide a programmable controller capable of

In order to achieve the above object, according to the invention of claim 1, a CPU, a ROM storing a fixed program such as a system program, an address space or a source code storing a source code of a user program are provided. A RAM in which an address space for compiling an address is set and an address decoding means for selecting another memory device from the current memory device when the specific address space is accessed by setting from the CPU. In addition, the CPU allocates an address space in which the CPU can read and execute the execution code to the ROM, and a part of the address space as a specific address space which is also allocated to the RAM by selecting the address decoding means. In each execution scan, the CPU is compiled and the CPU is executed by the user The address decoding means is set so that the address space of the RAM that stores the program is a specific address space, and the arithmetic processing is performed by executing the execution code on the RAM selected by this setting. After the calculation is completed, the address decoding means is set to select the ROM, and the program stored in the address space corresponding to the specific address space of the selected ROM by this setting is executed. The address space that stores the execution code of the user program obtained by compiling in step 2 is mapped to a specific address space in the memory address space that stores the execution code and can be executed by the CPU. With this, it is possible to use a large-capacity user program, and the execution code is stored when the user program is not executed. It is the real by the C PU The address space that can be executed can be occupied by the ROM, so that programs stored in the ROM can be easily used and the functions of the PC can be increased.

In the invention of claim 2, in the invention of claim 1, at the time of the first execution scan: the source code of the user program on the AM is connected to the execution code executable by the CPU, and the address of the CPU after the compilation is read. Depending on the setting of the decoding means, the RAM that stores the execution code in the specific address space is selected, and the CPU executes the execution code stored in the RAM to execute the arithmetic processing. When scanning, the CPU executes the execution code of the user program to perform calculations and sets the address decoding means to select the RAM that stores the execution code.The execution code executed by the CPU This is effective when using a CPU that can manage the address space that can be accessed by the CPU as data in addition to the address space where can be stored.

According to a third aspect of the present invention, in the first aspect of the present invention, the RAM which stores the source program is selected by the CPU at the time of the first execution scan by setting the address decoding means, and the address corresponding to the specific address space of the RAM is selected. In the space, the CPU compiles the source program into executable code that can be executed on the II line. After the compilation, the CPU executes the execution code stored in the RAM to perform arithmetic processing. Sometimes, when the CPU executes the execution code of the user program to perform the operation, the address decoding means is set so that the RAM that stores the execution code is selected. This is effective when using a CPU that manages only the address space where code can be stored. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a system configuration diagram of Embodiment 1 of the present invention. FIG. 2 is an explanatory diagram of a configuration of an address space used in the embodiment.

FIG. 3 is a flowchart for explaining the operation of the above.

FIG. 4 is a flowchart for explaining the operation of the second embodiment of the present invention.

FIG. 5 is an explanatory diagram of a configuration of an address space used in the above.

FIG. 6 is an explanatory diagram of a configuration of a conventional address space. The best form for carrying out KIKI

(Embodiment 1)

FIG. 1 shows a configuration of a programmable controller (hereinafter, abbreviated as PC) of the present embodiment. The CPU 10 and an execution code (such as a system program including a compile process program and a communication process program) of a system program including a communication process program ROM11 (for example, machine code) is stored. (Of course, a plurality of devices may be used, but one device is shown for the sake of simplicity.) A free address space, a source code for a user program, and an address space for storing an execution code obtained by compiling the source code are provided, and further used for temporarily storing data. RAMI 2 (of course, multiple devices may be used, but one device is shown for simplicity of explanation) and A device selection register 13 in which data for selecting a memory device that allocates an address space to an address space where the CPU 10 can access and execute the execution code is set by the CPU 10, and a device selection register 1 assigning the Select signal S, or § dress outputs S ₂ to the specific address space when § address data for a particular § address space is output from the C PU 1 0 on the basis of the content of the data set in the 3 As a memory device, an address decode circuit 14 for selecting either ROM 11 or RAMI 2 is provided. Here, the device selection register 13 and the address decode circuit 14 provide the address decode means. Constitute. In FIG. 1, DB indicates a data bus and AB indicates an address bus.

Here, as shown in FIG. 2, the CPU 10 used in the programmable controller of the present embodiment has an address space X that can access and execute the execution code and a memory address space X ₂ that can be independently accessed as data. and using what may have respectively different, the ROM 1 1 volume having occupy Adoresu space X _t in the embodiment, with using the RAM I 2 of space occupied by the Adoresu space X _2, Adoresu space X, some of the specific Adoresu spatial X ₁₀ that can be assigned by selecting R OM 1 1 or RAM I 2 by § address decoding means, the remaining Adoresu space ROM 1 1 is a Adoresu space X [pi occupied at all times.

That the C PU 10 is set to "0" in the device selection register 13, § de Resudeko - de circuit 14 assigns the ROM 1 1 when a particular § address space X ₁₀ is accessed. In other words, in this case, the entire ROM 11 occupies the address space X ,. When the CPU 10 sets the device selection register 13 to “1”, the address decode circuit 14 accesses the specific address space X i, and the address space corresponding to the RAMI 2 when the specific address space X i is accessed. In other words, it maps the compilation address space.

Therefore, the CPU 10 can execute the execution code existing in the mapped address space of the RAMI2.

The fixed programs stored in the ROM 11 are system programs that are always required as a system for basic processing as a PC and subroutines for arithmetic processing, and those that are always required for compiling programs such as communication processing programs. The address space X u is allocated as the address space where the constantly needed programs reside, and the specific address space X! Is used as the storage address space for programs that are not always needed. . Is assigned.

Whereas the address space of RAM I 2 that is mapped to a particular address space X ₁₀ is RA Compile address space for storing the execution code generated by compiling the source code of the user program loaded in program (PROG) mode in Ml2 corresponds.

Next, the operation corresponding to the main configuration of the present invention will be described based on the flowchart shown in FIG.

First, the PC can set the PROG (program) mode and the RUN (execution) mode. When the PROG mode is set, the CPU 10 communicates with the programming tool stored in ROM11. Executes a program that performs communication processing of the user, loads the source code of the user program from the programming tool into RAMI 2, or transfers the source code on RAM 12 to the programming tool for debugging. Is performed.

Now, after the user program is loaded on RAMI 2, if the RUN mode is set to execute this user program, the CPU 10 starts compiling on ROM 11 1 to start the first execution scan. And compiles the source code of the user program on RAMI 2 into code that can be executed quickly by the CPU 10 in the compilation address space (indicated as compilation RAM in Fig. 3). .

After this compilation, I / O IZO (not shown) refresh processing is performed, and after this processing, the device selection register 13 is set to "1", and the specific address space Xi. The memory device selected by the address decode circuit 14 when accessing is changed from ROM11 to RAMI2. Therefore, when a particular Adoresu space X ₁₀ is accessed, the a two mapping the address space of the space X ₁₀ (in囡3 denoted as ROM space) in RAM 12 (FIG. 3, denoted as Compiles space). Next, the CPU 10 sets the specific address space X _t . Executes the execution code on the address space of RAMI2 mapped to the above to perform the arithmetic processing. When this operation is completed, The CPU 10 sets "0" in the device selection register 13. Thus returning the memory device when a particular § de Les space X ₁₀ is accessed § address decode circuit 14 selects from the RAM I 2 in ROM 1 1, so that the ROM 1 1 of the Adoresu space is called.

Then, the CFU ₁₀ executes the first execution scan by executing the execution code of the communication processing program stored in the specific address space X10 of the ROM 11.

Thereafter, while the RUN mode is set, the CPU 10 terminates the processing of the input / output IZO (not shown) refresh at each execution scan, and sets "1" to the device selection register 13 to set the specific address space Xi. . The process of changing the memory device selected by the address decode circuit 14 from the ROM 11 to the RAMI 2 when accessing the memory, and the user program that has already been compiled and stored in the RAMI 2 compilation address space. And executing the execution process by executing the execution code of the above. After completion of the calculation process, the device selection register 13 is set to "0", and the specific address space X [. The process of returning the memory device selected by the address decoding circuit 14 from the RAMI 2 to the ROM 11 when accessing the memory, and the specific address space X, of the RO 11. And the step of executing the execution code of the communication processing program stored in the server.

As described above, in the present embodiment, the address space storing the execution code of the user program obtained by compiling on the RAMI 2 is stored in the memory in which the execution code is stored and which can be executed by the CPU 10. A specific address space XL within the address space X,. By mapping the, on which it is possible to have use user blanking grams of large capacity, when not executing the user program can be occupied by ROM11 the Adoresu empty閗X _t, it is stored therefore in ROM 1 1 It is possible to increase the functions of the PC by making it easier to use programs that can be used. (Embodiment 2)

In the first embodiment, the address space X ₂ that can be accessed by the CPU 10 as data can be provided separately from the address space X _{: in} which the execution code executable by the CPU 10 is stored. The present embodiment corresponds to the case where the address space accessible by 10 is limited to the same address space X, for both the data and the execution code.

That is, as shown in the flowchart of FIG. 4, in the present embodiment, at the time of the first execution scan after entering the RUN mode, the device selection register 13 is first set to "1", and the specific address space X is set. The memory device selected by the address decode circuit 14 when accessing the memory is changed from ROM 11 to RAMI 2 as shown in FIG. 5 .The address space of RAMI 2 is changed to a specific address space X ₁₀ (FIG. (Written as Q). The source code of the user program is stored in advance in the address space of RAMI2 (indicated as RAM space in Fig. 4) to be mapped, and after mapping, stored in the address space X 空間 of ROM11. By executing the compilation program, the source code on RAMI 2 mapped to the specific address space X. is compiled to generate execution code (for example, machine code).

Subsequent operations are the same as those in the first embodiment, and a description thereof will not be repeated. Since the configuration as a PC is the same as that of the first embodiment, it is not particularly shown here with reference to (1) of the first embodiment. Industrial applicability

The invention according to claim 1 includes a CPU, a ROM storing a fixed program such as a system program, and a RAM storing an address space for storing a source code of a user program and an address space for compiling the source code. When a specific address space is accessed by setting from the CPU, Address decoding means for selecting another memory device from the current memory device, and allocating, to the ROM, an address space in which the CPU can read and execute the execution code, and assign one of the address spaces to the ROM. The part is used as a specific address space that is also allocated to RAM by selecting the address decoding means, and the CPU is compiled at each execution scan, and the user program that has become an execution code that the CPU can execute at high speed is used. The address decoding means is set so that the address space of the stored RAM is a specific address space, and the execution process is executed by executing the execution code on the RAM selected by this setting, After this operation is completed, the address decode means is set to select the ROM, and this setting corresponds to the specific address space of the selected ROM. Since the program stored in the address space is executed, the address W that stores the execution code of the user program obtained by compiling it on the RAM is vacated by the CPU where the execution code is stored. By mapping to a specific address space in the executable memory address space, it is possible to use a large-capacity user program. The executable address space can be occupied by the ROM, so that it is possible to increase the number of programs stored in the ROM and to increase the functions of the PC.

The invention according to claim 2 is the invention according to claim 1, wherein at the time of the first execution scan, the source code of the user program on the RAM is compiled into an execution code executable by the CPU, and this compilation is performed. After that, according to the setting of the address decoding means of the CPU, the RAM that stores the execution code in the specific address space is selected, and the CPU executes the execution code stored in the RAM to execute the arithmetic processing, and thereafter execute each time. When scanning, the CPU executes the execution code of the user program and performs an operation so that the RAM that stores the execution code is selected. Since the dress-decoding means is set, it is effective when using a CPU that can manage the address space accessible by the CFU as data in addition to the address space that can store the execution code executed by the CPU.

The invention according to claim 3 is the invention according to claim 1, wherein the RAM for storing the source program is selected by the CPU at the time of the first execution scan by the setting for the address decoding means, and the address corresponding to the specific address space of the RAM is selected. In the space, the source program is compiled into executable code that can be executed by the CFU, and after this compilation, the CPU executes the executable code stored in RAM to perform arithmetic processing. When the PU executes the execution code of the user program and performs an operation, the address decoding means is set to select the RAM that stores the execution code, so that the execution code executed by the address space can be stored. This is effective when using a CPU that manages only the address space.

Claims

The scope of the claims

1. CPU, ROM storing fixed programs such as system programs, RAM for setting the address space for storing the source code of the user program and address space for compiling the source code, and setting from the CPU. A specific address space is accessed by a predetermined address space, and the address space is allocated to select another memory device from the current memory device.The address space in which the CPU can read and execute the execution code is provided. In addition to allocating to the ROM, a part of the address space is used as a specific address space that is also allocated to the RAM by selecting address decoding means. At each execution scan, the CPU is compiled and the CPU is executed at high speed. The address space of the RAM that stores the user program that has become The address decoding means is set to be in the dress space, and the execution process is executed by executing the execution code on the RAM selected by this setting. A programmable controller characterized by setting and executing a program stored in an address space corresponding to a specific address blank of a ROM selected by the setting.

2. In the first case, the source code of the user program on the RAM is compiled into an executable code that can be executed by the CPU at the time of the first execution scan. The CPU executes the execution code stored in the specified address space by selecting the RAM that stores the execution code, and the CPU executes the execution code. Set the address decoding means to select the RAM that stores the execution code when executing the operation by executing the execution code.

3. In claim 1, address decoupling by the CPU during the first execution scan -Select the RAM that stores the source program according to the setting of the source means, compile the source program into an executable code that can be executed by the CPU in the address space corresponding to the specific address space of the RAM, and compile this After that, the CPU executes the execution code stored in the RAM to perform the arithmetic processing.After that, the execution code is stored when the CPU executes the execution code of the user program and performs the operation at each execution scan. Set the address decoding method so that the selected RAM is selected.