WO1997032296A1 - Addressable matrix display - Google Patents

Addressable matrix display Download PDF

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Publication number
WO1997032296A1
WO1997032296A1 PCT/US1997/001917 US9701917W WO9732296A1 WO 1997032296 A1 WO1997032296 A1 WO 1997032296A1 US 9701917 W US9701917 W US 9701917W WO 9732296 A1 WO9732296 A1 WO 9732296A1
Authority
WO
WIPO (PCT)
Prior art keywords
address lines
display
elements
addressable
longitudinal
Prior art date
Application number
PCT/US1997/001917
Other languages
French (fr)
Inventor
Vikas Vats
Original Assignee
Motorola Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc. filed Critical Motorola Inc.
Publication of WO1997032296A1 publication Critical patent/WO1997032296A1/en

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3666—Control of matrices with row and column drivers using an active matrix with the matrix divided into sections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • This invention relates to an addressable matrix display such as a liquid crystal display comprising rows and columns of addressable display elements.
  • Conventional addressable matrix displays for example a Liquid Crystal Display (LCD)
  • LCD Liquid Crystal Display
  • the address line are connected to buffer or driving circuits at the edges of the matrix display.
  • the number of row and column address lines can be significantly high. Accordingly, a large number of connections between the driving circuits and address lines are required which may increase production cost and affect reliability. Furthermore, when considering small portable devices, such as pagers, the connection between the driver circuits and matrix display occupy valuable space. In addition, an unnecessary large number of such connections may also affect reliability.
  • an addressable matrix display comprising:
  • each one of said first longitudinal address lines being associated with a respective aligned group of display elements located in said area;
  • each one of said second longitudinal address lines being associated with a respective aligned group of display elements located in said another area;
  • groups of said elements associated with their respective said first longitudinal address lines and groups of said elements associated with their respective said second longitudinal address lines are aligned in rows, and wherein groups of said elements associated with their respective said transverse address lines are aligned in columns.
  • groups of said elements associated with their respective said first longitudinal address lines and groups of said elements associated with their respective said second longitudinal address lines are aligned in columns, and wherein groups of said elements associated with their respective said transverse address lines are aligned in rows.
  • all said elements are associated with their respective address lines by a respective switching means.
  • said switching means may be a transistor.
  • said addressable display matrix is a liquid crystal display.
  • each of said display elements comprises an electrode fabricated on a substantially transparent plate.
  • all said address lines are coupled to buffering circuitry.
  • FIG. 1 is a schematic diagram of a first preferred embodiment of an addressable matrix display in accordance with the invention
  • FIG. 2 is a schematic diagram of a second preferred embodiment of an addressable matrix display in accordance with the invention.
  • FIG. 3 is a diagram illustrating part of a third embodiment of an addressable matrix display in accordance with the invention.
  • FIG. 1 there is illustrated an addressable matrix display in the form of a liquid crystal display 1 coupled to associated buffer and driver circuitry 2,3,4.
  • Liquid crystal display 1 includes a plurality of transverse address lines TAl to TA6, a plurality of first longitudinal address lines LAI to LA6 and a plurality of second longitudinal address lines LA7 to LA12. Associated with each of the address lines are aligned rows and columns of display elements 5 each of which has a common electrode formed on a continuous conductive transparent plate 7.
  • Liquid crystal display also includes a transparent glass plate 6 which is spaced parallel to plate 7. Fabricated on glass plate 6 are the display elements 5, address lines LAI to LA12, TAl to TA6 and thin film transistors 9. The source electrode of each one of transistors 9 is connected to a respective display element 5.
  • a nematic liquid crystal material is sealed between the plates 6,7 and an polarising material is externally coated over one or both of plates 6,7.
  • plates 6,7 are provided with alignment layer as is known in the art.
  • Half of the display elements 5 are in a group located in an area Al on the display and half the display elements are located in an area A2 on the display.
  • First longitudinal address lines LAI to LA6 are aligned in rows and are coupled to the gate electrodes of transistors 9 in the same row.
  • second longitudinal address lines LAI to LA6 are aligned in rows and are coupled to the gate electrodes of transistors 9 in the same row.
  • TA6 are aligned in columns and each column is coupled to the drain electrode of all transistors in two columns. Further, one of these columns is in area Al and the other is in area A2.
  • a light source (not shown) emits light into the display 1 between plates 6,7.
  • the nematic liquid crystal material and display elements 5 modulate this light to provide a visual display as is known to a person skilled in the art.
  • the addressing of elements 5 is dependent upon signals provided along address lines TAl to TA6, LAI to LA12. For example if an element 5a is to be addressed then TAl is set to an appropriate voltage and LA6 is also be set to an appropriate voltage. Alternatively, if an element 5b is to be addressed then TAl is set to an appropriate voltage and LA12 is also set to an appropriate voltage.
  • FIG. 2 a second preferred embodiment of an addressable matrix display 10 is illustrated.
  • the matrix display 10 is almost identical to the display of Fig. 1. Accordingly, to avoid repetition, only the differences will be described.
  • Liquid crystal display 1 includes a plurality of transverse address lines TAl to TA6 forming, a plurality of first longitudinal address lines LAI to LA7 and a plurality of second longitudinal address lines LA8 to LA14.
  • Half of the display elements 5 are in a group located in an area Al on the display and half the display elements are located in an area A2 on the display.
  • First longitudinal address lines LAI to LA7 are aligned in columns and are coupled to the drain electrodes of transistors 9 in the same column.
  • second longitudinal address lines LA8 to LA14 are aligned in columns and are coupled to the drain electrodes of transistors 9 in the same column.
  • transverse address lines TAl to TA6 are aligned in rows and each row is coupled to the gate electrode of all transistors in two rows.
  • one of these columns is in area Al and the other is in area A2.
  • a light source (not shown) emits light into the display 1 between plates 6,7.
  • the nematic liquid crystal material and display elements 5 modulate this light to provide a visual display as is known to a person skilled in the art.
  • the addressing of elements 5 is dependent upon signals provided along address lines TAl to TA6, LAI to LA12. For example, if an element 5a is to be addressed then TAl is set to an appropriate voltage and LA6 is also be set to an appropriate voltage. Alternatively, if an element 5b is to be addressed then TAl is set to an appropriate voltage and LA12 is also set to an appropriate voltage.
  • Fig. 3 a part of a third preferred embodiment is illustrated. This embodiment is similar to the embodiment of Fig. 2 except that the transistors 9 and elements 5 are replaced with passive display elements 16. These passive elements are known in the art an example of which are super-twist nematic liquid crystal display elements. As a result, when addressing elements 16, a potential of 6 Volts is applied to the appropriate lines LAI to LA14 and 0 volts is applied to the appropriate lines TAl to TA6.
  • the present invention requires less connections, between driver circuits 2,3,4 and address lines than that required by conventional addressable displays having more row elements 5 than column elements 5, or vice versa. For instance, in Fig. 1 each row comprises 14 elements whereas each column comprises 6 elements. ' For this configuration the number of connections required between driver circuits 2,3,4 and the address lines TAl to TA6, LAI to LA12 is 19, whereas a conventional addressable matrix display would require 26 connections.
  • each row comprises 1000 elements and each column comprises 100 elements.
  • the present invention advantageously only requires 600 connections (500 transverse connections and 100 longitudinal connections) .
  • a conventional addressable matrix display would require 1100 connections. Accordingly, the present invention may advantageously improve reliability and reduce the amount of space required for coupling addressable matrix displays to driver circuits.

Abstract

An addressable matrix display (1) comprising a plurality of first longitudinal address lines (TA1 to TA6) associated with an area of the display and a respective aligned group of display elements (5). There is also a plurality of second longitudinal address lines (LA7 to LA12) associated with another area of the display and a respective aligned group of display elements (5). The display (5) also has a plurality of transverse address lines (TA1 to TA6) each one of which is associated with a plurality of display elements (5), wherein some of the elements are selectively addressable by signals supplied along the first longitudinal address lines (TA1 to TA6) and transverse address lines (TA1 to TA6). Furthermore, other ones of the elements are selectively addressable by signals supplied along the second longitudinal address lines (LA7 to LA12) and transverse address lines (TA1 to TA6).

Description

ADDRESSABLE MATRIX DISPLAY
FIELD OF THE INVENTION
This invention relates to an addressable matrix display such as a liquid crystal display comprising rows and columns of addressable display elements.
BACKGROUND ART
Conventional addressable matrix displays, for example a Liquid Crystal Display (LCD) , comprise row and column address lines for selectively addressing display elements of the LCD. The address line are connected to buffer or driving circuits at the edges of the matrix display.
When considering conventional matrix displays used for high resolution computer graphics or television pictures, the number of row and column address lines can be significantly high. Accordingly, a large number of connections between the driving circuits and address lines are required which may increase production cost and affect reliability. Furthermore, when considering small portable devices, such as pagers, the connection between the driver circuits and matrix display occupy valuable space. In addition, an unnecessary large number of such connections may also affect reliability.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an addressable matrix display which overcomes or alleviates at least one other problems associated with prior art addressable matrix displays.
According to one aspect of the invention there is provided an addressable matrix display comprising:
a plurality of first longitudinal address lines associated with an area of said display, each one of said first longitudinal address lines being associated with a respective aligned group of display elements located in said area;
a plurality of second longitudinal address lines associated with another area of said display, each one of said second longitudinal address lines being associated with a respective aligned group of display elements located in said another area; and
a plurality of transverse address lines each one of which is associated with a plurality of display elements located in said area and a plurality of display elements located in said another area, wherein said elements in said area are selectively addressable by signals supplied along said first longitudinal address lines and said transverse address lines, and wherein said elements in said another area are selectively addressable by signals supplied along said second longitudinal address lines and said transverse address lines.
Preferably, groups of said elements associated with their respective said first longitudinal address lines and groups of said elements associated with their respective said second longitudinal address lines are aligned in rows, and wherein groups of said elements associated with their respective said transverse address lines are aligned in columns.
In an alternative preferable form, groups of said elements associated with their respective said first longitudinal address lines and groups of said elements associated with their respective said second longitudinal address lines are aligned in columns, and wherein groups of said elements associated with their respective said transverse address lines are aligned in rows.
Preferably, all said elements are associated with their respective address lines by a respective switching means.
Suitably, said switching means may be a transistor.
Preferably, said addressable display matrix is a liquid crystal display.
Suitably, each of said display elements comprises an electrode fabricated on a substantially transparent plate.
Preferably, all said address lines are coupled to buffering circuitry.
Suitably, there are more said elements in said rows than there are in said columns. Alternatively, there may be more said elements in said columns than there are in said rows.
BRIEF DESCRIPTION OF THE DRAWINGS
In order that the invention may be readily understood and put into practical affect, reference will now be made to preferred embodiments as illustrated with reference to the accompanying drawing in which:
FIG. 1 is a schematic diagram of a first preferred embodiment of an addressable matrix display in accordance with the invention;
FIG. 2 is a schematic diagram of a second preferred embodiment of an addressable matrix display in accordance with the invention; and
FIG. 3 is a diagram illustrating part of a third embodiment of an addressable matrix display in accordance with the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF
THE INVENTION
Referring to Fig. 1 there is illustrated an addressable matrix display in the form of a liquid crystal display 1 coupled to associated buffer and driver circuitry 2,3,4. Liquid crystal display 1 includes a plurality of transverse address lines TAl to TA6, a plurality of first longitudinal address lines LAI to LA6 and a plurality of second longitudinal address lines LA7 to LA12. Associated with each of the address lines are aligned rows and columns of display elements 5 each of which has a common electrode formed on a continuous conductive transparent plate 7.
Liquid crystal display also includes a transparent glass plate 6 which is spaced parallel to plate 7. Fabricated on glass plate 6 are the display elements 5, address lines LAI to LA12, TAl to TA6 and thin film transistors 9. The source electrode of each one of transistors 9 is connected to a respective display element 5.
As is known in the art a nematic liquid crystal material is sealed between the plates 6,7 and an polarising material is externally coated over one or both of plates 6,7. In addition, plates 6,7 are provided with alignment layer as is known in the art.
Half of the display elements 5 are in a group located in an area Al on the display and half the display elements are located in an area A2 on the display. First longitudinal address lines LAI to LA6 are aligned in rows and are coupled to the gate electrodes of transistors 9 in the same row. Similarly, second longitudinal address lines LAI to LA6 are aligned in rows and are coupled to the gate electrodes of transistors 9 in the same row. In contrast, the transverse address lines TAl to
TA6 are aligned in columns and each column is coupled to the drain electrode of all transistors in two columns. Further, one of these columns is in area Al and the other is in area A2.
In use, a light source (not shown) emits light into the display 1 between plates 6,7. The nematic liquid crystal material and display elements 5 modulate this light to provide a visual display as is known to a person skilled in the art.
The addressing of elements 5 is dependent upon signals provided along address lines TAl to TA6, LAI to LA12. For example if an element 5a is to be addressed then TAl is set to an appropriate voltage and LA6 is also be set to an appropriate voltage. Alternatively, if an element 5b is to be addressed then TAl is set to an appropriate voltage and LA12 is also set to an appropriate voltage.
Referring to Fig. 2 a second preferred embodiment of an addressable matrix display 10 is illustrated.
The matrix display 10 is almost identical to the display of Fig. 1. Accordingly, to avoid repetition, only the differences will be described.
As illustrated the matrix display 10 is coupled to associated buffer and driver circuitry 11,12,13. Liquid crystal display 1 includes a plurality of transverse address lines TAl to TA6 forming, a plurality of first longitudinal address lines LAI to LA7 and a plurality of second longitudinal address lines LA8 to LA14.
Half of the display elements 5 are in a group located in an area Al on the display and half the display elements are located in an area A2 on the display. First longitudinal address lines LAI to LA7 are aligned in columns and are coupled to the drain electrodes of transistors 9 in the same column. Similarly, second longitudinal address lines LA8 to LA14 are aligned in columns and are coupled to the drain electrodes of transistors 9 in the same column.
In contrast, the transverse address lines TAl to TA6 are aligned in rows and each row is coupled to the gate electrode of all transistors in two rows.
Further, one of these columns is in area Al and the other is in area A2.
When the present invention is in use, a light source (not shown) emits light into the display 1 between plates 6,7. The nematic liquid crystal material and display elements 5 modulate this light to provide a visual display as is known to a person skilled in the art.
In Fig. 1, the addressing of elements 5 is dependent upon signals provided along address lines TAl to TA6, LAI to LA12. For example, if an element 5a is to be addressed then TAl is set to an appropriate voltage and LA6 is also be set to an appropriate voltage. Alternatively, if an element 5b is to be addressed then TAl is set to an appropriate voltage and LA12 is also set to an appropriate voltage.
In Fig. 3 a part of a third preferred embodiment is illustrated. This embodiment is similar to the embodiment of Fig. 2 except that the transistors 9 and elements 5 are replaced with passive display elements 16. These passive elements are known in the art an example of which are super-twist nematic liquid crystal display elements. As a result, when addressing elements 16, a potential of 6 Volts is applied to the appropriate lines LAI to LA14 and 0 volts is applied to the appropriate lines TAl to TA6.
The present invention requires less connections, between driver circuits 2,3,4 and address lines than that required by conventional addressable displays having more row elements 5 than column elements 5, or vice versa. For instance, in Fig. 1 each row comprises 14 elements whereas each column comprises 6 elements. ' For this configuration the number of connections required between driver circuits 2,3,4 and the address lines TAl to TA6, LAI to LA12 is 19, whereas a conventional addressable matrix display would require 26 connections.
As a further example consider an addressable matrix display in which each row comprises 1000 elements and each column comprises 100 elements. The present invention advantageously only requires 600 connections (500 transverse connections and 100 longitudinal connections) . In contrast, a conventional addressable matrix display would require 1100 connections. Accordingly, the present invention may advantageously improve reliability and reduce the amount of space required for coupling addressable matrix displays to driver circuits.
Although the invention has been described with reference to preferred embodiments it is to be understood that the invention is not limited to the embodiment described herein.

Claims

WE CLAIM:
1. An addressable matrix display comprising:
a plurality of first longitudinal address lines associated with an area of said display, each one of said first longitudinal address lines being associated with a respective aligned group of display elements located in said area;
a plurality of second longitudinal address lines associated with another area of said display, each one of said second longitudinal address lines being associated with a respective aligned group of display elements located in said another area; and
a plurality of transverse address lines each one of which is associated with a plurality of display elements located in said area and a plurality of display elements located in said another area, wherein said elements in said area are selectively addressable by signals supplied along said first longitudinal address lines and said transverse address lines, and wherein said elements in said another area are selectively addressable by signals supplied along said second longitudinal address lines and said transverse address lines.
2. An addressable matrix display as claimed in claim 1, wherein groups of said elements associated with their respective said first longitudinal address lines and groups of said elements associated with their respective said second longitudinal address lines are aligned in rows, and wherein groups of said elements associated with their respective said transverse address lines are aligned in columns .
3. An addressable matrix display as claimed in claim 1, wherein groups of said elements associated with their respective said first longitudinal address lines and groups of said elements associated with their respective said second longitudinal address lines are aligned in columns, and wherein groups of said elements associated with their respective said transverse address lines are aligned in rows.
4. An addressable matrix display as claimed in claim 1, wherein all said elements are associated with their respective address lines by a respective switching means.
5. An addressable matrix display as claimed in claim 4, wherein said addressable display matrix is a liquid crystal display.
6. An addressable matrix display as claimed in 5, wherein each of said display elements comprises an electrode fabricated on a substantially transparent plate.
7. An addressable matrix display as claimed in claim 5, wherein all said address lines are coupled to buffering circuitry.
8. An addressable matrix display as claimed in claim 5, wherein there are more said elements in said rows than there are in said columns.
9. An addressable matrix display as claimed in claim 5, wherein there are more said elements in said columns than there are in said rows.
PCT/US1997/001917 1996-02-29 1997-02-05 Addressable matrix display WO1997032296A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SG9606156 1996-02-29
SG9606156-9 1996-02-29

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WO1997032296A1 true WO1997032296A1 (en) 1997-09-04

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2332294A (en) * 1997-12-11 1999-06-16 Sharp Kk Multilayer display panels
EP1811492A1 (en) * 2006-01-23 2007-07-25 TPO Hong Kong Holding Limited Active matrix display device
US20080074567A1 (en) * 2006-09-26 2008-03-27 Jin Jeon Liquid Crystal Display
US20090251403A1 (en) * 2008-04-07 2009-10-08 Himax Technologies Limited Liquid crystal display panel

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4308534A (en) * 1978-12-08 1981-12-29 Kabushiki Kaisha Daini Seikosha Multiplexing liquid crystal display device having different display formats
US4778260A (en) * 1985-04-22 1988-10-18 Canon Kabushiki Kaisha Method and apparatus for driving optical modulation device
JPH01319092A (en) * 1988-06-20 1989-12-25 Nec Corp Thin-film el display device
US4985698A (en) * 1987-10-28 1991-01-15 Hitachi, Ltd. Display panel driving apparatus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4308534A (en) * 1978-12-08 1981-12-29 Kabushiki Kaisha Daini Seikosha Multiplexing liquid crystal display device having different display formats
US4778260A (en) * 1985-04-22 1988-10-18 Canon Kabushiki Kaisha Method and apparatus for driving optical modulation device
US4985698A (en) * 1987-10-28 1991-01-15 Hitachi, Ltd. Display panel driving apparatus
JPH01319092A (en) * 1988-06-20 1989-12-25 Nec Corp Thin-film el display device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2332294A (en) * 1997-12-11 1999-06-16 Sharp Kk Multilayer display panels
EP1811492A1 (en) * 2006-01-23 2007-07-25 TPO Hong Kong Holding Limited Active matrix display device
US20080074567A1 (en) * 2006-09-26 2008-03-27 Jin Jeon Liquid Crystal Display
US8144114B2 (en) * 2006-09-26 2012-03-27 Samsung Electronics Co., Ltd. Liquid crystal display
US20090251403A1 (en) * 2008-04-07 2009-10-08 Himax Technologies Limited Liquid crystal display panel
CN101556780B (en) * 2008-04-07 2011-10-12 奇景光电股份有限公司 Liquid crystal display panel

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