WO1997027626A1 - Boitier de circuit integre a dissipation calorifique et mise a la masse ameliorees - Google Patents

Boitier de circuit integre a dissipation calorifique et mise a la masse ameliorees Download PDF

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Publication number
WO1997027626A1
WO1997027626A1 PCT/US1997/001360 US9701360W WO9727626A1 WO 1997027626 A1 WO1997027626 A1 WO 1997027626A1 US 9701360 W US9701360 W US 9701360W WO 9727626 A1 WO9727626 A1 WO 9727626A1
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WIPO (PCT)
Prior art keywords
puck
integrated circuit
lead frame
die
recited
Prior art date
Application number
PCT/US1997/001360
Other languages
English (en)
Inventor
Albert C. Imhoff
Richard John Giacchino
Paul Eugene HOGAN II
Original Assignee
The Whitaker Corporation
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Filing date
Publication date
Application filed by The Whitaker Corporation filed Critical The Whitaker Corporation
Publication of WO1997027626A1 publication Critical patent/WO1997027626A1/fr

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01039Yttrium [Y]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01057Lanthanum [La]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Definitions

  • a specific IC package may be used for different types of IC dies. Therefore, specialized and low volume ICs can realize the benefits of low cost standardized packaging under some circumstances.
  • the printed circuit board (PCB) manufacturing processes are designed and optimized to accept the standard package sizes and shapes available from IC manufacturers. As digital ICs become faster and more highly integrated, they consume and, therefore, must dissipate increasing amounts of power during operation. For some ICs, it is possible to dissipate all of the generated heat through the wirebonds, the lead frame and the leads to the PCB. For ICs that have relatively higher power dissipation requirements, it is known to attach a metal puck on the top of a lead frame.
  • the puck is attached to the lead frame by attachment compound or by brazing as disclosed in U.S. Patent No. 3,930,114.
  • the puck is disposed within a plastic IC package so that an major surface of the puck is exposed on a top side of the IC, the top side being the side facing away from the IC leads that engage a PCB.
  • metal fins are attached to the puck for additional heat dissipating capacity.
  • Heat generated by the IC flows from the die and/or the lead frame through the attachment compound and to the puck and/or fins. Air flows or is forced over the puck surface/fins for cooling to dissipate the heat generated by the IC.
  • the smaller packaging provides for less air volume for cooling in higher power products. There is a need, therefore, for a small plastic package for power ICs having an efficient heat dissipation capability.
  • plastic packages that are conventional in the industry are advantageously an acceptable low cost packaging option for most digital and low frequency ICs.
  • plastic packaging is an attractive option.
  • Many of the components in mobile communication applications require operation at radio frequencies (RF) and higher.
  • RF radio frequencies
  • the conventional plastic IC packaging however, has certain disadvantages at RF and microwave operating frequencies.
  • An integrated circuit package having a seating plane side comprises a die, a lead frame, and a metal puck disposed on said lead frame.
  • the lead frame is encased in the package material exposing a surface of the puck and the leads. The surface of the puck is exposed on the seating plane side of the integrated circuit package.
  • a package for a high frequency IC has a high quality path to RF ground.
  • a package for a high frequency IC can dissipate substantial heat in a relatively small package and with limited air volume.
  • a dissipation material is constrained from thermal expansion by a constraining material sufficient so as to reduce stress on the die so as not to exceed the tensile strength of the die.
  • a material can have an engineered coefficient of thermal expansion providing for a match to an IC die, while still providing favorable high thermal conductivity and dissipation.
  • Figure 1 is a cross sectional view of a plastic integrated circuit package according to the teachings of the present invention.
  • Figure 2 is a cross sectional view of an alternate embodiment of a plastic integrated circuit package according to the teachings of the present invention showing coplanarity between ends of the integrated circuit package leads distal from the die attach paddle and an exposed first major surface of the puck.
  • Figure 3 is a cross sectional view of an alternate embodiment of a plastic integrated circuit package according to the teachings of the present invention showing coplanarity between ends of the integrated circuit package leads and the bottom surface of the puck.
  • Figure 4 is a plan view of a position in a dual position lead frame strip for use in a preferred embodiment according to the teachings of the present invention as seen prior to encapsulation and singulation.
  • the IC package body outline is shown in phantom line.
  • Figure 5 is a plan view of a position in a dual position strip of an alternate embodiment of a lead frame strip according to the teachings of the present invention.
  • Figure 6 is a plan view of a position in a dual position puck frame strip illustrating two pucks prior to attachment to a lead frame and singulation.
  • the puck frame is for use in conjunction with the lead frame illustrated in Figures 4 and 5 to manufacture an integrated circuit package according to the teachings of the present invention.
  • Figure 7 is a cross sectional view of the puck cut along the lines 7--7 of Figure 6.
  • Figure 8 is a view of a die with wire bonds attached to the die attach paddle according to the teachings of the present invention.
  • Figure 9 is a perspective view of the puck frame superimposed upon the lead frame after metallurgical attachment according to the teachings of the present invention and prior to die attach, encapsulation, and singulation.
  • the superi position of the lead frame and puck frame shows conceptual alignment of the two frames.
  • Figure 10 is a perspective view of a plastic packaged integrated circuit shown with the plastic package partially cut away to illustrate the relative positioning of the die, the lead frame, the puck, and the leads according to the teachings of the present invention.
  • Figure 11 is a cross sectional view of a punch press and puck frame prior to singulation of the pucks.
  • Figure 12 is a cross sectional view of a punch press and puck frame subsequent to singulation of the pucks.
  • Figure 13 is a cross sectional view of an adapter that retains the pucks and fixture for receipt of prepared lead frames.
  • Figure 14 is a cross sectional view of the adapter assembly held by a transfer tool.
  • Figure 15 is a cross sectional view of the adapter and pucks placed over a lead frame fixture and lead frame .
  • Figure 16 is a cross sectional view of the adapter and pucks over a lead frame fixture with cover plate and weight prior to a reflow operation to attach the pucks to the lead frames.
  • Figure 17 is a perspective view of a plastic packaged integrated circuit shown with the plastic package partially cut away to illustrate the relative position of the seating plane side of the IC relative to the puck.
  • Figure 18 is a cross section of one embodiment of a puck according to the teaching of the present invention illustrating the different material layers of the puck.
  • an integrated circuit (IC) package 40 has a seating plane side 41.
  • the seating plane side 41 is defined as that side of the IC toward which respective ends of the leads, distal from the package, extend.
  • the IC package 40 is an SOIC-8 package according to the JEDEC standard 95, MS-012.
  • the seating plane side 41 is juxtaposed to or, in the case of surface mount IC packages, engages the printed circuit board substrate.
  • the IC package 40 comprises an integrated circuit die 1 attached to a die attach paddle 4 of a lead frame 2 using electrically conductive adhesive 8.
  • the IC die 1 is a GaAs based power amplifier, although any IC that may benefit from a high quality ground and efficient thermal dissipation capacity is appropriate.
  • a high frequency power amplifier requires heat dissipation capability as well as a high quality reference, or ground, for the high frequency energy.
  • the die attach paddle 4 has a first side 5 on which the die is disposed and a second opposite side 6 on which is disposed a puck 10.
  • the puck 10 is a solid copper cylindrical disc stamped out of metal having internal and external major surfaces 12,11.
  • the internal major surface 12 of the puck 10 is electrically connected to the die attach paddle 4 by means such as soldering, brazing, or welding.
  • a diameter of the puck 10 is sized relative to the die attach paddle 4 so as to fit within the confines of, but substantially cover the paddle 4.
  • the integrated circuit die 1 has contacts 42 electrically attached to signal lines on the IC.
  • the contacts 42 are electrically attached to respective leads 3 of the lead frame 2 through a wire bond 7 using conventional means.
  • Ground lines of the integrated circuit die 1 are electrically attached to the die attach paddle 4 through a wire bond 7 as illustrated in Figure 8.
  • the integrated circuit package 40 is manufactured and the IC die 1 and puck 10 appropriately positioned so that the external major surface 11 of the puck is exposed after plastic packaging material 9 is formed around the die, lead frame, wirebonds, and puck.
  • the leads 3 and the exposed surface 11 of the puck 10 are soldered to conductive traces on the printed circuit board substrate in a conventional manner.
  • the printed circuit board is laid out to have a connection point to RF ground, or in an alternate embodiment, any ground, at a point between and central to the two parallel lines of connection points that receive the IC leads 3.
  • the puck 10 is electrically attached to a ground trace or ground plane on the printed circuit board underneath the IC package.
  • Soldering the exposed surface of the puck 10 to an electrical reference point on the PCB completes the electrical path from a point on the IC to the PCB.
  • the conventional ground path is from the die through a wire bond to the lead of the lead frame, and the lead to the ground connection on the PCB.
  • a high quality ground path is realized without increasing the size of the package.
  • a specific example might be if circuitry external to the packaged IC needed access to the reference or ground of the IC.
  • a wire bond 7 could connect a ground contact 42 to the die attach paddle 4 as well as one or more leads 3 as desired.
  • the lead frame 2 could be manufactured to have one or more leads 3 fused to the die attach paddle 4. See Figure 5 showing two of the leads 3 fused to the die attach paddle 4.
  • electrical connection to the die attach paddle 4 would not be through a wire bond 7, but rather through the IC die itself .
  • Attachment of the puck 10 in this manner also provides efficient thermal conduction from the IC die 1, through the die attach paddle 4 , and through the puck 10, where heat is dissipated through the printed circuit board, ground traces, and/or a ground plane thereon.
  • a thermal ground connection through the puck 10 is a more direct path and has a greater cross sectional area than an IC lead through which to conduct heat .
  • Heat is conducted through the puck 10 to a PCB by physical contact where is it further conducted through the PCB itself.
  • the PCB has a larger surface area than the IC. As the heat is distributed over the larger surface area, it can be more efficiently dissipated.
  • a preferred process to manufacture a plastic packaged integrated circuit comprises the steps of: attaching a puck 10 to a lead frame 2, attaching an integrated circuit die 1 to the lead frame 1, wire bonding electrical connections from the integrated circuit to a die attach paddle 4 of the lead frame 2 and to respective leads 3 of the lead frame 2, encapsulating the lead frame 2 with plastic packaging 9, trimming the packaged IC from the lead frame 2, and forming the leads 3 of the lead frame 2 into a finished part.
  • a preferred embodiment of the step of attaching a puck 10 to a lead frame 2 further comprises the steps of preparing the lead frame 2 by stenciling solder paste onto an unplated side of the lead frame 2. Solder paste is placed on the die attach paddle 4 of respective lead frames 2 in a strip. The prepared lead frame 3 is placed solder side up into a lead frame fixture 13 that holds the lead frame 2 stationary.
  • a puck frame 15 is placed onto registration pins (not shown) on punch tooling.
  • the registration pins cooperate with registration holes 14 in the puck frame 15.
  • the pucks 10 are singulated from a puck frame 15 by the punch tooling prior to placement and attachment to the lead frame 2.
  • Figure 9 of the drawings illustrates the conceptual alignment of the puck frame 15 to the lead frame 2 showing coincidence of the registration holes 14 of the lead frame 2 and the puck frame 15 for proper alignment.
  • Singulation comprises placing the puck frame 15 on a punch press 16. When the punch press 16 is actuated, the pucks 10 are singulated and separated from the puck frame 15.
  • the puck frame 15 remains on the punch press tooling 16.
  • An adapter 17 is placed over the singulated pucks 10.
  • the adapter 17 has guide holes 21.
  • a transfer tool 18 picks up the adapter 17 by vacuum actuation which holds the adapter 17 and the pucks 10 in proper position.
  • the transfer tool 18 picks and places the adapter 17 and pucks 10 over the prepared lead frame 2 located on the lead frame fixture 13.
  • Guide pins 22 of the lead frame fixture 13 cooperate with the guide holes 21 of the adapter to properly register the singulated pucks 10 to the lead frames 2.
  • a cover plate 19 is placed over the adapter 17.
  • the cover plate 19 is further covered by a weight 20.
  • the weighted lead frame fixture 13 assembly is heated in a controlled inert gas atmosphere to reflow the solder and attach the pucks 10 to respective lead frames 2.
  • the prepared lead frame 2 with the pucks 10 thereon is then used in the die attach, wire bonding, and encapsulation steps.
  • the packaging steps using a lead frame 2 prepared with pucks 10 according to the teachings of the present invention result in a plastic IC package having the external major surface of the puck 10 exposed on a seating plane side 41 of the finished IC package 40. It is preferred that the encapsulated lead frame 2 is trimmed and formed so the end of respective leads 3 distal from the lead frame 2 are substantially coplanar with the exposed surface 11 of the puck 10.
  • the coplanarity provides for easier attachment of the puck 10 to the printed circuit substrate during the solder step of attaching leads to the printed circuit substrate.
  • the exposed surface 11 of the puck 10 is substantially coplanar with the seating plane side surface of the plastic of the IC as well as ends of the leads 3 distal from the lead frame 2. See Figure 2 of the drawings .
  • a conventional trim and form tool is modified to form the ends of the leads 3 distal from the lead frame 2 to be coplanar with a seating plane side of the plastic package and puck 10.
  • a thickness of the puck 10 is selected, so that the exposed surface protrudes from the seating plane side 41 of the packaged IC 40 a distance of approximately 5 mils for an SOIC-8 plastic package. The protrusion achieves the desired substantial coplanarity of ends of the leads and the exposed surface 11 of the puck 10 without a modification of the conventional trim and form tool . See Figure 3 of the drawings .
  • a solid copper puck 10 as disclosed hereinbefore is capable of dissipating heat in a plastic package for a four watt GaAs integrated circuit power device .
  • the four watt device limitation is due in part to the thermal expansion differential between the die attach paddle 4, the IC die 1, and the bonds therebetween. As the IC die 1 heats, heat transfers as intended to the die attach paddle 4 and puck 10. The die attach paddle 4, therefore, heats as does the IC die 1. Due to the different coefficients of thermal expansion between the GaAs IC die 1 and copper die attach paddle 4, a stress is imposed on the die 1. If the resulting stress exceeds the strength of the die 1, the die 1 cracks resulting in catastrophic device failure.
  • the difference in thermal expansion coefficients between the die 1 and the die attach paddle 4 may be addressed in part through use of conductive adhesive to attach the die 1 to the die attach paddle 4.
  • the compliance of the conductive adhesive relieves the stress between the die 1 and the die attach paddle 4 through resilient deformation.
  • the conductive adhesive is less thermally conductive than less compliant methods of attachment.
  • the lower thermal conductivity adversely affects the amount of heat that can be reliably dissipated through the puck 10, thereby limiting the overall power rating of the packaged IC 40.
  • the general trend in the industry is toward higher power devices. There is a need, therefore, for a low cost plastic package that can dissipate heat for higher power devices with acceptable reliability.
  • a material from which a puck 10 can be made that exhibits high thermal conductivity while at the same time having a coefficient of thermal expansion matched to that of the IC die 1.
  • the puck 10 is attached to the copper die attach paddle 4.
  • the copper die attach paddle 4 has an opening 44 therein within which the die 1 is received.
  • the internal major surface 12 of the puck 10 is larger than the opening 44 in the die attach paddle 4.
  • the die 1 is soldered directly onto the internal major surface 12 of the puck 10 providing for a highly thermally and electrically conductive rigid bond between the die 1 and the puck 10.
  • the puck 10 when made according to the teachings of the present invention exhibits thermal expansion within acceptable expansion limits of the IC die 1, thereby obviating the need for a compliant bond between the die 1 and the puck 10. It is the salient characteristics of the puck 10 that are matched to the IC die 1 that provides the intended advantage.
  • the term "matched" is defined as significantly close so that within the anticipated range of operating temperature, the die 1 and the puck 10 exhibit similar thermal expansion so that the stress placed on the IC die 1 due to the respective expansions between the die 1 and the puck 10 does not exceed the tensile strength of the IC die 1.
  • some IC dies for example gallium arsenide, have a non linear coefficient of thermal expansion that decreases as the die temperature increases. The coefficient of thermal expansion, therefore, must be carefully chosen so that the stress placed on the IC die 1 falls within an appropriate range.
  • the carefully chosen material exhibiting the thermal expansion properties matched to the IC die 1 makes possible the direct attachment of die 1 to puck 10.
  • the puck 10 is attached to the die attach paddle 4 by any known means including soldering, braising, welding or adhesive attachment.
  • the die attach paddle 4 has an opening sufficiently large to fully receive the IC die 1.
  • the IC die 1 is attached directly to the puck 10, by soldering for example, and is surrounded by the die attach paddle 4.
  • the puck 10 is made from a laminated metal .
  • the laminate comprises alternating thermal dissipation and constraining layers 30, 31.
  • the dissipation layer is made from a high electrical and thermal conductivity material, typically metal.
  • the constraining layer 31 provides acceptable and sufficient electrical and thermal conductivity but has a lower coefficient of expansion.
  • the thermal dissipation layer 30 provides for the thermal and electrical conduction necessary for appropriate performance of the puck 10.
  • the constraining layer 31 may have a lower but sufficient thermal and electrical thermal conductivity but due to its lower coefficient of thermal expansion limits or constrains the actual expansion of the thermal dissipation layer.
  • the lamination of the two metals is performed according to conventional practice.
  • the bond between the thermal dissipation layer 30 and the constraining layer 31 is sufficiently strong to withstand the stress present at the interface of the two metals. Any odd number of layers is appropriate with the constraining layers being internal to the puck 10.
  • the outside layers 33 having the higher thermal conductivity are attached to the PCB and the die 1/die attach paddle 4 respectively.
  • the properties of the laminated puck material may be selected by the selection of layer thicknesses and materials employed for the layers.
  • Thermal conductivity and coefficient of thermal expansion is estimated from the following relations.
  • EFFECTIVE the effective thermal conductivity
  • I is the total thickness of the puck 10, /, is the layer thickness, k, is the thermal conductivity of the layer, and /represents the number of layers.
  • ct EFFECTIVE A simplified relation is used to predict the effective coefficient of thermal conductivity, ct EFFECTIVE :
  • / is the layer thickness
  • EYs Young's Modulus of the layer
  • is the coefficient of thermal expansion of the layer
  • / represents the number of layers. Accordingly, the effective values of thermal conductivity and coefficient of thermal expansion may be engineered through the selection of desired thicknesses of the conductive and constraining layers.
  • the preferred puck material has nine layers, comprising five copper dissipation layers 30 each having a thickness of approximately 3 mils and four molybdenum, constraining layers 31, each having a thickness of approximately 3 mils.
  • the laminated metal may be stamped and processed into a plastic package in identical fashion as with the solid copper puck as is described above.
  • the puck 10 is made from a mixture of two powered materials, typically metal comprising a dissipation material and a constraining material.
  • the puck 10 made from powdered metal operates the same way the laminate version does, except that one layer is not constraining an adjacent layer, rather the material itself based on its heterogeneous composition, is constrained in X,Y and Z axes as opposed to along a plane (i.e. just the X and Y directions) .
  • the powdered materials are mixed in specific proportion, pressed, and sintered to an effective density of between 92 and 99 percent solid according to conventional practice. Although most metals are appropriate, depending upon the desired characteristics, the preferred dissipation material is copper and the preferred constraining material is tungsten.
  • the composition of the puck 10 is determined by employing conventional powder metallurgy techniques to obtain high thermal conductivity with the desired coefficient of thermal expansion.
  • the theoretical density P THEORETICA of a powdered metal material can be estimated by the following equation:
  • J rHI RLU AL (Wt% m , ut x p ( omR ) + (Wt% TUNC ⁇ 1LN n/NG TI
  • Wt% represents the percentage of the total weight of each material .
  • powdered metal materials The nature of powdered metal materials is that m practice this theoretical density is never achieved due to processing variations. Therefore it is valuable to consider the powdered metal material in terms of its fractional density, the ratio of measured versus theoretical densities. This fractional density is an important component in determining final mechanical properties .
  • n is a factor associated with the density and structure of the powder metal compact. Values for n are in the range of 0.8 to 1.10. In many instances n can be approximated as :
  • the puck 10 for a gallium arsenide IC die 1
  • the puck 10 is made using 10% by weight of copper and 90% by weight of tungsten pressed and sintered to yield a 94% solid puck weight .
  • the pressed and sintered puck 10 results in a final puck format rather than a sheet of metal that may be stamped. Therefore, the process by which the puck 10 would be attached to the die attach paddle 4 does not include a puck frame 15. Attachment of the puck 10 to the die attach paddle 4 is by way of a fixture to position the puck 10 over the lead frame. The puck 10 may thereafter be attached to the die attach paddle 4 of the lead frame 2. Solder is the preferred method of attachment of the puck 10 to the die 1.
  • both embodiments are capable of dissipating power for a 10 watt GaAs device in a reliable plastic package.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

La présente invention concerne un boîtier plastique de circuit intégré (40) comportant une structure de puits thermique dont une majeur partie de la surface (11) donne sur la face plane d'assise (41) du circuit intégré en boîtier. Un disque (10) est solidarisé à la semelle de fixation de microplaquette (4) d'une grille de connexions (2). Ce disque est également électriquement connecté à la masse de la microplaquette du circuit intégré (1). Le disque est constitué d'un premier matériau thermoconducteur combiné à un second matériau limitant la dilatation thermique pour assurer une meilleure dissipation de l'énergie dans le circuit intégré en boîtier de plastique (40).
PCT/US1997/001360 1996-01-26 1997-01-27 Boitier de circuit integre a dissipation calorifique et mise a la masse ameliorees WO1997027626A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US59199496A 1996-01-26 1996-01-26
US08/591,994 1996-01-26

Publications (1)

Publication Number Publication Date
WO1997027626A1 true WO1997027626A1 (fr) 1997-07-31

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WO (1) WO1997027626A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7042730B2 (en) * 2002-07-31 2006-05-09 International Rectifier Corporation Non-isolated heatsink(s) for power modules
US7812441B2 (en) 2004-10-21 2010-10-12 Siliconix Technology C.V. Schottky diode with improved surge capability
US9419092B2 (en) 2005-03-04 2016-08-16 Vishay-Siliconix Termination for SiC trench devices
US9627552B2 (en) 2006-07-31 2017-04-18 Vishay-Siliconix Molybdenum barrier metal for SiC Schottky diode and process of manufacture
US9627553B2 (en) 2005-10-20 2017-04-18 Siliconix Technology C.V. Silicon carbide schottky diode

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63142838A (ja) * 1986-12-05 1988-06-15 Matsushita Electronics Corp 半導体装置
JPH04171749A (ja) * 1990-11-02 1992-06-18 Mitsubishi Electric Corp 半導体装置
EP0521405A1 (fr) * 1991-07-01 1993-01-07 Sumitomo Electric Industries, Ltd. Composant évacuant la chaleur et dispositif semi-conducteur qui en est muni
JPH07153878A (ja) * 1993-11-26 1995-06-16 Tokyo Tungsten Co Ltd プラスチックパッケージされた半導体装置ならびにヒートシンクの製造方法
US5493153A (en) * 1992-11-26 1996-02-20 Tokyo Tungsten Co., Ltd. Plastic-packaged semiconductor device having a heat sink matched with a plastic package

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63142838A (ja) * 1986-12-05 1988-06-15 Matsushita Electronics Corp 半導体装置
JPH04171749A (ja) * 1990-11-02 1992-06-18 Mitsubishi Electric Corp 半導体装置
EP0521405A1 (fr) * 1991-07-01 1993-01-07 Sumitomo Electric Industries, Ltd. Composant évacuant la chaleur et dispositif semi-conducteur qui en est muni
US5493153A (en) * 1992-11-26 1996-02-20 Tokyo Tungsten Co., Ltd. Plastic-packaged semiconductor device having a heat sink matched with a plastic package
JPH07153878A (ja) * 1993-11-26 1995-06-16 Tokyo Tungsten Co Ltd プラスチックパッケージされた半導体装置ならびにヒートシンクの製造方法

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Title
PATENT ABSTRACTS OF JAPAN vol. 012, no. 402 (E - 673) 25 October 1988 (1988-10-25) *
PATENT ABSTRACTS OF JAPAN vol. 016, no. 478 (E - 1274) 5 October 1992 (1992-10-05) *
PATENT ABSTRACTS OF JAPAN vol. 095, no. 009 31 October 1995 (1995-10-31) *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7042730B2 (en) * 2002-07-31 2006-05-09 International Rectifier Corporation Non-isolated heatsink(s) for power modules
US7812441B2 (en) 2004-10-21 2010-10-12 Siliconix Technology C.V. Schottky diode with improved surge capability
US9412880B2 (en) 2004-10-21 2016-08-09 Vishay-Siliconix Schottky diode with improved surge capability
US9419092B2 (en) 2005-03-04 2016-08-16 Vishay-Siliconix Termination for SiC trench devices
US9627553B2 (en) 2005-10-20 2017-04-18 Siliconix Technology C.V. Silicon carbide schottky diode
US9627552B2 (en) 2006-07-31 2017-04-18 Vishay-Siliconix Molybdenum barrier metal for SiC Schottky diode and process of manufacture

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