WO1997023035B1

WO1997023035B1 - Triple-balanced passive transmission fet mixer

Info

Publication number: WO1997023035B1
Application number: PCT/US1996/019964
Authority: WO
Filing date: 1996-12-18
Publication date: 1997-08-21

Abstract

FET mixer comprising two switching circuits, each comprising two series connected FET transistors (Q1, Q2; Q3, Q4); a local oscillator balun (T1A, T1B) having a single two terminal input port and two terminal output ports, each output port being connected to the together connected bases of the transistors (Q1, Q2; Q3, Q4) of one of the switching circuits; an RF balun (T2A, T2B) connecting the RF input signal to the drains of the transistors of the switching circuits; an IF balun (T3A, T3B) and a DC bias circuit (45). The mixer needs only a low local oscillator power, provides for a partial cancellation of the nonlinearity distortion imposed on the RF signal and has a reduced intermodulation distortion.

Claims

AMENDED CLAIMS[received by the International Bureau on 21 June 1997 (21 06 97), original claims 1 and 10 amended, new claims 21-26 added, remaining claims unchanged (6 pages)]

1. A triple balanced mixer comprising: a first switching circuit comprising a first and a second FET transistor each having a gate and a drain and a source, the first and second FET transistors having their gates connected to one another and their sources connected together such that the first and second FET transistors are connected in series; a second switching circuit comprising a third and a fourth FET transistor each having a gate and a drain and a source, the third and fourth FET transistors having their gates connected to one another and their sources connected together such that the third and fourth FET transistors are connected in series; a balanced local oscillator circuit for providing a signal to switch said first and second switching circuits including an LO balun having a two-terminal input port for connection to an external local oscillator signal source, a first two-terminal output port coupled to the gate and the source of said first and second FET transistors, and a second two-terminal output port coupled to the gate and source of said third and fourth

FET transistors; a first balun termination resistor coupled across a first output port of said LO balun; a second balun termination resistor coupled across a second output port of said LO balun; a first capacitor connected in series with said first output port of the LO balun and with said gates belonging to the first and second FET transistors; a second capacitor connected in series with said second output port of the LO balun and with said gates belonging to the third and fourth FET transistors; and an intermediate frequency (IF) balun having a two-terminal input port for coupling to an external intermediate frequency source, and first and second two- terminal output ports; a radio frequency (RF) balun having a two-terminal input port for coupling to an external radio frequency source, and first and second two-terminal output ports; a first terminal of said first RF balun output port electrically connected to said first FET drain and to a second terminal of said first IF balun output port; a second terminal of said first RF balun output port electrically connected to said

AMENDED SHEET (ARTICLE 1$ third FET drain and to a second terminal of said second IF balun output port; a first terminal of said second RF balun output port electrically connected to said fourth FET drain and to a first terminal of said first IF balun output port; a second terminal of said second RF balun output port electrically connected to said second FET drain and to a first terminal of said second IF balun output port; said electrical connection between said local oscillator balun and said source and gate terminals of said first, second, third, and fourth FET transistors being in pair-wise phase complementary manner wherein the signal from said first terminal of said local oscillator circuit is coupled to the gates of said FETs in said first switching circuit and to said sources in said second switching circuit and wherein the signal from said second terminal of said local oscillator circuit is coupled to the sources of said FETs in said first switching circuit and to said gates in said second switching circuit such that said first and second FET transistors are driven about 180 degrees out of phase relative to the driving of said third and fourth FET transistors such that said first and second FET transistors are driven to ON and OFF conduction states opposite to conduction states of said third and fourth FET transistors; and dc bias means coupled to each FET transistor source for applying a dc bias voltage from an external bias voltage source to the source terminals of each of said first, second, third, and fourth FET transistors such that intermodulation distortion is reduced by the application of the bias voltage to the source terminals of said FET transistors; and wherein symmetry of the mixer provides partial cancellation of nonlinearity distortion imposed on the RF signal.

2. The mixer in Claim 1, wherein said bias means comprising a bias voltage input port for coupling to an external bias voltage source; and a bias scaling resistor and a reverse bias protection diode and a impedance matching resistor serially coupled between said bias voltage input port and an FET transistor source terminal; and an ac isolation capacitor coupled between said serially coupled diode and impedance matching resistor; said RF balun and said IF balun terminals coupled to said

FET gate terminals providing a return path for said bias current introduced at said FET source terminals.

3. The mixer in claim 1 , wherein said mixer further comprising first and second dc blocking capacitors connected to said balanced oscillator circuit two-terminal input port and inteφosed between said local oscillator circuit and said external local oscillator source for blocking a predetermined range of low frequency signals from said mixer.

4. The mixer of claim 1, wherein said baluns comprises a transmission line baluns.

5. The mixer of claim 4, wherein said transmission line balun comprises bifilar windings on a ferrite core.

6. The mixer of claim 5, wherein said RF transmission line balun has a characteristic impedances of approximately 50 ohms.

7. The mixer of claim 1 , further comprising a ceramic substrate.

8. The mixer of claim 1, further comprising an alumina ceramic substrate subjacent first FET, said second FET, said third Fet, and said fourth FET.

9. The mixer of claim 7, wherein each said FET transistors comprise a GaAs MESFET MMIC device mounted to the alumina substrate.

10. The mixer of Claim 1 , wherein said mixer operates in the LO/RF/IF frequency range between 10 Mhz and 1000 MHz.

11. A mixer comprising: a first switching circuit comprising a first and a second FET transistor each having a gate and a drain and a source, the first and second FET transistors having their gates connected to one another and their sources connected together such that the first and second FET transistors are connected in series; a second switching circuit comprising a third and a fourth FET transistor each having a gate and a drain and a source, the third and fourth FET transistors having their gates connected to one another and their sources connected together such that the third and fourth FET transistors are connected in series; a balanced local oscillator input port for receiving an external local oscillator signal and for coupling said local oscillator signal to said first and second switching devices, a local oscillator balun having a two-terminal input port coupled to said external local oscillator and a first two-terminal output port coupled to the gate and the source of said first and second FET transistors, and a second two-terminal output port coupled to the gate and source of said third and fourth FET transistors; and an intermediate frequency (IF) balun having a two-terminal input port for coupling to an external intermediate frequency source, and first and second two- terminal output ports; a radio frequency (RF) balun having a two-terminal input port for coupling to an external radio frequency source, and first and second two-terminal output ports; a first terminal of said first RF balun output port coupled to said first FET drain and to a second terminal of said first IF balun output port, a second terminal of said first RF balun output port coupled to said third FET drain and to a second terminal of said second IF balun output port, a first terminal of said second RF balun output port coupled to said fourth FET drain and to a first terminal of said first IF balun output port, a second terminal of said second RF balun output port coupled to said second FET drain and to a first terminal of said second IF balun output port; said coupling between said local oscillator balun and said source and drain terminals of said first, second, third, and fourth FET transistors being in pair-wise phase complementary manner such that said first and second FET transistors are driven about 180 degrees out of phase relative to said third and fourth FET transistors such that said first and second FET transistors are driven to on and off conduction states opposite to the conduction states of said third and fourth FET transistors.

12. The mixer of Claim 11, further comprising: a first balun termination resistor coupled across a first output port of said local oscillator balun; a second balun termination resistor coupled across a second output port of said local oscillator balun; a first capacitor connected in series with said first output port of the LO balun and with said gates belonging to the first and second FET transistors; and a second capacitor connected in series with said second output port of the LO balun and with said gates belonging to the third and fourth FET transistors.

13. The mixer in Claim 11, further comprising dc bias means coupled to each FET transistor source for applying a dc bias voltage from an eternal bias voltage source to the source terminals of each of said first, second, third, and fourth FET transistors.

14. The mixer in Claim 13, wherein said bias means comprising a bias voltage input port for coupling to an external bias voltage source; and a bias scaling resistor and a reverse bias protection diode and a impedance matching resistor serially coupled between said bias voltage input port and an FET transistor source terminal; and an ac isolation capacitor coupled between said serially coupled diode and impedance matching resistor; said RF balun and said IF balun terminals coupled to said FET gate terminals providing a return path for said bias current introduced at said FET source terminals.

15. The mixer in claim 11, wherein said mixer further comprising first and second dc blocking capacitors connected to said balanced oscillator two-terminal input port and interposed between said local oscillator circuit and said external local oscillator source for blocking a predetermined range of low frequency signals from said mixer.

16. The mixer in claim 15, wherein said predetermined range of low frequency signals include d.c. signals.

17. The mixer of claim 11, wherein said baluns comprise transmission line baluns.

18. The mixer of claim 17, wherein said transmission line balun comprises bifilar windings on a ferrite core.

19. The mixer of claim 17, wherein said RF transmission line balun has a characteristic impedances of approximately 50 ohms.

20. The mixer of claim 11 , wherein each said FET transistor comprises a GaAs MESFET.

21. The mixer of claim 1, wherein said mixer is operated as an up-frequency converter, and said input signal is applied to the IF port and the output signal is extracted from the RF port.

22. The mixer of claim 1, wherein said mixer is operated as an down- frequency converter, and said input signal is applied to the RF port and the output signal is extracted from the IF port.

23. The mixer of claim 1, wherein said RF bandwidth is from about 1700 Mhz to about 2200 MHz.

24. The mixer of claim 1 , wherein said IF bandwidth is from about 10 Mhz to about 200 MHz.

25. The mixer of claim 1, wherein said mixer further comprises a gate bias circuit for applying a bias voltage between said gate and source terminals, and a drain bias circuit for applying a drain bias voltage between said drain and source terminals, said drain bias operating in conjunction with said circuit to amplify an applied LO signal.

26. The mixer of claim 1 , and said partial cancellation of nonlinearity distortion occurs during a period of maximum distortion and is recursive with respect to each LO signal cycle.