Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
  • H01R43/00—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
  • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
  • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
  • B23K20/002—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating specially adapted for particular articles or work
  • B23K20/004—Wire welding
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
  • H01L21/4814—Conductive parts
  • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
  • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
  • H01L21/4814—Conductive parts
  • H01L21/4885—Wire-like parts or pins
  • H01L21/4889—Connection or disconnection of other leads to or from wire-like parts, e.g. wires
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
  • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
  • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
  • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/10—Bump connectors ; Manufacturing methods related thereto
• • H—ELECTRICITY
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  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/10—Bump connectors ; Manufacturing methods related thereto
  • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
  • H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
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  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
  • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
  • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
  • H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
  • H05K3/326—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor the printed circuit having integral resilient or deformable parts, e.g. tabs or parts of flexible circuits
• • C—CHEMISTRY; METALLURGY
  • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
  • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
  • C25D21/00—Processes for servicing or operating cells for electrolytic coating
  • C25D21/02—Heating or cooling
• • C—CHEMISTRY; METALLURGY
  • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
  • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
  • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
  • C25D5/60—Electroplating characterised by the structure or texture of the layers
  • C25D5/605—Surface topography of the layers, e.g. rough, dendritic or nodular layers
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  • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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  • H01L2224/161—Disposition
  • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
  • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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  • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
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  • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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Definitions

• the invention relates to making temporary, pressure connections between electronic components and, more particularly, to techniques for mounting resilient contact structures (spring contacts) to semiconductor devices.
• Individual semiconductor (integrated circuit) devices are typically produced by creating several identical devices on a semiconductor wafer, using known techniques of photolithography, deposition, and the like. Generally, these processes are intended to create a plurality of fully-functional integrated circuit devices, prior to singulating (severing) the individual dies from the semiconductor wafer.
• a wafer "tester” or “prober” may advantageously be employed to make a plurality of discrete pressure connections to a like plurality of discrete terminals (bond pads) on the dies, and provide signals (including power) to the dies.
• the semiconductor dies can be exercised (tested and burned in) , prior to singulating the dies from the wafer.
• interconnections between electronic components can be classified into the two broad categories of “relatively permanent” and “readily demountable”.
• a “relatively permanent” connection is a solder joint. Once two components are soldered to one another, a process of unsoldering must be used to separate the components. A wire bond is another example of a "relatively permanent" connection.
• An example of a "readily demountable" connection is rigid pins of one electronic component being received by resilient socket elements of another electronic component .
• the socket elements exert a contact force (pressure) on the pins in an amount sufficient to ensure a reliable electrical connection therebetween.
• a certain minimum contact force is desired to effect reliable pressure contact to electronic components (e.g., to terminals on electronic components) .
• a contact e.g., to terminals on electronic components.
• load force of approximately 15 grams (including as little as 2 grams or less and as much as 150 grams or more, per contact) may be desired to ensure that a reliable electrical connection is made to a terminal of an electronic component which may be contaminated with films on its surface, or which has corrosion or oxidation products on its surface.
• the minimum contact force required of each spring demands either that the yield strength of the spring material or that the size of the spring element are increased. As a general proposition, the higher the yield strength of a material, the more difficult it will be to work with (e.g., punch, bend, etc.) . And the desire to make springs smaller essentially rules out making them larger in cross-section.
• the requisite resiliency and/or compliance elements i.e., spring elements
• a plurality of inherently resilient contact structures are mounted to a carrier substrate, the carrier substrate is mounted to the semiconductor device, and the spring elements are connected, such as with bond wires to corresponding ones of the bond pads on the semiconductor device.
• the spring elements provide the desired resiliency, per se, without requiring other instrumentalities.
• the carrier substrate remains fixed with respect to the electronic component (e.g., semiconductor device) to which it is mounted - in other words, the carrier substrate is not resiliently mounted to the semiconductor device.
• the carrier substrate is rigid.
• spring elements are mounted to leads of leadframes, and the leadframes function as the spring contact carrier.
• the spring contacts can make reliable, temporary contact to test boards, which may be as simple and straightforward as ordinary printed circuit boards;
• the same resilient contact structures can make reliable pressure connections to circuit boards, when held in place by a spring clip, or the like; and (d) the same resilient contact structures can make reliable permanent connection to circuit boards, such as by soldering.
• spring contact elements can serve "double duty" both as temporary and as permanent connections to an electronic component, such as a semiconductor die.
• the spring contact element carriers are mounted to the semiconductor dies prior to the semiconductor dies being singulated (separated) from a semiconductor wafer.
• a plurality of pressure contacts can be made to one or more unsingulated semiconductor dies (devices) using a "simple" test board to power-up the semiconductor devices, and the like.
• a "simple" test board is a substrate having a plurality of terminals, or electrodes, as contrasted with a traditional "probe card” which is a substrate having a plurality of probe elements extending from a surface thereof.
• a simple test board is less expensive, and more readily configured than a traditional probe card.
• the same spring contact elements which are mounted to the semiconductor dies and which are used to exercise the semiconductor dies can be used to make permanent or pressure connections to the semiconductor dies after they have been singulated from the wafer.
• the spring contact elements are preferably formed as "composite interconnection elements" which are fabricated directly upon terminals of the carrier substrate.
• the "composite” (multilayer) interconnection element is fabricated by mounting an elongate core element, which may be a wire (wire stem) or a ribbon, to a terminal of the carrier substrate, shaping the core element to have a spring shape, and overcoating the core element to enhance the physical (e.g., spring) characteristics of the resulting composite interconnection element and/or to securely anchor the resulting composite interconnection element to the carrier substrate.
• composite throughout the description set forth herein, is consistent with a 'generic' meaning of the term (e.g., formed of two or more elements) , and is not to be confused with any usage of the term “composite” in other fields of endeavor, for example, as it may be applied to materials such as glass, carbon or other fibers supported in a matrix of resin or the like.
• spring shape refers to virtually any shape of an elongate element which will exhibit elastic
• This includes elongate elements shaped to have one or more bends, as well as substantially straight elongate elements.
• contact area As used herein, the terms “contact area”, “terminal”, “pad” , and the like refer to any conductive area on any electronic component to which an interconnection element is mounted or makes contact .
• the core of the composite interconnection element (spring element) is shaped after an end of the core is mounted to a terminal on the carrier substrate.
• the core element is shaped prior to mounting to an electronic component.
• the core element is mounted to or is a part of a sacrificial substrate which is not an electronic component.
• the sacrificial substrate is removed after shaping, and either before or after overcoating.
• tips having various topographies can be disposed at the contact ends of the interconnection elements. (See also Figures 11A-11F of the PARENT CASE.)
• the core is a "soft" material having a relatively low yield strength, and is overcoated with a "hard” material having a relatively high yield strength.
• a soft material such as a gold wire is attached (e.g., by wire bonding) to a bond pad of a semiconductor device and is overcoated (e.g., by electrochemical plating) with a hard material such nickel and its alloys.
• Vis-a-vis overcoating the core single and multi-layer overcoatings, "rough” overcoatings having microprotrusions (see also Figures 5C and 5D of the PARENT CASE) , and overcoatings extending the entire length of or only a portion of the length of the core, are described.
• the tip of the core may suitably be exposed for making contact to an electronic component (see also Figure 5B of the PARENT CASE) .
• the term "plating” is used as exemplary of a number of techniques for overcoating the core element. It is within the scope of this invention that the core element can be overcoated by any suitable technique including, but not limited to: various processes involving deposition of materials out of aqueous solutions; electrolytic plating; electroless plating; chemical vapor deposition (CVD) ; physical vapor deposition (PVD) ; processes causing the deposition of materials through induced disintegration of liquid or solid precursors; and the like, all of these techniques for depositing materials being generally wel l known .
• electrochemical processes are preferred, especially electrolytic plating.
• the spring element is an elongate element of a "hard” material which is inherently (i.e., without overcoating, as in the case of the aforementioned composite interconnection element) suitable to functioning as a resilient contact structure.
• a "monolithic" spring element may be overcoated, to enhance its electrical contact characteristics and/or to securely anchor (in a manner akin to the aforementioned composite interconnection elements) the spring element to a terminal upon which it is mounted.
• overcoating to anchor it is only necessary to "tack" the spring element to the terminal, such as by soldering, gluing, and piercing an end of the spring element into a soft portion of the terminal.
• a plurality of hard spring elements may be mounted to a sacrificial substrate, for subsequent transfer to electronic components.
• the core is in the form of a wire.
• the core is a flat tab (conductive metallic ribbon) , or an elongate ribbon of material.
• Soft materials such as gold, which attach easily to the metallization of semiconductor devices, generally lack sufficient resiliency to function as springs. (Such soft, metallic materials exhibit primarily plastic, rather than elastic deformation.) Other soft materials which may attach easily to semiconductor devices and possess appropriate resiliency are often electrically non-conductive, as in the case of most elastomeric materials. In either case, desired structural and electrical characteristics can be imparted to the resulting composite interconnection element by the overcoating applied over the core. The resulting composite interconnection element can be made very small, yet can exhibit appropriate contact forces.
• a plurality of such composite interconnection elements can be arranged at a fine pitch (e.g., 10 mils) , even though they have a length (e.g., 100 mils) which is much greater than the distance to a neighboring composite interconnection element (the distance between neighboring interconnection elements being termed "pitch") .
• the composite interconnection elements of the present invention exhibit superior electrical characteristics, including electrical conductivity, solderability and low contact resistance. In many cases, deflection of the interconnection element in response to applied contact forces results in a "wiping" contact, which helps ensure that a reliable contact is made.
• An additional advantage of the present invention is that connections made with the interconnection elements of the present invention are readily demountable. Soldering, to effect the interconnection to a terminal of an electronic component is optional, but is generally not preferred at a system level.
• interconnection elements having controlled impedance are described. These techniques generally involve coating (e.g., electrophoretically) a conductive core or an entire composite interconnection element with a dielectric material (insulating layer) , and overcoating the dielectric material with an outer layer of a conductive material. By grounding the outer conductive material layer, the resulting interconnection element can effectively be shielded, and its impedance can readily be controlled. (See also Figure 10K of the PARENT CASE.)
• interconnection elements can be pre-fabricated as individual units, for later attachment to electronic components.
• Various techniques for accomplishing this objective are set forth herein. Although not specifically covered in this document, it is deemed to be relatively straightforward to fabricate a machine that will handle the mounting of a plurality of individual interconnection elements to a substrate or, alternatively, suspending a plurality of individual interconnection elements in an elastomer, or on a support substrate.
• composite interconnection element of the present invention differs dramatically from interconnection elements of the prior art which have been coated to enhance their electrical conductivity characteristics or to enhance their resistance to corrosion.
• the overcoating of the present invention is specifically intended to substantially enhance anchoring of the interconnection element to a terminal of an electronic component and/or to impart desired resilient characteristics to the resulting composite interconnection element. In this manner, stresses (contact forces) are directed to portions of the interconnection elements which are specifically intended to absorb the stresses.
• the present invention provides essentially a new technique for making spring contacts.
• the operative structure of the resulting spring is a product of plating, rather than of bending and shaping. This opens the door to using a wide variety of materials to establish the spring shape, and a variety of "friendly" processes for attaching the "falsework" of the core to electronic components.
• the overcoating functions as a "superstructure” over the "falsework” of the core, both of which terms have their origins in the field of civil engineering.
• a distinct advantage of the present invention is that free- standing spring contacts (spring elements) can be mounted on fragile semiconductor devices without requiring additional hostile techniques, such as brazing or soldering.
• any of the resilient contact structures may be formed as at least two composite interconnection elements.
• the composite interconnection elements are all metallic, permitting burn-in to be performed at elevated temperatures and, consequently, in a shorter time.
• the composite interconnection elements are free ⁇ standing, and are generally not limited by the bond pad layout of semiconductor devices .
• the composite interconnection elements of the present invention can be fashioned to have their tips at a greater pitch (spacing) than their bases, thereby immediately (e.g., at the first level interconnect) commencing and facilitating the process of spreading pitch from semiconductor pitch (e.g., 10 mils) to wiring substrate pitch (e.g., 100 mils) .
• Figure IA is a cross-sectional view of a longitudinal portion, including one end, of an interconnection element, according to an embodiment of the invention.
• Figure IB is a cross-sectional view of a longitudinal portion, including one end, of an interconnection element, according to another embodiment of the invention.
• Figure IC is a cross-sectional view of a longitudinal portion, including one end of an interconnection element, according to another embodiment of the invention.
• Figure ID is a cross-sectional view of a longitudinal portion, including one end of an interconnection element, according to another embodiment of the invention.
• Figure IE is a cross-sectional view of a longitudinal portion, including one end of an interconnection element, according to another embodiment of the invention.
• Figure 2A is a cross-sectional view of an interconnection element mounted to a terminal of an electronic component and having a multi-layered shell, according to the invention.
• Figure 2B is a cross-sectional view of an interconnection element having a multi-layered shell, wherein an intermediate layer is of a dielectric material, according to the invention.
• Figure 2C is a perspective view of a plurality of interconnection elements mounted to an electronic component (e.g., a probe card insert) , according to the invention.
• an electronic component e.g., a probe card insert
• Figure 2D is a cross-sectional view of an exemplary first step of a technique for manufacturing interconnection elements, according to the invention.
• Figure 2E is a cross-sectional view of an exemplary further step of the technique of Figure 2D for manufacturing interconnection elements, according to the invention.
• Figure 2F is a cross-sectional view of an exemplary further step of the technique of Figure 2E for manufacturing interconnection elements, according to the invention.
• Figure 2G is a cross-sectional view of an exemplary plurality of individual interconnection elements fabricated according to the technique of Figures 2D-2F, according to the invention.
• Figure 2H is a cross-sectional view of an exemplary plurality of interconnection elements fabricated according to the technique of Figures 2D-2F, and associated in a prescribed spatial relationship with one another, according to the invention.
• Figure 21 is a cross-sectional view of an alternate embodiment for manufacturing interconnection elements, showing a one end of one element, according to the invention.
• Figure 3A is a side view of a wire having its free end bonded to a metal layer applied to a substrate, through an opening in a photoresist layer, according to the present invention.
• Figure 3B is a side view of the substrate of Figure 3A, with the wire overcoated, according to the present invention.
• Figure 3C is a side view of the substrate of Figure 3B, with the photoresist layer removed and the metal layer partially removed, according to the present invention.
• Figure 3D is a perspective view of a semiconductor device, formed according to the techniques set forth in Figures 3A-3C, according to the present invention.
• Figure 4 is a perspective view of a semiconductor device of the prior art .
• Figure 5 is a side view of a carrier substrate having spring elements mounted to a semiconductor die, according to an embodiment of the invention.
• Figure 5A is a side view of a carrier substrate having spring elements mounted to two unsingulated semiconductor dies, according to an embodiment of the invention.
• Figure 5B is a side view of a carrier substrate, of the type illustrated in Figure 5, according to an embodiment of the invention.
• Figure 6 is a side view of an alternate embodiment of a carrier substrate having spring elements mounted to a semiconductor die, according to he invention.
• Figure 6A is a side view of the carrier semiconductor assembly of Figure 6, according to the invention.
• Figure 6B is a side view of an alternate embodiment of the carrier assembly of Figure 6, according to the invention.
• Figures 7A-7F are side cross-sectional views of an alternate embodiment of the carrier substrate of the present invention.
• Figure 8A is a perspective view of an alternate embodiment of the chip-scale (chip interconnection) carrier of the present invention.
• Figure 8B is a side cross-sectional view of the chip-scale carrier of Figure 8A.
• Figure 9A is a partial, side, cross-sectional view of an embodiment of a spring carrier, according to the invention.
• Figure 9B is a partial, perspective view of an embodiment of a composite lead frame, according to the invention.
• Figure 9C is a partial, perspective view of an embodiment of a composite lead frame, according to the invention.
• Figure 10 is an exploded, side, cross-sectional view of another embodiment of a spring element carrier, according to the invention.
• Figure 11 is a perspective view of a spring element carrier mounted to a silicon (semiconductor) wafer, according to the invention.
• This patent application is directed to techniques of providing electronic components such as semiconductor devices with spring contacts, such as for testing (including exercising and performing burn-in) semiconductor devices while they are resident on a semiconductor wafer (i.e., prior to their being singulated from the wafer) and/or for effecting pressure connections between the semiconductor devices and other electronic components (such as printed circuit boards) .
• the techniques involve fabricating resilient contact structures upon carrier substrates which are attached to the semiconductor devices, making pressure connections to the resilient contact structures for testing the semiconductor devices, and using the same resilient contact structures to connect to the semiconductor die after it is singulated from the wafer.
• the resilient contact structures are implemented as "composite interconnection elements", such as have been described in the disclosure of the aforementioned U.S. Patent Application No. 08/452,255, filed 5/26/95 (“PARENT CASE”) , incorporated by reference herein.
• This patent application summarizes several of the techniques disclosed in the PARENT CASE in the discussions of Figures 1A-1E and 2A-2I.
• a "composite" interconnection element can be formed by starting with a core (which may be mounted to a terminal of an electronic component) , then overcoating the core with an appropriate material to: (1) establish the mechanical properties of the resulting composite interconnection element; and/or (2) when the interconnection element is mounted to a terminal of an electronic component, securely anchor the interconnection element to the terminal.
• a resilient interconnection element spring element
• Such a "composite" interconnection element is generally the preferred form of resilient contact structure for use in the embodiments of the present invention.
• Figures IA, IB, IC and ID illustrate, in a general manner, various shapes for composite interconnection elements, according to the present invention.
• composite interconnection elements that have a soft (readily shaped, and amenable to affixing by friendly processes to electronic components) core, overcoated by hard (springy) materials are described. It is, however, within the scope of the invention that the core can be a hard material -the overcoat serving primarily to securely anchor the interconnection element to a terminal of an electronic component.
• an electrical interconnection element 110 includes a core 112 of a "soft" material (e.g., a material having a yield strength of less than 40,000 psi) , and a shell
• the shell 114 is applied over the already-shaped core 112 by any suitable process, such as by a suitable plating process (e.g., by electrochemical plating) .
• Figure IA illustrates what is perhaps the simplest of spring shapes for an interconnection element of the present invention - namely, a straight cantilever beam oriented at an angle to a force "F" applied at its tip 110b.
• the shell 114 imparts a desired resiliency to the overall interconnection element 110.
• a resilient interconnection between electronic components can be effected between the two ends 110a and 110b of the interconnection element 110.
• the reference numeral 110a indicates an end portion of the interconnection element 110, and the actual end opposite the end 110b is not shown.
• the interconnection element 110 In contacting a terminal of an electronic component, the interconnection element 110 would be subjected to a contact force (pressure) , as indicated by the arrow labelled "F" .
• the thickness of the overcoat (whether a single layer or a multi-layer overcoat) be thicker than the diameter of the wire being overcoated.
• the overall thickness of the resulting contact structure is the sum of the thickness of the core plus twice the thickness of the overcoat, an overcoat having the same thickness as the core (e.g., 1 mil) will manifest itself, in aggregate, as having twice the thickness of the core.
• the interconnection element e.g., 110
• the interconnection element will deflect in response to an applied contact force, said deflection (resiliency) being determined in part by the overall shape of the interconnection element, in part by the dominant (greater) yield strength of the overcoating material (versus that of the core) , and in part by the thickness of the overcoating material.
• the terms “cantilever” and “cantilever beam” are used to indicate that an elongate structure (e.g., the overcoated core 112) is mounted (fixed) at one end, and the other end is free to move, typically in response to a force acting generally transverse to the longitudinal axis of the elongate element. No other specific or limiting meaning is intended to be conveyed or connoted by the use of these terms .
• an electrical interconnection element 120 similarly includes a soft core 122 (compare 112) and a hard shell 124 (compare 114) .
• the core 122 is shaped to have two bends, and thus may be considered to be S- shaped.
• a resilient interconnection between electronic components can be effected between the two ends 120a and 120b of the interconnection element 120.
• reference numeral 120a indicates an end portion of the interconnection element 120, and the actual end opposite the end 120b is not shown.
• the interconnection element 120 In contacting a terminal of an electronic component, the interconnection element 120 would be subjected to a contact force (pressure) , as indicated by the arrow labelled "F" .
• an electrical interconnection element 130 similarly includes a soft core 132 (compare 112) and a hard shell 134 (compare 114) .
• the core 132 is shaped to have one bend, and may be considered to be U-shaped.
• a resilient interconnection between electronic components can be effected between the two ends 130a and 130b of the interconnection element 130.
• the reference numeral 130a indicates an end portion of the interconnection element 130, and the actual end opposite the end 130b is not shown.
• the interconnection element 130 In contacting a terminal of an electronic component, the interconnection element 130 could be subjected to a contact force (pressure) , as indicated by the arrow labelled "F" .
• the interconnection element 130 could be employed to make contact at other than its end 130b, as indicated by the arrow labelled "F ,M .
• Figure ID illustrates another embodiment of a resilient interconnection element 140 having a soft core 142 and a hard shell 144.
• the interconnection element 140 is essentially a simple cantilever (compare Figure IA) , with a curved tip 140b, subject to a contact force "F" acting transverse to its longitudinal axis.
• Figure IE illustrates another embodiment of a resilient interconnection element 150 having a soft core 152 and a hard shell 154.
• the interconnection element 150 is generally "C-shaped", preferably with a slightly curved tip 150b, and is suitable for making a pressure contact as indicated by the arrow labelled "F".
• the soft core can readily be formed into any springable shape - in other words, a shape that will cause a resulting interconnection element to deflect resiliently in response to a force applied at its tip.
• the core could be formed into a conventional coil shape.
• a coil shape would not be preferred, due to the overall length of the interconnection element and inductances (and the like) associated therewith and the adverse effect of same on circuitry operating at high frequencies (speeds) .
• the material of the shell, or at least one layer of a multi-layer shell has a significantly higher yield strength than the material of the core. Therefore, the shell overshadows the core in establishing the mechanical characteristics (e.g., resiliency) of the resulting interconnection structure.
• Ratios of shell:core yield strengths are preferably at least 2:1, including at least 3:1 and at least 5:1, and may be as high as 10:1. It is also evident that the shell, or at least an outer layer of a multi-layer shell should be electrically conductive, notably in cases where the shell covers the end of the core. (The parent case, however, describes embodiments where the end of the core is exposed, in which case the core must be conductive.)
• Suitable materials for the core (112, 122, 132, 142) include, but are not limited to: gold, aluminum, copper,, and their alloys. These materials are typically alloyed with small amounts of other metals to obtain desired physical properties, such as with beryllium, cadmium, silicon, magnesium, and the like. It is also possible to use silver, palladium, platinum; metals or alloys such as metals of the platinum group of elements. Solder constituted from lead, tin, indium, bismuth, cadmium, antimony and their alloys can be used.
• a wire of any material e.g., gold
• any material amenable to bonding using temperature, pressure and/or ultrasonic energy to effect the bonding
• any material amenable to overcoating e.g., plating
• non-metallic material can be used for the core.
• Suitable materials for the shell include (and, as is discussed hereinbelow, for the individual layers of a multi-layer shell) , but are not limited to: nickel, and its alloys; copper, cobalt, iron, and their alloys; gold (especially hard gold) and silver, both of which exhibit excellent current-carrying capabilities and good contact resistivity characteristics; elements of the platinum group; noble metals; semi-noble metals and their alloys, particularly elements of the platinum group and their alloys; tungsten and molybdenum. In cases where a solder-like finish is desired, tin, lead, bismuth, indium and their alloys can also be used.
• Electroplating and electroless plating are generally preferred techniques. Generally, however, it would be counter-intuitive to plate over a gold core. According to an aspect of the invention, when plating (especially electroless plating) a nickel shell over a gold core, it is desirable to first apply a thin copper initiation layer over the gold wire stem, in order to facilitate plating initiation.
• An exemplary interconnection element such as is illustrated in Figures 1A-1E may have a core diameter of approximately 0.001 inches and a shell thickness of 0.001 inches - the interconnection element thus having an overall diameter of approximately 0.003 inches (i.e., core diameter plus two times the shell thickness) .
• this thickness of the shell will be on the order of 0.2 - 5.0 (one-fifth to five) times the thickness (e.g., diameter) of the core.
• the resulting composite interconnection element exhibits a spring constant (k) of approximately 3-5 grams/mil. In use, 3-5 mils of deflection will result in a contact force of 9-25 grams. This example is useful in the context of a spring element for an interposer.
• the resulting composite interconnection element exhibits a spring constant (k) of approximately 3 grams/mil, and is useful in the context of a spring element for a probe.
• the resulting composite interconnection element exhibits a spring constant (k) of approximately 2-3 grams/mil, and is useful in the context of a spring element for mounting on a semiconductor device.
• the core need not have a round cross-section, but may rather be a flat tab (having a rectangular cross-section) extending from a sheet. It should be understood that, as used herein, the term “tab” is not to be confused with the term “TAB” (Tape Automated Bonding) .
• Figure 2A illustrates an embodiment 200 of an interconnection element 210 mounted to an electronic component 212 which is provided with a terminal 214.
• a soft (e.g., gold) wire core 216 is bonded (attached) at one end 216a to the terminal 214, is configured to extend from the terminal and have a spring shape (compare the shape shown in Figure IB) , and is severed to have a free end 216b. Bonding, shaping and severing a wire in this manner is accomplished using wirebonding equipment. The bond at the end 216a of the core covers only a relatively small portion of the exposed surface of the terminal 214.
• a shell is disposed over the wire core 216 which, in this example, is shown as being multi-layered, having an inner layer 218 and an outer layer 220, both of which layers may suitably be applied by plating processes.
• One or more layers of the multi-layer shell is (are) formed of a hard material (such as nickel and its alloys) to impart a desired resiliency to the interconnection element 210.
• the outer layer 220 may be of a hard material
• the inner layer may be of a material that acts as a buffer or barrier layer
• the inner layer 218 may be the hard material
• the outer layer 220 may be a material (such as soft gold) that exhibits superior electrical characteristics, including electrical conductivity and solderability.
• the outer layer of the interconnection element may be lead-tin solder or gold-tin braze material, respectively.
• Figure 2A illustrates, in a general manner, another key feature of the invention - namely, that resilient interconnection element can be securely anchored to a terminal on an electronic component.
• the attached end 210a of the interconnection element will be subject to significant mechanical stress, as a result of a compressive force (arrow "F") applied to the free end 210b of the interconnection element.
• the overcoat (218, 220) covers not only the core 216, but also the entire remaining (i.e., other than the bond 216a) exposed surface of the terminal 214 adjacent the core 216 in a continuous (non-interrupted) manner.
• the overcoat material cover at least a portion of the terminal adjacent the core. It is generally preferred, however, that the overcoat material cover the entire remaining surface of the terminal.
• each layer of the shell is metallic.
• the relatively small area at which the core is attached (e.g., bonded) to the terminal is not well suited to accommodating stresses resulting from contact forces ("F") imposed on the resulting composite interconnection element.
• F contact forces
• the shell covering the entire exposed surface of the terminal other than in the relatively small area comprising the attachment of the core end 216a to the terminal
• the overall interconnection structure is firmly anchored to the terminal.
• the adhesion strength, and ability to react contact forces, of the overcoat will far exceed that of the core end (216a) itself.
• the term "electronic component” includes, but is not limited to: interconnect and interposer substrates; semiconductor wafers and dies, made of any suitable semiconducting material such as silicon (Si) or galliu - arsenide (GaAs) ; production interconnect sockets; test sockets; sacrificial members, elements and substrates, as described in the parent case; semiconductor packages, including ceramic and plastic packages, and chip carriers; and connectors.
• the interconnection element of the present invention is particularly well suited for use as:
• interconnection elements extending as probes from substrates (described in greater detail hereinbelow) for testing electronic components
• the interconnection element of the present invention is unique in that it benefits from the mechanical characteristics (e.g., high yield strength) of a hard material without being limited by the attendant typically poor bonding characteristic of hard materials. As elaborated upon in the parent case, this is made possible largely by the fact that the shell (overcoat) functions as a "superstructure" over the "falsework" of the core, two terms which are borrowed from the milieu of civil engineering. This is very different from plated interconnection elements of the prior art wherein the plating is used as a protective (e.g., anti-corrosive) coating, and is generally incapable of imparting the desired mechanical characteristic to the interconnection structure. And this is certainly in marked contrast to any non-metallic, anticorrosive coatings, such as benzotriazole (BTA) applied to electrical interconnects.
• BTA benzotriazole
• both the electrical and mechanical (e.g., plastic and elastic) characteristics of an interconnection element formed according to the invention are readily tailored for particular applications. For example, it may be desirable in a given application that the interconnection elements exhibit both plastic and elastic deformation. (Plastic deformation may be desired to accommodate gross non-planarities in components being interconnected by the interconnection elements.) When elastic behavior is desired, it is necessary that the interconnection element generate a threshold minimum amount of contact force to effect a reliable contact. It is also advantageous that the tip of the interconnection element makes a wiping contact with a terminal of an electronic component, due to the occasional presence of contaminant films on the contacting surfaces.
• the term "resilient”, as applied to contact structures, implies contact structures (interconnection elements) that exhibit primarily elastic behavior in response to an applied load (contact force)
• the term “compliant” implies contact structures (interconnection elements) that exhibit both elastic and plastic behavior in response to an applied load (contact force)
• a "compliant" contact structure is a "resilient” contact structure.
• the composite interconnection elements of the present invention are a special case of either compliant or resilient contact structures .
• a number of features are elaborated upon in detail, in the parent case, including, but not limited to: fabricating the interconnection elements on sacrificial substrates; gang- transferring a plurality of interconnection elements to an electronic component; providing the interconnection elements with contact tips, preferably with a rough surface finish; employing the interconnection elements on an electronic component to make temporary, then permanent connections to the electronic component; arranging the interconnection elements to have different spacing at their one ends than at their opposite ends,- fabricating spring clips and alignment pins in the same process steps as fabricating the interconnection elements; employing the interconnection elements to accommodate differences in thermal expansion between connected components; eliminating the need for discrete semiconductor packages (such as for SIMMs) ; and optionally soldering resilient interconnection elements (resilient contact structures) .
• Figure 2B shows a composite interconnection element 220 having multiple layers.
• An innermost portion (inner elongate conductive element) 222 of the interconnection element 220 is either an uncoated core or a core which has been overcoated, as described hereinabove.
• the tip 222b of the innermost portion 222 is masked with a suitable masking material (not shown) .
• a dielectric layer 224 is applied over the innermost portion 222 such as by an electrophoretic process.
• An outer layer 226 of a conductive material is applied over the dielectric layer 224.
• An exemplary material for the dielectric layer 224 is a polymeric material, applied in any suitable manner and to any suitable thickness (e.g., 0.1 - 3.0 mils) .
• the outer layer 226 may be multi-layer.
• at least one layer of the outer layer 226 is a spring material, when it is desired that the overall interconnection element exhibit resilience.
• FIG. 2C illustrates an embodiment 250 wherein a plurality (six of many shown) of interconnection elements 251..256 are mounted on a surface of an electronic component 260, such as a probe card insert (a subassembly mounted in a conventional manner to a probe card) . Terminals and conductive traces of the probe card insert are omitted from this view, for illustrative clarity.
• the attached ends 251a..256a of the interconnection elements 251..256 originate at a first pitch (spacing) , such as 0.050 - 0.100 inches.
• the interconnection elements 251..256 are shaped and/or oriented so that their free ends (tips) are at a second, finer pitch, such as 0.005 - 0.010 inches.
• An interconnect assembly which makes interconnections from a one pitch to another pitch is typically referred to as a "space transformer" .
• the tips 251b..256b of the interconnection elements are arranged in two parallel rows, such as for making contact to (for testing and/or burning in) a semiconductor device having two parallel rows of bond pads (contact points) .
• the interconnection elements can be arranged to have other tip patterns, for making contact to electronic components having other contact point patterns, such as arrays.
• the invention is applicable to fabricating a plurality of interconnection components and arranging the plurality of interconnection elements in a prescribed spatial relationship with one another, such as in a peripheral pattern or in a rectangular array pattern.
• interconnection elements directly to terminals of electronic components has been discussed hereinabove.
• the interconnection elements of the present invention can be fabricated upon, or mounted to, any suitable surface of any suitable substrate, including sacrificial substrates.
• PARENT CASE describes, for example with respect to Figures 11A-11F fabricating a plurality of interconnection structures (e.g., resilient contact structures) as separate and distinct structures for subsequent mounting to electronic components, and which describes with respect to Figures 12A-12C mounting a plurality of interconnection elements to a sacrificial substrate (carrier) then transferring the plurality of interconnection elements en masse to an electronic component.
• interconnection structures e.g., resilient contact structures
• Figures 12A-12C mounting a plurality of interconnection elements to a sacrificial substrate (carrier) then transferring the plurality of interconnection elements en masse to an electronic component.
• Figures 2D-2F illustrate a technique for fabricating a plurality of interconnection elements having preformed tip structures, using a sacrificial substrate.
• Figure 2D illustrates a first step of the technique 250, in which a patterned layer of masking material 252 is applied onto a surface of a sacrificial substrate 254.
• the sacrificial substrate 254 may be of thin (1-10 mil) copper or aluminum foil, by way of example, and the masking material 252 may be common photoresist.
• the masking layer 252 is patterned to have a plurality (three of many shown) of openings at locations 256a, 256b, 256c whereat it is desired to fabricate interconnection elements.
• the locations 256a, 256b and 256c are, in this sense, comparable to the terminals of an electronic component .
• the locations 256a, 256b and 256c are preferably treated at this stage to have a rough or featured surface texture. As shown, this may be accomplished mechanically with an embossing tool 257 forming depressions in the foil 254 at the locations 256a, 256b and 256c. Alternatively, the surface of the foil at these locations can be chemically etched to have a surface texture. Any technique suitable for effecting this general purpose is within the scope of this invention, for example sand blasting, peening and the like.
• a plurality (one of many shown) of conductive tip structures 258 are formed at each location (e.g., 256b) , as illustrated by Figure 2E.
• This may be accomplished using any suitable technique, such as electroplating, and may include tip structures having multiple layers of material.
• the tip structure 258 may have a thin (e.g., 10 - 100 microinch) barrier layer of nickel applied onto the sacrificial substrate, followed by a thin (e.g., 10 microinch) layer of soft gold, followed by a thin (e.g., 20 microinch) layer of hard gold, followed by a relatively thick (e.g., 200 microinch) layer of nickel, followed by a final thin (e.g., 100 microinch) layer of soft gold.
• the first thin barrier layer of nickel is provided to protect the subsequent layer of gold from being “poisoned" by the material (e.g., aluminum, copper) of the substrate 254, the relatively thick layer of nickel is to provide strength to the tip structure, and the final thin layer of soft gold provides a surface which is readily bonded to.
• the invention is not limited to any particulars of how the tip structures are formed on the sacrificial substrate, as these particulars would inevitably vary from application-to- application.
• a plurality (one of many shown) of cores 260 for interconnection elements may be formed on the tip structures 258, such as by any of the techniques of bonding a soft wire core to a terminal of an electronic component described hereinabove.
• the cores 260 are then overcoated with a preferably hard material 262 in the manner described hereinabove, and the masking material 252 is then removed, resulting in a plurality (three of many shown) of free ⁇ standing interconnection elements 264 mounted to a surface of the sacrificial substrate, as illustrated by Figure 2F.
• the overcoat material 262 firmly anchors the cores 260 to their respective tip structures 258 and, if desired, imparts resilient characteristics to the resulting interconnection elements 264.
• the plurality of interconnection elements mounted to the sacrificial substrate may be gang-transferred to terminals of an electronic component. Alternatively, two widely divergent paths may be taken.
• a silicon wafer can be used as the sacrificial substrate upon which tip structures are fabricated, and that tip structures so fabricated may be joined (e.g., soldered, brazed) to resilient contact structures which already have been mounted to an electronic component .
• the sacrificial substrate 254 may simply be removed, by any suitable process such as selective chemical etching. Since most selective chemical etching processes will etch one material at a much greater rate than an other material, and the other material may slightly be etched in the process, this phenomenon is advantageously employed to remove the thin barrier layer of nickel in the tip structure contemporaneously with removing the sacrificial substrate.
• the thin nickel barrier layer can be removed in a subsequent etch step. This results in a plurality
• the overcoat material may also be slightly thinned in the process of removing the sacrificial substrate and/or the thin barrier layer. However, it is preferred that this not occur.
• Such an outer layer of gold is intended primarily for its superior conductivity, contact resistance, and solderability, and is generally highly impervious to most etching solutions contemplated to be used to remove the thin barrier layer and the sacrificial substrate.
• the plurality (three of many shown) of interconnection elements 264 may be "fixed" in a desired spatial relationship with one another by any suitable support structure 266, such as by a thin plate having a plurality of holes therein, whereupon the sacrificial substrate is removed.
• the support structure 266 may be of a dielectric material, or of a conductive material overcoated with a dielectric material. Further processing steps (not illustrated) such as mounting the plurality of interconnection elements to an electronic component such as a silicon wafer or a printed circuit board may then proceed.
• tip structures (258) may be formed of virtually any desired material and having virtually any desired texture.
• gold is an example of a noble metal that exhibits excellent electrical characteristics of electrical conductivity, low contact resistance, solderability, and resistance to corrosion. Since gold is also malleable, it is extremely well-suited to be a final overcoat applied over any of the interconnection elements described herein, particularly the resilient interconnection elements described herein. Other noble metals exhibit similar desirable characteristics. However, certain materials such as rhodium which exhibit such excellent electrical characteristics would generally be inappropriate for overcoating an entire interconnection element. Rhodium, for example, is notably brittle, and may not perform well as a final overcoat on a resilient interconnection element.
• the first layer of a multi-layer tip structure can be rhodium (rather than gold, as described hereinabove) , thereby exploiting its superior electrical characteristics for making contact to electronic components without having any impact whatsoever on the mechanical behavior of the resulting interconnection element.
• Figure 21 illustrates an alternate embodiment 270 for fabricating interconnection elements.
• a masking material 272 is applied to the surface of a sacrificial substrate 274, and is patterned to have a plurality (one of many shown) of openings 276, in a manner similar to the technique described hereinabove with respect to Figure 2D.
• the openings 276 define areas whereat interconnection elements will be fabricated as free-standing structures.
• the area within the opening may be textured, in any suitable manner, such as to have one or more depressions, as indicated by the single depression 278 extending into the surface of the sacrificial substrate 274.
• a core (wire stem) 280 is bonded to the surface of the sacrificial substrate within the opening 276, and may have any suitable shape. In this illustration, only a one end of one interconnection element is shown, for illustrative clarity. The other end (not shown) may be attached to an electronic component. It may now readily be observed that the technique 270 differs from the aforementioned technique 250 in that the core 280 is bonded directly to the sacrificial substrate 274, rather than to a tip structure 258.
• a gold wire core (280) is readily bonded, using conventional wirebonding techniques, to the surface of an aluminum substrate (274) .
• a layer 282 of gold is applied (e.g., by plating) over the core 280 and onto the exposed area of the substrate 274 within the opening 276, including within the depression 278.
• the primary purpose of this layer 282 is to form a contact surface at the end of the resulting interconnection element (i.e., once the sacrificial substrate is removed) .
• a relatively hard material such as nickel
• one primary purpose of this layer 284 is to impart desired mechanical characteristics (e.g., resiliency) to the resulting composite interconnection element.
• another primary purpose of the layer 284 is to enhance the durability of the contact surface being fabricated at the lower (as viewed) end of the resulting interconnection element.
• a final layer of gold (not shown) may be applied over the layer 284, to enhance the electrical characteristics of the resulting interconnection element.
• the masking material 272 and sacrificial substrate 274 are removed, resulting in either a plurality of singulated interconnection elements (compare Figure 2G) or in a plurality of interconnection elements having a predetermined spatial relationship with one another (compare Figure 2H) .
• This embodiment 270 is exemplary of a technique for fabricating textured contact tips on the ends of interconnection elements. In this case, an excellent example of a "gold over nickel" contact tip has been described. It is, however, within the scope of the invention that other analogous contact tips could be fabricated at the ends of interconnection elements, according to the techniques described herein. Another feature of this embodiment 270 is that the contact tips are constructed entirely atop the sacrificial substrate (274) , rather than within the surface of the sacrificial substrate (254) as contemplated by the previous embodiment 250.
• Figures 3A, 3B, and 3C are comparable to Figures 1C-1E of the PARENT CASE, and illustrate a technique 300 for fabricating composite interconnections directly upon semiconductor devices, including unsingulated semiconductor devices. This technique is comparable to a technique disclosed in the aforementioned commonly-owned, copending U.S. Patent Application No. 08/558,332.
• a semiconductor device 302 has a patterned conductive layer 304.
• This layer 304 may be a top metal layer, which is normally intended for bond-out to the die, as defined by openings 306 in an insulating (e.g., passivation) layer 308
• a bond pad (typically nitride) .
• a bond pad would be defined which would have an area corresponding to the area of the opening 306 in the passivation layer 308.
• a wire would be bonded to the bond pad.
• a blanket layer 310 of metal material e.g., aluminum
• metal material e.g., aluminum
• a patterned layer 312 of masking material e.g., photoresist
• a patterned layer 312 of masking material is applied over the layer 310 with openings 314 aligned over the openings 306 in the passivation layer 308.
• Portions of the blanket conductive layer 310 are covered by the masking material 312, other portions of the blanket conductive layer 310 are exposed (not covered) within the openings 314 of the layer of masking material 312.
• the exposed portions of the blanket conductive layer 310, within the openings 314 will serve as "pads" or “terminals” (compare 214) , and may be gold plated (not shown) .
• the opening 314 is larger than the opening 306. As will be evident, this will result in a larger bond area (defined by the opening 132) than is otherwise (as defined by the opening 306) present on the semiconductor die 302.
• the conductive layer 310 acts as a shorting layer to protect the device 302 from damage during a process of electronic flame off (EFO) of the wire stem (core) 320.
• EFO electronic flame off
• An end 320a of an inner core (wire stem) 320 is bonded to the top (as viewed) surface of the conductive layer 310, within the opening 314.
• the core 320 is configured to extend from the surface of the semiconductor die, to have a springable shape and is severed to have a tip 320b, in the manner described hereinabove (e.g., by electronic flame off) .
• the shaped wire stem 320 is overcoated with one or more layers of conductive material 322, as described hereinabove
• the overcoat material 322 completely envelops the wire stem 320 and also covers the conductive layer 310 within the area defined by the opening 314 in the photoresist 312.
• the photoresist 312 is then removed (such as by chemical etching, or washing) , and the substrate is subjected to selective etching (e.g., chemical etching) to remove all of the material from the conductive layer 310 except that portion 315 (e.g., pad, terminal) of the layer 310 which is covered by the material 322 overcoating the wire stem 320.
• Another important advantage of this technique is that a hermetically-sealed (completely overcoated) connection is effected between the contact structure 324 and the terminal (pad) 315 to which it is mounted.
• the composite interconnection elements of the present invention are readily mounted to (or fabricated upon) a substrate (particularly a semiconductor die) in a manner in which the tips (e.g., 320b) of the interconnection elements
• terminals e.g., bond pads
• openings are made in the resist (e.g., 314) whereat resilient contact structures are not mounted. Rather, such openings could advantageously be employed to effect connections (such as by traditional wirebonding) to other pads on the same semiconductor die or on other semiconductor dies. This affords the manufacturer the ability to "customize" interconnections with a common layout of openings in the resist.
• the masking layer 312 can additionally be patterned, so as to leave additional conductive lines or areas upon the face of the semiconductor device 302 (i.e., in addition to providing openings 314 whereat the interconnection elements 324 are mounted and overcoated) .
• This is illustrated in the figure by the "elongate" openings 324a and 324b extending to the openings 314a and 314b, respectively, and the "area" opening 324c optionally (as shown) extending to the opening 314c.
• elements 304, 308 and 310 are omitted, for illustrative clarity.
• the overcoat material 322 will be deposited in these additional openings
• elongated areas 324a and 324b which when plated, become lines
• the elongated areas 324a and 324b which can serve as on-chip (302) capacitors.
• providing openings in the masking layer 312 at other than the locations of the contact structures 324 can help uniformize deposition of the subsequent overcoat material 322.
• the contact structures (324) are pre-fabricated, for example in the manner of Figures 2D-2F described hereinabove, and brazed to the terminals 315, either with or without tips (258) having controlled topography.
• the topography of a tip structure (258) can be controlled to be flat, to make an effective pressure connection with a z-axis conductive adhesive (868) , such as is described in the PARENT CASE and in commonly-owned, copending U.S. Patent Application No. (attorney docket 95-554) , filed 11/15/95.
• Modern integrated circuits are generally produced by creating several, typically identical integrated circuit dies
• “Burn-in” is a process whereby a chip (die) is either simply powered up (“static” burn-in) , or is powered up and has signals exercising to some degree the functionality of the chip
• Burn-in is usually performed on a die-by-die basis, after the dies are singulated (diced) from the wafer, but it is also known to perform burn-in prior to singulating the dies.
• the temporary connections to the dies are made by test probes.
• Functional testing can also be accomplished by making temporary connections to the dies.
• each die is provided with built-in self test (self-starting, signal-generating) circuitry which will exercise some of the functionality of the chip.
• a test jig must be fabricated for each die, with probe pins precisely aligned with bond pads on the particular die required to be exercised (tested and/or burned-in) . These test jigs are relatively expensive, and require an inordinate amount of time to fabricate.
• Burn-in boards are expensive, which increases the overall cost of fabrication and which can only be amortized over large runs of particular devices.
• packaging typically involves making some sort of "permanent" connection to the die, such as by bond wires. (Often, such "permanent" connections may be un-done and re-done, although this is not generally desirable.)
• Figure 4 illustrates a semiconductor device 400 which comprises a semiconductor die 402 having a plurality of bond pads (terminals) 404 arranged in a row along a centerline of the die 402. (In this, and in subsequent, illustrations, bond pads are shown in a "stylized" manner as being atop the surface of a semiconductor die.) For example, there may be in excess of one hundred such bond pads arranged at a 5 mil pitch.
• the semiconductor device 400 is exemplary of a 64-megabit memory device. As is known, connections to the device 400 can be made with an LOC (lead on chip) leadframe 410 having a plurality of leadframe fingers 412 extending across the top surface 402a of the die 402 towards respective ones of the bond pads 404.
• LOC lead on chip
• the leadframe fingers 412 are connected to respective ones of the bond pads 404 by bond wires 414.
• bond wires 414 there are redundancy openings (not shown) , or windows, in the passivation layer (not shown) through which the top metallization layer of the semiconductor device is exposed, to permit reconfiguring certain connections internal to the device in order to make otherwise non-functional devices functional.
• a plurality of resilient contact structures are mounted to a rigid carrier substrate, the carrier substrate is mounted to the semiconductor device, and the spring elements are electrically connected to corresponding ones of the bond pads on the semiconductor device.
• Figure 5 is a side view of semiconductor device assembly
• Figures 16E and 16F are side views of a technique for fabricating resilient contact structures in a manner suitable for stacking chips (semiconductor dies) , one atop another, according to the present invention.
• Figures 16E and 16F illustrate a technique 1650 for fabricating resilient contact structures in a manner suitable for stacking chips (semiconductor dies) , one atop another.
• a sacrificial structure 1652 (compare 1602) is disposed atop a first electronic component 1662 (compare 1612) .
• a wire 1658 is bonded at one end 1658a to a pad 1664 on the first electronic component 1662, is configured to have a springable shape (in a manner similar to that of Figure 16A) , and an intermediate portion 1658c of the wire 1658 is bonded to the sacrificial structure 1652 (without severing) .
• the sacrificial structure 1652 may be provided with a contact tip 1654 (compare 1026 of Figure IOC) to which the intermediate portion of the wire is bonded.
• the wire is further shaped to extend from the sacrificial structure 1652 in a springable shape (e.g., compare the S-shape of Figure 2E) , and is severed to have a free end 1658b.
• TtB shaped wire stem may be plated either prior to (compare Figure 16B) or after (compare Figure 16D) removing the sacrificial structure 1652 to become a resilient contact structure, and may have a topological contact (compare 1026) applied to its free end 1658b.
• a second electronic component 1672 is disposed between the first electronic component 1662 and the intermediate portions 1658c of the resilient contact structures (overcoated wire stems) to effect interconnections between the first electronic component 1662 and terminals 1674 of the second electronic component 1672.
• An advantage of this technique is that the interconnects (overcoated portion of the wire stem between 1658c and 1658b) also extend from the second electronic component 1672, for making connections to external systems (other electronic components) .
• the first electronic component 1662 is a microprocessor
• the second electronic component 1672 is a memory device.
• the semiconductor device 500 is similar to the semiconductor device 400, in that it comprises a semiconductor die 502 (compare 402) having a plurality of bond pads 504
• bond pads 504 may be arranged in a single row down a centerline of the semiconductor die 502.
• a rigid carrier substrate 510 is mounted, using any suitable adhesive (not shown) to the face 502a of the die 502, on an area of the die not occupied by bond pads 504.
• the carrier substrate 510 is formed of any suitable, rigid material, such as ceramic, silicon, PCB material (such as Kevlar (tm) , FR4, or the like) , or metal having an insulating coating.
• the carrier substrate may also be formed of a polymer.
• the adhesive is any suitable adhesive such as thermoplastic or cyanide-ester. It is not required that the adhesive be resilient, or that it allow the carrier substrate 510 to be compressed towards the semiconductor die 502. However, in the case of carrier substrates having a substantially different coefficient of thermal expansion than that of the semiconductor die, it is advantageous to select an adhesive that will accommodate (such as by low shear strength) such differences in coefficients of thermal expansion.
• the adhesives contemplated to be used to adhere the carrier (e.g., 510) to the substrate (e.g., 502) are suitably thermoplastic, cyanide-ester, epoxy, silicone, or flexible epoxy.
• the term “rigid”, as applied to the carrier (e.g., 510) denotes that the carrier need not be resilient, and is preferably rigid per se .
• the term “rigid carrier” also applies to a flexible carrier that is adhered to a rigid substrate (e.g., 502) without intervening means for permitting/encouraging the carrier to flex. In this latter case, the mounted carrier would be reinforced (rigidized, in use) by the underlying rigid substrate (e.g., 502) .
• a plurality of resilient contact structures (spring elements) 512 are mounted to corresponding ones of a first plurality of terminals 514 on the top (as viewed) surface 510a of the carrier substrate 510.
• a second plurality of terminals 516 are also provided on the top surface 510a of the carrier substrate 510, and are connected to corresponding ones of the first plurality of terminals 512 by conductive lines 518.
• the carrier substrate 510 is thus recognizable as a type of wiring substrate, wherein the terminals 514, the terminals 516 and the lines 518 can all be patterned from a single conductive layer.
• the resilient contact structures (spring elements) 512 are mounted to the terminals 514 in any suitable manner and to have any desired resilient/compliant characteristics, such as has been described hereinabove (e.g., compare Figure 2A) .
• the resilient contact structures (spring elements) 512 are connected to corresponding ones of the bond pads 504 by bond wires 520 extending between the bond pads 504 and the terminals 516.
• the carrier substrate, with spring contacts fabricated thereupon can be prefabricated for later mounting to semiconductor dies. Additionally, engineering changes in the layout and interconnection of the terminals on the carrier substrate are readily effected prior to mounting the carrier substrate to the semiconductor die.
• the rigid carrier substrate can be located anywhere on the die other than atop the bond pads. If there are redundancy openings (windows) in the passivation layer of the die, the rigid carrier substrate may be designed and disposed so that it does not overlie the redundancy windows, and can readily be fabricated to avoid such "conflicts", but this is not absolutely necessary. For example, if the die has already been probed (tested) , and the necessary modifications thereto made through the exposed redundancy windows (e.g., by "fusing" wiring layers of the die, for re-routing signals) , it is acceptable that the carrier overlie the already-used redundancy windows. Generally, the carrier can overlie the redundancy windows if they are no longer needed.
• the carrier substrate e.g., 510
• the spring elements e.g., 512
• the semiconductor die e.g., 502
• the spring elements extend away from the front surface (e.g., 502a) of the semiconductor die. This forms what can be termed a "semiconductor assembly".
• Figure 5A illustrates two of a plurality of semiconductor dies 532 and 534, adjacent one another, which have not been singulated (separated) from a semiconductor wafer.
• Each die 532 and 534 (compare 502) is provided with a plurality of bond pads 536 and 538 (compare 504) , respectively.
• a single rigid carrier substrate 540 (compare 510) is disposed atop both of the adjacent semiconductor dies 532 and 534, so as to "bridge" (span) the at least two unsingulated semiconductor dies. In other words, the rigid carrier substrate 540 hangs over the edge of either one of the two dies.
• resilient contact structures (spring elements) 542 and 544 are mounted to first pluralities of terminals 546 and 548 (compare 514) , and the terminals 546 and 548 are connected via pluralities of conductive lines 550 and 552 (compare 518) , respectively, to second pluralities of terminals 554 and 556
• each semiconductor die is provided with a plurality of spring elements (542, 546) connected to its bond pads (536, 538) , said spring elements extending upwards (as viewed) from the surface of the dies.
• This can be done with all of the dies on a wafer, or with a selected portion of the dies on the wafer.
• only one carrier substrate will be required for every two unsingulated dies on the wafer, in the event that the unsingulated dies have central rows of pads.
• a single rigid carrier substrate could span any number of adjacent unsingulated dies on a wafer (i.e., by being disposed at the intersection of the four unsingulated dies) .
• it would be preferred to "pick and place" one carrier per die (on a wafer) or to mount one single very large carrier to the entire wafer of unsingulated dies. This is generally the case for all of the carrier embodiments disclosed herein.
• a suitable mechanism e.g., wafer saw, laser, etc. can be used to slice along the line 570, between the adjacent unsingulated dies.
• the mounting of resilient contact structures to unsingulated dies provides a technique for testing (exercising and/or burning-in) semiconductor dies, prior to their being singulated (separated) from a semiconductor wafer, without being constrained by the arrangement of dies or the layout of bond pads on the dies, with the requisite resiliency and/or compliance being resident on the semiconductor dies, rather than requiring the probe cards to be provided with resilient contact structures extending therefrom, and permits using the same resilient contact structures for final packaging of the semiconductor devices.
• a plurality of pressure contacts can be made to one or more unsingulated semiconductor dies (devices) using a "simple" test board to power-up the semiconductor devices, and the like.
• a "simple" test board would be a substrate having a plurality of terminals,or electrodes, as contrasted with a traditional "probe card” which is a substrate having a plurality of probe elements extending from a surface thereof.
• a simple test board is less expensive, and more readily configured than a traditional probe card.
• Figure 5B illustrates a feature 580 of the invention, wherein the carrier of Figure 5 is mounted in the aforementioned manner to an electronic component 502 (e.g., a semiconductor die) and, in a final step is encapsulated with an encapsulant
• an electronic component 502 e.g., a semiconductor die
• This technique 580 can be performed either before semiconductor dies are singulated from a semiconductor wafer, or after the are singulated.
• Figure 6 illustrates an alternate technique 600 for providing semiconductor dies with spring elements, and is applicable to either unsingulated dies or to singulated dies.
• a rigid carrier substrate 610 (compare 510 or 540) is mounted (with a suitable adhesive, as described hereinabove) to a surface 602a of a semiconductor die 602.
• the semiconductor die 602 has a plurality of bond pads 604 disposed on its surface 602a, and the rigid carrier substrate 610 has a corresponding plurality of terminals 612 disposed on its top (as viewed) surface) .
• a bond wire 618 is bonded to the bond pad, is extended, and is bonded to a corresponding terminal 612, without severing the bond wire 618.
• the bond wire 618 is further extended (as portion 620 of the bond wire) to extend from the surface of the carrier substrate 610, and is shaped and severed in the manner described hereinabove (compare Figure 2A) .
• This provides a free-standing wire stem 620 having a spring shape and a tip 620a.
• the wire stem 620 is contiguous with the bond wire 618 (i.e., it is one continuous wire which has been bonded at a midportion thereof to the terminal 612) .
• the assembly i.e., of die 602, carrier substrate 610 and bond wire 618, can readily be overcoated with a material 622.
• the masking material 630 may be left in place, or may be removed after overcoating.
• Figure 6B illustrates an alternate embodiment 650 of the carrier assembly of Figure 6.
• this embodiment :
• a layer of encapsulant 682 is applied over the masking material 680 to stabilize the bottom portion (base) of the resulting composite interconnection element (670/672, compare 620/622) - in other words, to "fix” the joint between the wire stem and the carrier 660 (compare 610) .
• a suitable amount of encapsulant 682 is applied to cover the base of the composite interconnection (spring) element, while leaving the a substantial portion (including the tip) of the resulting composite interconnection (spring) element exposed.
• Figures 7A-7F illustrate an alternate technique 700 for fabricating and for employing the spring element carriers of the present invention.
• Figure 7A illustrates a leadframe having a plurality (one of many shown) of leadframe fingers 702. Each finger 702 has an inner end 702a.
• Masking material 704, such as photoresist 704 is applied to the outer portions of both sides (top and bottom, as viewed) of the leadframe fingers 702, leaving inner portions of the leadframe fingers unmasked.
• Figure 7B illustrates that a core element (wire stem) 706 is bonded to the exposed inner portion of the leadframe finger 702, and is shaped to have a springable shape, in a manner akin to the above-described techniques of mounting wire stems to terminals of electronic components (compare core 216, Figure 2A) .
• the leadframe with shaped core element mounted thereto is overcoated with a suitable conductive metallic material 708, such as nickel, in a manner such as is described hereinabove.
• a suitable conductive metallic material 708 such as nickel
• the masking material 704 is removed, and a film 712 of an adhesive material such as adhesive tape or double-sided polyimide with adhesive is mounted to the underside (as viewed) of the leadframe fingers 702.
• the entire structure can then be encapsulated, such as with epoxy, which extends upward (as viewed) to the bases of the springs 710.
• Figure 7E illustrates a complete leadframe having two sets (700 and 700a) of leadframe fingers directed inward, towards one another, and a central opening 720 therebetween.
• spring elements need not be composite interconnection elements
• the carrier is suitably mounted by the adhesive film 712 to a front surface of an electronic component 730 having a plurality of terminals 732, and each terminal is wire bonded to a respective one of the leadframe fingers 702 by a bond wire 734.
• the outer portions of the leadframe fingers 702 - namely, those portions which were masked (704) and which did not become overcoated, can be etched away, or removed in any suitable manner.
• the adhesive layer 712 covers the entire front (top, as viewed in Figure 7E) surface of the electronic component
• the chip- scale carrier can be mounted to unsingulated semiconductor dies on a semiconductor wafer either before of after the semiconductor dies are tested and burned-in.
• the leadframe fingers (702) are initially tied to one another by a frame, similar to conventional leadframes, said frame being removed (such as by stamping away) after the chip-scale carrier is mounted to a semiconductor die.
• This has the advantage that standard leadframe processing equipment can be employed to handle the chip-scale carriers of the present invention.
• the component e.g., 730
• the component would be picked and placed onto the leadframe, wire bonded (734) thereto, and encapsulated, prior to removing said leadframe frame (if any) .
• FIG. 8A illustrates an embodiment of a chip-scale carrier 800 according to the invention.
• An electronic component 802 such as a semiconductor device has a plurality (two of many shown) of terminals 804 and 805 within openings 806 and 807, respectively, in an insulating layer 808 on the front (top, as viewed) surface of the component 802.
• a carrier substrate 810 (compare 510) is provided upon which spring elements (composite interconnection elements, resilient contact structures) are fabricated and from which bond wire connections to the terminals of the electronic component may be made.
• the substrate 810 is a multi-layer substrate, including an insulating layer 812, a patterned conductive layer 814 disposed atop the insulating layer 812, another insulating layer 816 disposed atop the conductive layer 814 and another patterned conductive layer 818 atop the insulating layer 816.
• the insulating layer 816 is disposed generally centrally upon the first conductive layer and is sized to permit two end portions of each of the individual conductive lines of the first conductive layer to be exposed, at corresponding two side edges of the second insulating layer.
• the alternating sequence of insulating and conductive layers can be repeated to form a multi-layer substrate having three or more layers.
• the conductive layer 814 is patterned to have a plurality
• the conductive layer 818 is patterned to have a plurality (one of many shown) of conductive lines extending from a one (left, as viewed) side edge of the insulating layer 816 to an opposite (right, as viewed) side edge of the insulating layer 816.
• the insulating layer 812 is bigger than the insulating layer 816, and the insulating layer 816 is disposed atop a midportion of the conductive layer 814 so the ends of the conductive lines (814) are exposed.
• a core element (wire stem) 820 is bonded to one exposed end (end portion) of the conductive line(s) 814, and a core element (wire stem) 822 is bonded to one exposed end (end portion) of the conductive line(s) 818, in the manner described hereinabove as a preliminary step in the fabrication of free-standing resilient contact structures extending from the conductive lines of the substrate.
• the substrate 810 is disposed atop the insulating layer 808 of the electronic component (i.e., on the face of the electronic component) .
• the inner ends (opposite end portions) of the conductive lines 814 and 818 are connected to selected ones of the terminals 804 and 805 of the electronic component 802 with bond wires 830 and 832, respectively.
• the wire stems 820 and 822 be overcoated to impart a desired resiliency to a resulting composite interconnection element.
• the "bonding shelves" end portions of the conductive lines 814 and 818 which will be wire bonded to the terminals of the electronic component
• the wire stems can be overcoated (e.g., plated) with one or more layers of conductive material 826, and the masking material 824 may then be removed, as illustrated by Figure 8B.
• An advantage of this embodiment (800) is that the wiring on each bonding shelf goes directly to the spring element (resilient contact structure) , and there is no need for vias to be formed through the multi-layer substrate (810) . This permits very high density connections to be made to the electronic component (802) , without requiring fine conductive lines (on the substrate) , which translates to reduced cost. Moreover, the chip-scale carrier of the present invention simplifies transitions from peripheral arrays of terminals on an electronic component to area arrays of spring elements.
• the spring elements can originate on any level, but can be caused to terminate in the same plane (as indicated by the dashed line in Figure 8B) .
• the spring elements can readily be caused to terminate at the same height above the electronic component (802) .
• the substrate (810) can have any number of layers.
• a one layer can be dedicated to power, another dedicated to ground, and additional one or more layers dedicated to carrying signals to and from the electronic component .
• the substrate (810) can be affixed to the electronic component in any suitable manner, such as with an adhesive, and is readily sized to sit atop a semiconductor device without overhanging the edges of the semiconductor device.
• the bonding shelves are at other than peripheral locations on their respective layers.
• the advantages of having a multilayer, via- less carrier will accrue when a wiring layer of any level is accessible for mounting spring contacts at any selected area (i.e., other than a peripheral shelf) and for connecting to terminals of an electronic component (e.g., semiconductor die) , so long as the selected area to which the springs are mounted is accessible (not covered by an overlying layer of the multilayer carrier) .
• free ends (tips) of the spring contacts originating from the various levels (layers) of the multi-layer carrier need not all be coplanar (terminating on the same plane) .
• the spring contacts are readily fabricated so that their tips are at any desired height (z-axis) above the carrier substrate.
• the spring carriers of the present invention can be fabricated utilizing substantially conventional leadframes, to take advantage of automated equipment for mounting semiconductor dies to said leadframes.
• Figure 9A illustrates an embodiment 900 of the invention wherein a spring element 902 is mounted (in the case of composite interconnection elements, bonded and overcoated) to an inner portion of a lead 904 of a leadframe.
• An outer portion 906 of the leadframe is a frame (ring) 906.
• the lead 904 is severed at a position outward (to the right, as viewed in the figure) between the spring element 902 and the frame 906, and preferably inward of the periphery of the semiconductor die 908. This is suitably accomplished by inserting a rigid (well-supported) anvil-like element 914 in the gap between the front (top, as viewed in the figure) surface of the semiconductor die 908 and the back (bottom, as viewed in the figure) surface of the lead 904, and urging a wedge-shaped tool 916 against the front (top, as viewed in the figure) surface of the lead 904, opposite the anvil 914 with sufficient force to sever the leads of the leadframe.
• the leadframe be sized to fit entirely within the periphery of the semiconductor die 908.
• Figure 9B illustrates an alternate embodiment 950 of the invention.
• the carrier includes a plurality of conductive leads (lines) 952 (preferably sans frame) which are backed with (supported by) an insulating layer 954, such as a kapton (tm) film.
• a spring element 956 (compare 902) is mounted to an inner portion of each lead 952 (compare 904) , and each lead 952 is connected to a corresponding terminal 958 (compare 910) of a semiconductor die 960 (compare 908) .
• a suitable adhesive 962 (compare 912) is used to mount the spring carrier 950 to the front surface of the semiconductor die 960.
• the leads 952 are patterned and sized so that they do not extend beyond the periphery of the semiconductor die 960.
• the insulating film 954 may extend beyond the periphery of the semiconductor die 960. This is generally preferred.
• a dashed line 966 indicates the boundary between the inner portion and the outer portion of the insulating layer. These two portions of the insulating layer may be severed from one another in any suitable manner including, but not limited to, providing perforations along the line 966, applying a hot bar to the line 966, directing a focussed laser beam along the line 966, or the like.
• Figure 9C illustrates, in perspective, a spring carrier 970 mounted to a semiconductor die 972, with the inner ends of the leads 974 encapsulated, with spring elements 976 extending from the leads, and with the outer portion 978 of the leadframe shown in dashed lines (having been excised, as described hereinabove) .
• Figure 10 illustrates another embodiment 1000 of a semiconductor chip assembly, utilizing solder connections to the semiconductor die (chip) rather than bond wires.
• a spring element carrier substrate 1002 is provided with a plurality (two of many shown) of terminals 1004 on a top surface 1002a and a plurality (two of many shown) of terminals 1006 on a bottom surface 1002b.
• a plurality (two of many shown) of spring elements 1008 are mounted to the terminals 1004, in a manner similar to the previous embodiments.
• the terminals 1004 are connected to the terminals 1006 through the carrier substrate 1002, using suitable vias or the like (not shown) .
• a semiconductor device (die, chip) 1010 has a plurality (two of many shown) of terminals 1012 disposed on its front (top, as viewed) surface.
• the terminals 1006 are arranged to be in alignment with corresponding ones of the terminals 1012, and the thermal coefficient of expansion of the carrier substrate 1002 is chosen to nearly match the thermal coefficient of expansion of the semiconductor die 1010.
• the carrier substrate 1002 is mounted to the semiconductor chip 1010 by soldering.
• small quantities of solder or solder paste 1014 are applied to at least one of the terminals 1006 and 1012. This may be done by screening (e.g., solder paste) , by inserting a solder preform between the carrier substrate 1002 and the semiconductor die 1010, or by any suitable conventional technique for effecting flip-chip type connections (solder joints) between two electronic components.
• solder masses (1014) When the solder masses (1014) are reflowed, the carrier substrate 1002 will tend to align itself to the semiconductor chip, due to surface tension.
• one or more large "dummy” solderable features 1016 and 1018 are provided, both on the bottom surface 1002b of the carrier substrate and on the front surface of the semiconductor die 1010, respectively.
• a suitable quantity (not shown) of solder or solder paste is applied to at least one of these features, in the manner described with respect to the solder masses 1014.
• solder or solder paste
• the carrier substrate 1002 and semiconductor die can be encapsulated (not shown) , in the manner set forth hereinabove.
• any spring elements may extend from the surfaces of the chip-scale carrier (e.g., 800) .
• this invention is not limited to the use of composite spring elements comprising a core and an overcoat.
• a plurality of individual chip-scale carriers can be configured in an array for mounting, en masse, to an electronic component (e.g., a semiconductor wafer) .
• an electronic component e.g., a semiconductor wafer
• a plurality of chip-scale carriers can be "tied” together with bond wires which are overcoated to enhance their rigidity.
• a plurality of chip- scale carriers can be physically associated with one another in a leadframe-type arrangement, or on a TAB (tape automated bonding) tape type carrier.
• Figure 11 illustrates a technique 1100 whereby a spring carrier 1102 (compare 1002) is mounted in a flip-chip manner to a semiconductor wafer 1106.
• the spring carrier 1102 may span more than one die site 1104 on the semiconductor wafer 1106.
• the spring carrier 1102 spans six adjacent die sites 1104.
• singulating (dicing) the die sites e.g., sawing the wafer
• the spring carrier 1102 will also be diced.
• the free-standing spring contacts (compare 1108) extending from the exposed surface of the spring carrier 1102 are omitted, for illustrative clarity.
• the technique 600 set forth in Figures 6 and 6A could be applied to a carrier substrate spanning two or more unsingulated dies on a wafer, in the manner set forth in Figure 5A.
• a carrier substrate of a hermetic material such as ceramic is preferred. If necessary to ensure hermeticity, an encapsulating material could cover the edges of the carrier substrate and the surface to which the spring elements are mounted (including the bottom portions of the spring elements) .
• Another variation on the themes set forth hereinabove would be to take a relatively large carrier substrate (having corresponding pluralities of spring elements mounted thereto) , mount and connect (e.g., reflow soldering) the carrier to a plurality of joined semiconductor dies (e.g., by solder bumps on the semiconductor dies or on the bottom surface of the "oversize” carrier substrate) , then slice up (singulate) the semiconductor dies (with spring carriers attached thereto) .
• An encapsulant as mentioned in the previous paragraph, could be employed either before or after singulating the semiconductor dies .

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• 1996
  • 1996-05-28 AU AU59657/96A patent/AU5965796A/en not_active Abandoned
  • 1996-05-28 WO PCT/US1996/008328 patent/WO1997016866A2/en active IP Right Grant
  • 1996-05-28 KR KR1019970708468A patent/KR100299465B1/ko not_active IP Right Cessation
  • 1996-05-28 JP JP51454797A patent/JP2968051B2/ja not_active Expired - Fee Related

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