WO1997016002A1 - Dispositif de recuperation de signal d'horloge pour systemes de communication mettant en application une modulation d'impulsions en amplitude ou en quadrature - Google Patents

Dispositif de recuperation de signal d'horloge pour systemes de communication mettant en application une modulation d'impulsions en amplitude ou en quadrature Download PDF

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Publication number
WO1997016002A1
WO1997016002A1 PCT/IB1996/001141 IB9601141W WO9716002A1 WO 1997016002 A1 WO1997016002 A1 WO 1997016002A1 IB 9601141 W IB9601141 W IB 9601141W WO 9716002 A1 WO9716002 A1 WO 9716002A1
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WO
WIPO (PCT)
Prior art keywords
signal
absolute value
baseband
clock
clock signal
Prior art date
Application number
PCT/IB1996/001141
Other languages
English (en)
Inventor
Beomsup Kim
Original Assignee
Philips Electronics N.V.
Philips Norden Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/592,219 external-priority patent/US5802113A/en
Application filed by Philips Electronics N.V., Philips Norden Ab filed Critical Philips Electronics N.V.
Priority to JP51644397A priority Critical patent/JP2002516039A/ja
Priority to EP96933573A priority patent/EP0800731A1/fr
Publication of WO1997016002A1 publication Critical patent/WO1997016002A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/38—Demodulator circuits; Receiver circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Definitions

  • This invention relates generally to transmission systems using synchronous pulse amplitude modulation and particularly to clock signal recovery apparatus used therein.
  • modulation formats adopted by the Electronics Industry Association Interim Standard 54 and IS 136 use a linear modulation technique known generally as differential phase shift keying, or DPSK.
  • DPSK differential phase shift keying
  • One variant of the adopted standard is known generally as pi over four quaternary phase shift keyed, or ⁇ /4 QPSK.
  • this standard utilizes square-root raised cosine filter wi ⁇ h roll-off or ⁇ /4 DQPSK (pi over four differential phase shift keying) of 0.35 and enjoys its principle advantage in bandwidth efficiency.
  • I and Q signal components are modulated in quadrature upon a carrier for transmission.
  • Quadrature modulation of the I and Q components is preferred due to its minimization of crosstalk or crosscoupling between the I and Q components and the ease with which the I and Q signal components may be subsequently separated.
  • the received signal is frequency converted to an intermediate frequency signal which is then synchronously detected to produce a baseband signal having the recovered I and Q components.
  • a data detector then processes the baseband I and Q components to recover the data.
  • the correct detection of data widiin the receiver requires the availability of a clock signal or timing signal corresponding in frequency and phase to the clock signal employed during data encoding by the transmitter.
  • receivers Since it is impractical in the face of limited channel bandwidth availability to separately transmit the clock signal, receivers generate a clock signal locally which is synchronized to the transmitter.
  • a process generally referred to as clock signal recovery is used to extract clock signal information from the received signal which is then used as a timing signal to detect the encoded data synchronously. Because provision of a properly synchronized clock signal is a critical factor in data detection, extremely tight phase-locked loops responsive to the recovered clock information are operative upon the receiver clock.
  • clock signal recovery has been implemented using either intermediate frequency or baseband signals.
  • clock recovery systems may be generally described as either “data-aided” in which the data generated by the data detection system is utilized in the clock recovery process or “non data- aided” in which clock recovery is carried on independent of detected data.
  • data-aided clock recovery systems enjoy substantial advantages over non data-aided systems in providing recovered clock signals exhibiting substantially less signal jitter.
  • data-aided clock recovery systems are subject to error accumulation problems and relatively slow clock signal recovery because it requires more computation.
  • the latter problem arises in that the clock signal recovery system requires the ou ⁇ ut data from the data detection system to function while the data detection system requires recovered clock signals to perform its detection. In practice, this problem is met by utilizing slow initial acquisition cycles based on the use of known initial data sequences within the transmitted signal.
  • non data-aided clock signal recovery systems achieve fast clock signal recovery and are not subject to error accumulation problems exhibited by data-aided systems.
  • non data-aided systems are subject to excessive clock signal jitter or phase r.oise. Since jitter in the recovered clock signal affects the error performance of the receiver directly in mat me recovered clock signal is used to equalize the channel and to detect the data, such jitter must of necessity be minimized.
  • present clock signal recovery systems whether data-aided or non data-aided result in substantial compromise of clock signal recovery effectiveness and reliability. There arises therefore a need in die art for a clock signal recovery system which achieves fast clock signal recovery and low jitter performance without being subject to error accumulation problems.
  • a clock signal recovery system comprising: a first absolute value generator having an I signal component input for receiving the baseband I signal component, means for converting the I signal component to an absolute value I signal and an absolute value I signal output; a second absolute value generator having a Q signal component input for receiving the baseband Q signal component, means for converting the Q signal component to an absolute value Q signal and an absolute value Q signal output; combining means coupled to u e absolute value I and Q signal outputs for combining the absolute value I signal and the absolute value Q signals to form a combined I and Q absolute value signal; a third absolute value generator coupled to the combining means for generating absolute values of the combined I and Q absolute value signal; and a clock signal filter having
  • Figure 2 sets forth a block diagram of the present invention clock signal recovery system
  • Figure 3 sets forth a graphical representation of a typical recovered clock signal utilizing ⁇ ie present invention clock signal recovery system. Description of the Preferred Embodiment
  • FIG. 1 sets forth an illustrative digital communication system receiver utilizing the present invention clock recovery system and generally referenced by numeral 10.
  • Receiver 10 includes a receiving antenna 11 coupled to a conventional frequency converting system 12, the ou ⁇ ut of which is coupled to an intermediate frequency amplifying and filtering circuit 13.
  • a baseband signal detector 14 is coupled to intermediate frequency circuit 13 and includes an I signal ou ⁇ ut 20 and a Q signal ou ⁇ ut 21.
  • a data detector 15 includes baseband inputs 22 and 23 coupled to ou ⁇ uts 20 and 21 respectively of baseband detector 14 and a detected data ou ⁇ ut 24.
  • a processor 16 which may be constructed in accordance with conventional fabrication techniques is operatively coupled to data detector 15 by a bidirectional coupling 25.
  • a receiver clock 34 constructed in accordance with conventional fabrication techniques includes an ou ⁇ ut 40 providing clock signals to clock input 26 of data detector 15.
  • a conventional phase-locked loop 35 includes a clock signal input 36 coupled to clock 34 and a clock reference signal input 37 coupled to ou ⁇ ut 33 of clock recovery circuit 30. Ou ⁇ ut 38 of phase-locked loop 35 is coupled to clock 34 to complete the phase-locked loop coupling operative upon clock 34.
  • antenna 11, frequency converter 12, intermediate frequency filter 13 and baseband detector 14 operate in accordance with conventional techniques in which a transmitted data communication signal received by antenna 11 is converted by frequency converter 12 to an intermediate frequency signal corresponding to the passband frequency of intermediate frequency amplifier 13.
  • Intermediate frequency filter 13 excludes undesired harmonics and interfering signals and couples uie filtered intermediate frequency signal to baseband detector 14.
  • Baseband detector 14 utilizes conventional demodulation techniques, such as synchronous detection, to recover the respective baseband I and Q signal components from die intermediate frequency signal and provides baseband I and Q signal inputs to data detector 15.
  • the signal received at antenna 11 includes a carrier signal modulated in accordance with a synchronous pulse amplitude modulation.
  • modulation systems are well known and, while they differ somewhat in format, are similar in their use of periodic data pulses having amplitudes modulated within predetermined amplitude levels to communicate data in a more efficient manner.
  • uie type of synchronous pulse amplitude modulation utilized is that known as ⁇ /4 QPSK or ⁇ /4 DQPSK modulation.
  • data detector 15 operates in response to processor 16 and locally generated clock signals provided by clock 34 to detect uie modulated data and provide detected data at ou ⁇ ut 24.
  • phase-locked loop 35 operates in response to a sample of uie local clock signal produced by clock 34 and a reference signal input at input 37 recovered by clock recovery system 30. While a variety of phase-locked loop systems may be utilized to synchronize clock 34, all basically require a reference signal reliably related to the transmitter clock signal to control the local clock circuit within the receiver.
  • clock recovery circuit 30 fulfills this critical requirement in a novel and inventive manner.
  • the operation of clock recovery system 30 is set forth below in greater detail.
  • clock recovery system 30 receives baseband I and Q input signals from baseband detector 14 and produces an ou ⁇ ut signal at ou ⁇ ut 33 which comprises the recovered reference clock signal to be used in controlling phase-locked loop 35.
  • clock recovery system 30 is a baseband recovery system in mat it utilizes baseband I and Q signals.
  • clock recovery system 30 is a non data-aided system in that it operates witiiout utilization of the detected data recovered by data detector 15.
  • clock recovery system 30 does not exhibit uie slow initial acquisition cycle and tendency toward error accumulation which have plagued data-aided systems.
  • clock recovery system 30 provides the superior clock signal jitter performance characteristic of data-aided systems which has heretofore been unobtainable in non data-aided clock recovery systems.
  • FIG. 2 sets forth a block diagram of uie present invention clock recovery system generally referenced in Figure 1 by numeral 30.
  • clock recovery system 30 includes respective I and Q signal inputs 31 and 32 and a recovered clock signal ou ⁇ ut 33.
  • An absolute value generator 50 includes an input 51 coupled to I signal input 31 and an ou ⁇ ut 52.
  • a second absolute value generator 60 includes an input 61 coupled to Q signal input 32 and an ou ⁇ ut 62.
  • a summing network 53 includes an additive input 54 coupled to I signal ou ⁇ ut 52 and a subtractive input 55 coupled to Q signal ou ⁇ ut 62.
  • Summing network 53 combines the absolute value ou ⁇ uts of generators 50 and 60 to produce a combined ou ⁇ ut 56 which is applied to an input 71 of a ⁇ hird absolute value generator 70.
  • Generator 70 includes an ou ⁇ ut 72 coupled to input 74 of a filter 73.
  • Filter 73 includes a filtered signal ou ⁇ ut 33 which is coupled to input 37 of phase-locked loop 34 in uie manner described above. It should also be recalled mat phase-locked loop 34 receives a sample clock signal from clock 34 at input 36 and produces a clock control signal at ou ⁇ ut 38 which is applied to clock 34 in the manner shown in Figure 1.
  • the baseband I and Q signals at inputs 31 and 32 are converted to absolute value I and Q signals by absolute value generators 50 and 60 and applied to summing network 53.
  • absolute value generators 50 and 60 ra ⁇ ier dian squaring circuits used in prior art systems provides substantially lower signal distortion and substantial saving of computation required by the system processor.
  • the absolute value I and Q signals combined widiin summing network 53 are subjected to a furdier absolute value computation within absolute value generator 70.
  • die use of a third absolute value generator 70 operative upon die combined I and Q absolute value signals further lowers the signal distortion.
  • filter 73 fulfills the function of clock filtering widiin clock recovery circuit 30 and substantially excludes undesired harmonics and signal components while emphasizing die recovered clock signal.
  • filter 73 comprises a baud rate or higher rate widi a low order filter functioning to select the clock signal frequency components from die absolute value signal generated by generator 70 which forms die recovered reference clock signal for use by phase-locked loop 34.
  • Figure 3 sets forth a graphical representation of a typical recovered clock signal utilizing die present invention clock signal recovery system as it would appear at ou ⁇ ut 33 of filter 73 (seen in Figure 2).
  • Figure 3 displays relative amplitude along vertical axis 101 and time along horizontal axis 100.
  • a typical baseband I component signal is shown as dashed-line curve 102.
  • the corresponding recovered clock reference signal provided by the above-described present invention clock signal recovery system is shown as solid-line curve 103.
  • die signal waveform of curve 103 defines a plurality of positive going peaks 104 dirough 111 which are generally evenly spaced in time and relatively constant in amplitude.
  • the signal waveform of curve 103 defines a plurality of negative going peaks 112 through 118 interleaved or interspaced between positive going peaks 104 dirough 111 which are also substantially equally spaced in time and which also define relatively constant peak amplitudes.
  • the relatively even time intervals between peaks of the recovered clock signal provide periodic reliable reference information for use by uie phase-locked loop controlling the local clock signal.
  • the stable consistent amplitudes of uie signal peaks also ensure that undesired phase errors will not be introduced onto die phase-locked loop reference signa.
  • clock recovery system provides a recovered reference clock signal which defines peak portions which may readily be used to synchronize die receiver clock phase-locked loop. It will be equally apparent to diose skilled in die art tiiat the present invention clock signal recovery system provides die advantages of bodi data-aided and non data-aided systems while avoiding their disadvantages. As a result, the system compromises previously required are avoided.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Récepteur de communication de données comprenant des moyens classiques de réception et de démodulation d'un signal à modulation synchrone d'impulsions en amplitude, permettant de produire des signaux de bande de base I et Q. Une paire de générateurs de valeur absolue traitent les signaux de bande de base I et Q afin de produire des signaux I et Q de valeur absolue qui sont combinés de manière à constituer un signal combiné I et Q. Le signal combiné I et Q est appliqué à un troisième générateur de valeur absolue, dont la sortie est filtrée par un débit en bauds ou par un débit supérieur au moyen d'un filtre bas, afin de produire un signal d'horloge récupéré.
PCT/IB1996/001141 1995-10-25 1996-10-24 Dispositif de recuperation de signal d'horloge pour systemes de communication mettant en application une modulation d'impulsions en amplitude ou en quadrature WO1997016002A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP51644397A JP2002516039A (ja) 1995-10-25 1996-10-24 パルス振幅変調／直角位相振幅変調を用いる通信システムのクロック信号回復装置
EP96933573A EP0800731A1 (fr) 1995-10-25 1996-10-24 Dispositif de recuperation de signal d'horloge pour systemes de communication mettant en application une modulation d'impulsions en amplitude ou en quadrature

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US703895P 1995-10-25 1995-10-25
US60/007,038 1995-10-25
US08/592,219 US5802113A (en) 1995-10-25 1996-01-26 Clock signal recovery system for communication systems using quadrature amplitude modulation
US08/592,219 1996-01-26

Publications (1)

Publication Number Publication Date
WO1997016002A1 true WO1997016002A1 (fr) 1997-05-01

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EP (1) EP0800731A1 (fr)
WO (1) WO1997016002A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7738599B2 (en) 2002-10-24 2010-06-15 Trident Microsystems (Far East) Ltd. Method and circuit for generating an auxiliary symbol for adjusting a QAM demodulator

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4344176A (en) * 1980-04-03 1982-08-10 Codex Corporation Time recovery circuitry in a modem receiver
JPH06177927A (ja) * 1992-12-07 1994-06-24 Murata Mfg Co Ltd Ｄｑｐｓｋ遅延検波回路
US5455847A (en) * 1992-07-10 1995-10-03 Hewlett-Packard Company Clock recovery phase detector
US5524120A (en) * 1994-07-05 1996-06-04 Rockwell International Corporation Digital low power symbol rate detector

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4344176A (en) * 1980-04-03 1982-08-10 Codex Corporation Time recovery circuitry in a modem receiver
US5455847A (en) * 1992-07-10 1995-10-03 Hewlett-Packard Company Clock recovery phase detector
JPH06177927A (ja) * 1992-12-07 1994-06-24 Murata Mfg Co Ltd Ｄｑｐｓｋ遅延検波回路
US5524120A (en) * 1994-07-05 1996-06-04 Rockwell International Corporation Digital low power symbol rate detector

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7738599B2 (en) 2002-10-24 2010-06-15 Trident Microsystems (Far East) Ltd. Method and circuit for generating an auxiliary symbol for adjusting a QAM demodulator

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Publication number Publication date
EP0800731A1 (fr) 1997-10-15

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