WO1997014218A1 - Gatable level-pulling circuit - Google Patents
Gatable level-pulling circuit Download PDFInfo
- Publication number
- WO1997014218A1 WO1997014218A1 PCT/US1996/014222 US9614222W WO9714218A1 WO 1997014218 A1 WO1997014218 A1 WO 1997014218A1 US 9614222 W US9614222 W US 9614222W WO 9714218 A1 WO9714218 A1 WO 9714218A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- level
- pulling
- signal
- pin
- mode
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1731—Optimisation thereof
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/30—Modifications for providing a predetermined threshold before switching
- H03K17/302—Modifications for providing a predetermined threshold before switching in field-effect transistor switches
Definitions
- the present invention relates generally to integrated circuit design and use, and in
- Some applications of an IC may use certain IC pins, i.e. points of electrical contact
- IC pins (such as IC pins for a high impedance logic signal input function) which are not connected to an external logic signal may tend to oscillate or cause excessive power consumption if not pulled to a stable logic signal state that is undriven or
- a traditional solution to oscillation of floating logic input IC pins incorporates a "pull- up” or “pull-down” resistor coupled between the input IC pin and a positive or
- the level-pulling device e.g., a pull-up or pull-down
- resistor pulls the input IC pin to a given logic state to repress oscillation.
- input IC pin is not used, i.e., the IC device is used in an application not requiring that particular IC pin, no oscillation occurs. If a particular IC pin is used, (i.e., coupled to an external device in a given application), an input signal at the IC pin must
- a level-pulling function should be established only when needed, and disabled at other times.
- a high resistance field effect transistor (FET) having a small, long channel serves as
- a configuration device such as a mask or
- an input signal is applied to the input IC pin, the IC pin is undesirably in a level-pulling mode and excess power is devoted to overcoming the level-pulling device.
- the present invention provides circuitry automatically establishing or disabling a
- a logic signal responsive to signal activity at the IC pin drives a level-pulling device to dynamically establish or disable a level-pulling function at the IC pin.
- a level-pulling device for an integrated circuit device pin under the present invention includes a level-pulling element coupling the pin to a selected electrical potential.
- the level-pulling device includes a gate receiving a mode-setting signal selecting
- a mode-setting element produces the mode-setting signal as a
- An integrated circuit device under the present invention selectively responds to an external signal to establish or disable a level-pulling function.
- An electrical signal conductor couples the external signal to signal processing circuitry of the integrated circuit.
- a level-pulling device couples the signal conductor to a selected electrical
- the level-pulling device dictates resistance between the signal conductor and the selected electrical potential. A first state of the level-pulling device
- mode-driving device responds to electrical potential at the signal conductor to drive
- FIG. 1 illustrates an integrated circuit (IC) device including pins used in only some
- FIG. 2 illustrates, partially and in block diagram, circuitry intemal to the IC device of
- FIG. 1 including circuitry relative to a potentially unused pin of the IC.
- FIG. 3 is an altemative circuit relative to that shown in FIG. 2.
- FIG. 4 illustrates signal waveforms including an input logic signal and corresponding
- FIG. 1 illustrates an integrated circuit (IC) device 10 including about its periphery a plurality of pins 12 establishing electrical signal paths between integrated circuit 10
- IC integrated circuit
- circuit 10 includes certain ones of pins 12 which may or may not be used in a given
- Pin 12a represents one of such pins 12.
- Pin 12a includes a logic signal input function which may or may not be
- pin 12a is unconnected or undriven
- Pin 12a may, therefore, be considered a floating
- FIG. 2 illustrates level-pulling circuitry of integrated circuit 10 relative to pin 12a.
- a bond wire 20 electrically couples pin 12a to a bond pad 22 of integrated circuit 10.
- Conductor 24 couples pad 22 to an input buffer 26.
- Conductor 28 couples the output of input buffer 26 to control and signal processing circuitry 30,
- a high resistance field effect transistor (FET) 32 couples conductor 24 to a selected electrical potential, i.e., ground potential 34. FET 32 establishes or disables a level-
- a logic signal delivered via conductor 36 at FET gate 32a establishes or disables the level-pulling function of FET 32.
- such logic signal establishes a level-pulling function by "closing" FET 32, i.e., providing a given magnitude
- Integrated circuit 10 includes a flip-flop register 40, responsive to signal activity at pin 12a, to drive the gate 32a of FET 32.
- Conductor 36 couples the Q output of register 40 to gate 32a of FET 32.
- Register 40 includes a SET input and a RESET input.
- a conductor 42 couples to the SET input of register 40 to establish
- a conductor 44 couples conductor 28 and the RESET input of register 40 to drive register 40 dynamically during operation of integrated circuit 10 and thereby selectively establish or disable a FET 32 level-pulling
- circuitry 30 initially drives conductor 42 with a pulse 70 of sufficient duration to set register 40, i.e., close FET 32, and establish a level-pulling function.
- pulse 70 could also originate from "off-chip", e.g., a global
- pin 12a may be an input/output pin by further incorporation
- an output buffer 50 having a signal input conductor 52 and an output enable conductor 54 applied thereto.
- a conductor 56 couples the output of buffer 50 to conductor 24, thereby allowing signal processing circuitry 30 to selectively drive pin 12a.
- integrated circuit 10 may be designed for a variety of applications, some of
- FET 32 is disabled as a
- circuit 10 manufacture or initial configuration. Integrated circuit 10 dynamically responds to signal activity at pin 12a to selectively establish or disable the desired
- FIG. 3 illustrates an altemative mode-driving device, i.e., a mechanism driving FET
- register 40 is replaced with an OR gate 60.
- Conductor 36 couples the output of OR gate 60 to gate 32a of FET
- Conductor 44 connects to an inverting input 60a of OR gate 60.
- Conductor 42 connects to an inverting input 60a of OR gate 60.
- signal processing circuitry 30 provides an
- pulse 70 is of sufficient duration to cause FET 32 to close, thereby
- a logic value one arriving at pin 12a causes FET 32 to open, following inherent delay in elements 26, 60, and 32, thereby disabling the level-pulling function.
- the level-pulling function remains
- FIG. 4 illustrates waveforms representative of the circuitry of FIGS. 2 and 3.
- waveform 98 represents the initial pulse 70 establishing a level-pulling function.
- Waveform 100 corresponds to an logic input signal provided by an external device
- Waveform 102 represents current drawn through a traditional level-
- Waveform 104 illustrates current drawn through FET 32
- Waveform 108 passes through FET 32 upon the first occurrence of a logic value one presentation in waveform 100, i.e., at the first rising edge in waveform 100.
- Waveform 108
- Waveform 108 illustrates multiple occurrences of current passage through FET 32, i.e., one for each rising edge in the input waveform 100.
- Waveforms 104
- the present invention provides, for unconnected IC pins, a mechanism and
- FET 32 is initially placed in a level-pulling mode to maintain a first logic state at the
- circuitry of the present invention automatically
- level-pulling device i.e., conserves power otherwise consumed in driving the input pin to a state opposite that established by a level-pulling device.
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP96929907A EP0855104A4 (en) | 1995-10-13 | 1996-09-04 | Gatable level-pulling circuit |
JP9515031A JPH11513556A (en) | 1995-10-13 | 1996-09-04 | Gating level pulling circuit |
AU69141/96A AU6914196A (en) | 1995-10-13 | 1996-09-04 | Gatable level-pulling circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/543,248 | 1995-10-13 | ||
US08/543,248 US5594362A (en) | 1995-10-13 | 1995-10-13 | Gatable level-pulling circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1997014218A1 true WO1997014218A1 (en) | 1997-04-17 |
Family
ID=24167210
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1996/014222 WO1997014218A1 (en) | 1995-10-13 | 1996-09-04 | Gatable level-pulling circuit |
Country Status (6)
Country | Link |
---|---|
US (1) | US5594362A (en) |
EP (1) | EP0855104A4 (en) |
JP (1) | JPH11513556A (en) |
AU (1) | AU6914196A (en) |
CA (1) | CA2227254A1 (en) |
WO (1) | WO1997014218A1 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5777488A (en) * | 1996-04-19 | 1998-07-07 | Seeq Technology, Inc. | Integrated circuit I/O node useable for configuration input at reset and normal output at other times |
JP3465493B2 (en) * | 1996-09-26 | 2003-11-10 | ヤマハ株式会社 | Semiconductor integrated circuit |
EP2255440A1 (en) * | 2008-03-16 | 2010-12-01 | Nxp B.V. | Methods, circuits, systems and arrangements for undriven or driven pins |
JP6128911B2 (en) * | 2013-03-22 | 2017-05-17 | ラピスセミコンダクタ株式会社 | Semiconductor device and power-down control method |
CN114342261A (en) * | 2019-10-18 | 2022-04-12 | 罗姆股份有限公司 | Audio circuit |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5051622A (en) * | 1989-11-08 | 1991-09-24 | Chips And Technologies, Inc. | Power-on strap inputs |
US5111079A (en) * | 1990-06-29 | 1992-05-05 | Sgs-Thomson Microelectronics, Inc. | Power reduction circuit for programmable logic device |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5086407A (en) * | 1989-06-05 | 1992-02-04 | Mcgarity Ralph C | Data processor integrated circuit with selectable multiplexed/non-multiplexed address and data modes of operation |
JPH03104315A (en) * | 1989-09-19 | 1991-05-01 | Matsushita Electron Corp | Input terminal potential fixing circuit for cmos semiconductor device |
DE69034165T2 (en) * | 1990-07-20 | 2005-09-22 | Infineon Technologies Ag | Microprocessor with a variety of bus configurations |
EP0518488A1 (en) * | 1991-06-12 | 1992-12-16 | Advanced Micro Devices, Inc. | Bus interface and processing system |
JPH06195476A (en) * | 1992-07-21 | 1994-07-15 | Advanced Micro Devicds Inc | Integrated circuit for incorporation of microcontroller and method for reduction of power consumption by it |
US5432465A (en) * | 1994-05-06 | 1995-07-11 | Windbond Electronics Corp. | Integrated circuit switchable between a line driver function and a bidirectional transceiver function during the packaging stage of the integrated circuit |
-
1995
- 1995-10-13 US US08/543,248 patent/US5594362A/en not_active Expired - Lifetime
-
1996
- 1996-09-04 EP EP96929907A patent/EP0855104A4/en not_active Withdrawn
- 1996-09-04 CA CA002227254A patent/CA2227254A1/en not_active Abandoned
- 1996-09-04 JP JP9515031A patent/JPH11513556A/en active Pending
- 1996-09-04 WO PCT/US1996/014222 patent/WO1997014218A1/en not_active Application Discontinuation
- 1996-09-04 AU AU69141/96A patent/AU6914196A/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5051622A (en) * | 1989-11-08 | 1991-09-24 | Chips And Technologies, Inc. | Power-on strap inputs |
US5111079A (en) * | 1990-06-29 | 1992-05-05 | Sgs-Thomson Microelectronics, Inc. | Power reduction circuit for programmable logic device |
Non-Patent Citations (1)
Title |
---|
See also references of EP0855104A4 * |
Also Published As
Publication number | Publication date |
---|---|
JPH11513556A (en) | 1999-11-16 |
US5594362A (en) | 1997-01-14 |
EP0855104A1 (en) | 1998-07-29 |
CA2227254A1 (en) | 1997-04-17 |
EP0855104A4 (en) | 1999-11-10 |
AU6914196A (en) | 1997-04-30 |
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