WO1997004570A1 - Controle des attributions de largeur de bande a l'aide d'un compteur de cadence - Google Patents

Controle des attributions de largeur de bande a l'aide d'un compteur de cadence Download PDF

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Publication number
WO1997004570A1
WO1997004570A1 PCT/US1996/011964 US9611964W WO9704570A1 WO 1997004570 A1 WO1997004570 A1 WO 1997004570A1 US 9611964 W US9611964 W US 9611964W WO 9704570 A1 WO9704570 A1 WO 9704570A1
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WO
WIPO (PCT)
Prior art keywords
cell
switch
predetermined value
value
counter
Prior art date
Application number
PCT/US1996/011964
Other languages
English (en)
Inventor
Stephen A. Caldara
Stephen A. Hauser
Thomas A. Manning
Raymond L. Strouble
Original Assignee
Fujitsu Network Communications, Inc.
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Network Communications, Inc., Fujitsu Limited filed Critical Fujitsu Network Communications, Inc.
Priority to AU65036/96A priority Critical patent/AU6503696A/en
Priority to JP9506067A priority patent/JPH11510324A/ja
Priority to PCT/US1996/011964 priority patent/WO1997004570A1/fr
Publication of WO1997004570A1 publication Critical patent/WO1997004570A1/fr

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    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management
    • H04L2012/5683—Buffer or queue management for avoiding head of line blocking
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5685—Addressing issues
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Definitions

  • This invention relates to telecommunications and more specifically to a method and apparatus for controlling delay and bandwidth allocation in a network switch.
  • Network switches such as Asynchronous Transfer Mode (ATM) network switches, are employed to route received network traffic received on one of a plurality of input ports to one or more of a plurality of output ports for delivery ultimately to an intended destination or destinations over a network communications link.
  • Input ports of the network switch may support a number of unidirectional physical links over which network traffic is received and output ports of the switch may likewise support a plurality of unidirectional physical links over which network traffic is transmitted.
  • the data streams comprise pluralities of ATM cells. Multiple cell streams involving different data sources and destinations may be multiplexed on any given link.
  • the cell streams referred to as connections, are differentiated by fields which are contained in the cell header.
  • Cell reception at a network switch is largely non- deterministic and bursty in nature. Thus, large numbers of cells may be received at a network switch which need to be quickly routed from the respective input port to the appropriate output port or ports of the switch. Moreover, cells may be received over the various links which are competing for the same switch bandwidth.
  • the network switch must manage such network traffic such that traffic which needs access to greater switch bandwidth are afforded such bandwidth while not starving other traffic which also needs access to the switch bandwidth. Additionally, different types of network traffic have different service needs. For some types of traffic, such as video and audio traffic, a minimum bandwidth within the network switch must be assured and minimum delays must be maintained to faithfully reproduce the signal at the destination. Other types of data traffic are not subject to the same requirements.
  • a method and apparatus for scheduling access to the available bandwidth within a network switch, such as an ATM network switch, having a plurality of input ports through which cells are received, a plurality of output ports for transmitting cells over a communication link, and a switch fabric for selectively forwarding cells received at each of the input ports to one or more of the output ports.
  • a network switch such as an ATM network switch
  • Cell streams for a plurality of connections are received at respective input ports of the network switch having a plurality of port processors comprising a To Switch Port processor (TSPP) , a From Switch Port Processor (FSPP) and Data Serial Interface. More specifically, the TSPP is responsible for handling incoming data streams and the FSPP is responsible for handling outgoing data streams.
  • the connection identification for each received cell is identified by parsing information contained in the cell header. Following parsing of the cell header and identification of the cell, the cell is placed on a queue associated with a scheduling list within the network switch if a cell buffer is available. If a cell buffer is unavailable, the cell is discarded and a statistics counter is updated or alternatively, the cell is forwarded to a system control module for further processing.
  • Network switch bandwidth is divided into allocated and dynamic bandwidth.
  • Allocated bandwidth is that network switch bandwidth which is guaranteed to be available to a scheduling list.
  • the allocated bandwidth for each scheduling list is preassigned as a switch administration function and may be changed under the control of network switch administration software. If a single connection is assigned to a scheduling list, that connection will have the ability to utilize the full amount of the allocated bandwidth. If multiple connections are assigned to a scheduling list, those connections will share the bandwidth assigned to the respective scheduling list.
  • the assignment of unallocated and unused allocated bandwidth (collectively referred to as "dynamic bandwidth") depends upon the instantaneous utilization of the switch resources. More specifically, dynamic bandwidth is shared by those connections which do not have allocated bandwidth and additionally may be shared by connections which have allocated bandwidth.
  • allocated bandwidth is managed using a time slot generator in conjunction with a pacing technique.
  • Bandwidth is overallocated to specified scheduling lists by assigning additional time slots to such lists, however, the pacing mechanism prevents the scheduling lists from using more than their respective designated bandwidth (which constitutes less than all of the allocated timeslots) .
  • a plurality of tables, known as switch allocation tables (SATs) are stored in memory within the switch. One such table is associated with each port processor within the network switch.
  • the SATs in conjunction with various scheduling lists and queues, are used in the determination of which cells will be dispatched from respective input ports through the switch fabric to the output ports on a cell time by cell time basis.
  • the entries within the respective SAT's contain scheduling list numbers which are used to select a queue assigned to a particular connection, i.e., the connection that will gain access to the switch fabric during the respective cell time.
  • a lookup table is maintained within the switch by administration software to map the respective connections to the various output ports.
  • Each SAT index counter produces an address output in response to a cell clock input.
  • the address outputs of the respective SAT index counters are coupled to respective address inputs of the SATs to selectively address one of the entries within each SAT within each cell time.
  • the SAT's are synchronized such that the same entry within each SAT, as specified by the respective SAT index counter, is selected during each clock interval.
  • the SAT index counters are continually clocked to identify successive entries within the SATs. After addressing or pointing to the last entry in the respective SATs, the SAT index counters wrap to address 0 so as to address the initial entry within the respective SATs.
  • the scheduling list numbers within the SATs comprise offsets which are used to index into a scheduling list table.
  • the scheduling list table serves to identify queues associated with the respective scheduling list.
  • Each queue comprises a FIFO which has entries pointing to one or more cells stored in a cell buffer memory and awaiting access to the switch fabric for selective forwarding from the respective input port to one or more of the output ports.
  • the scheduling list numbers within the SATs are maintained by administration software such that during any given cell interval, the output ports specified by the respective scheduling list numbers in the plurality of SATs are unique.
  • the amount of bandwidth and delay through the switch fabric is controlled by the number of entries in the respective SAT which are assigned to the respective scheduling lists.
  • the pacing mechanism assures that a predetermined number of entries with a SAT having a specified scheduling list number are skipped before allowing a cell from the respective scheduling list to be forwarded to one or more of the output ports. More specifically, a table of scheduling list descriptors is provided which includes one scheduling list descriptor for each scheduling list. Each scheduling list descriptor includes information pertinent to the respective scheduling list including a pace counter field and a pace limit field. The pace limit field specifies the number of entries within the SAT having a specific scheduling list number which must be accessed after dispatching a cell from that scheduling list prior to launching another cell through the switch fabric from that scheduling list.
  • the pace limit is programmable and is set under the control of system administration software.
  • the pace counter field represents a count of the remaining number of times that the respective scheduling list number must be accessed before launching another cell to the switch fabric from the respective scheduling list.
  • the pace counter for a respective scheduling list is set to the pace limit each time a cell is dispatched to the switch fabric from the respective list.
  • the pace counter for the respective scheduling list is decremented if the pace counter is not already set to 0. If the pace counter is equal to 0 it remains at zero until a cell is dispatched. If the pace counter is equal to 0, a cell may be launched to the switch fabric for delivery to the output port for the respective connection if a cell is queued for transmission on a queue of the respective scheduling list.
  • the pace counter is preset to 0 such that a cell will be dispatched the first time a SAT entry is accessed having the respective scheduling list number following enqueuing of a cell to a queue on that scheduling list.
  • the entries within the switch allocation table determine the allocated bandwidth for the respective connections identified in the SAT's and additionally reduce cell latency through the switch as a consequence of the overallocation of SAT entries for predetermined scheduling lists.
  • all slots within the SAT's are not allocated to scheduling lists.
  • slots within a SAT are not preassigned or allocated to a scheduling list, such slots are known as unallocated bandwidth and are available as dynamic bandwidth which may be assigned for use by connections competing for such dynamic bandwidth.
  • dynamic bandwidth is available for use in the event the respective SAT entry contains a valid scheduling list number but the pace counter does not permit a cell to be launched to the switch fabric for the respective scheduling list (pace counter is not equal to zero) (referred to as "unused allocated bandwidth") or in the event that a valid scheduling list number was present in the SAT for the respective time slot and the pace counter permitted the launching of a cell (pace counter was equal to 0) but no cell was present in the respective scheduling list's queue to be dispatched.
  • the foregoing scheduling technique assures that connections which need a minimum allocated bandwidth will receive that bandwidth. Additionally latency is reduced when compared to systems which utilize time slot bandwidth allocation without the presently disclosed pacing mechanism. Moreover, as a consequence of the pacing mechanism, bursty traffic is smoothed so that connections competing for resources are more likely to find dynamic bandwidth available.
  • Fig. 1 is a block diagram of a network switch in accordance with the present invention
  • Fig. la is a diagram illustrating the buffer organization in the network switch of Fig. 1;
  • Fig. 2 is a diagram of a plurality of switch allocation tables used in accordance with the present invention.
  • Fig. 3 is a diagram of the data structures used in conjunction with the switch allocation tables of Fig. 2;
  • Fig. 4 is a flow diagram illustrating the pacing mechanism employed in accordance with the present invention.
  • Fig. 5 is a diagram of data structures used to assure conflict avoidance in output port assignments.
  • the presently disclosed network switch 2 includes a plurality of input ports 14, a plurality of output ports 16 and an N x N switch fabric 9, coupled between the input ports 14 and output ports 16.
  • Each input port 14 includes a To Switch Port Processor ("TSPP") ASIC 22 and each output port 16 includes a From Switch Port Processor (“FSPP”) ASIC 17.
  • TSPP To Switch Port Processor
  • FSPP From Switch Port Processor
  • a Multipoint Topology Controller (“MTC”) ASIC 18 is coupled between each TSPP 22 and a Bandwidth Arbiter (“BA”) ASIC 12, as well as between the bandwidth arbiter 12 and each FSPP 17, as shown.
  • each MTC 18 supports up to four TSPPs 22 or FSPPs 17.
  • the switch fabric 9 includes a data switch 10, such as a data crossbar switch for data cell transport, a bandwidth arbiter 12 and MTCs 18 for control signal transport.
  • the N N switch fabric in the present embodiment yields a throughput of approximately N x 670 megabits per second.
  • the bandwidth arbiter 12 controls, inter alia, transport of data cells from a TSPP 22 to one or more FSPPs 17 through the data switch 10 (i.e., switch port scheduling) . More specifically, the bandwidth arbiter (“BA”) controls switch fabric interconnection, schedules available dynamic bandwidth and resolves multipoint to point bandwidth contention.
  • the TSPPs 22 accept streams of cells 26 as their inputs and presents another stream of cells to the data switch 10 for routing to the appropriate FSPPs 17.
  • Each FSPP 17 receives cells from the data switch 10 and schedules transmission of those cells onto network links 13 (i.e., link scheduling).
  • the incoming cells can be sourced by either a segmentation unit (not shown) which converts packets to cells, or alternatively cells may be sourced directly from a line interface such as an OC3 link.
  • Each of the input ports 14 and output ports 16 includes a plurality of input buffers 126 and output buffers 128, respectively (Fig. la).
  • the buffers 126, 128 are organized into a plurality of input queues 132a-m (referred to herein generally as input queues 132) and a plurality of output queues 134a-m (referred to herein generally as output queues 134) , respectively.
  • each input port 14 includes a plurality of input queues 132 and each output port 16 includes a plurality of output queues 134, as shown.
  • the input queues 132 are stored in a Control RAM 21 and a Pointer RAM 20 of the input port 14 and the output queues 134 are stored in a CRl RAM 44 and a CR2 RAM 44 of the output port 16.
  • a data cell 26 enters the network switch 2 through an input port 14 and is enqueued on an input queue 132 at the respective TSPP 22. The cell is then transmitted from the respective input queue 132 to one or more output queues 134 via the data switch 10. Control signals are transmitted from a
  • data and control signals may be transmitted from an input queue 132 to a particular one of the output queues 134, in the case of a point to point connection 140.
  • data and control signals may be transmitted from an input queue 132 to a selected set of output queues 134, in the case of a point to multipoint connection 142. From the output queue(s) 134, the data cell 26 is transmitted outside of the network switch 2, for example, to another switch 129 via a network link 13.
  • the bandwidth arbiter 12 contains a dataswitch or crossbar controller 80 which includes a probe crossbar, an XOFF crossbar and an XON crossbar, each of which is an NxN switch.
  • a request message, or probe control signal flows through the probe crossbar and is used to query whether or not sufficient space is available at the destination output queue, or queues 134 to enqueue a cell.
  • the request message is considered a "forward" control signal since its direction is from a TSPP 22 to one or more FSPPs 17 (i.e,., the same direction as data).
  • a two bit control signal flows in the reverse direction (from one or more FSPPs to a TSPP) through the XOFF crossbar and responds to the request message query by indicating whether or not the destination output queue, or queues 134 are presently capable of accepting data cells and thus, whether or not the transmitting TSPP can transmit cells via the data switch 10.
  • the XOFF control signal indicates that the queried output queue(s) 134 are not presently capable of receiving data
  • another reverse control signal which flows through the XON crossbar, notifies the transmitting TSPP once space becomes available at the destination output queue(s) 134.
  • Each output port 16 contains four memories: a Control RAM 1 (“CRl RAM”) 42, a Control RAM 2 (“CR2 RAM”) 44, a Cell Buffer RAM 48 and Quantum Flow Control RAM (“QFC RAM”) 46.
  • the Cell Buffer RAM 48 is where the actual cells are buffered while they await transmission to a network link 13.
  • the CRl RAM 42 and the CR2 RAM 44 contain the output queues 134, with each queue 134 containing pointers to cells in the Cell Buffer RAM 148.
  • the CRl RAM 42 contains information required to implement scheduling lists used to schedule link access by the output queues 134 associated with each link 13 supported by the FSPP 17.
  • the QFC RAM 46 stores update information for transfer to another switch 129 via a network link 13.
  • Update cells are generated in response to buffer state update information provided by a TSPP 22 and specify whether the particular TSPP 22 is presently capable of accepting data cells.
  • a VXT processor 19 inspects the cell header and indexes into certain lookup tables to ascertain whether the cell belongs to a valid scheduling list. In the event that the cell is associated with a valid scheduling list, the cell is assigned to an input queue number. The input queue number is used to point to a queue descriptor which contains state information pertaining to the respective scheduling list. Additionally, the queue number is used to locate the cells within the Cell Buffer RAM 23 as hereinafter described.
  • Switch allocation tables in conjunction with the pacing mechanism herein described, cooperatively assure deterministic delays within the network switch and provide for the allocation of bandwidth to individual connections or groups of connections comprising a scheduling list.
  • One switch allocation table is provided for each Input Port 14 within the Pointer Ram 20 of the respective Input Port 14.
  • the pointer ram 20 is coupled to a To Switch Port Processor ASIC (TSPP) 22 within the Input Port 14 via control and data buses 24.
  • TSPP To Switch Port Processor ASIC
  • SATs each comprise a linear table, the entries of which comprise scheduling list numbers, such as scheduling list numbers A, B, C, D, E and F shown in SATs 26.
  • SAT index counters 28a, 30a, 32a, 34a and 36a which sequentially address each entry within the respective SAT's.
  • the respective SAT index counters 28a, 30a, 32a, 34a and 36a are synchronized as hereinafter described such that the entry associated with the same SAT address for each of the SATs will be accessed at any given instant in time. For example, referring to Fig. 2, when the SAT index counter 28a provides an output address of "1", the Port 0 SAT 28 will provide an output equal to scheduling list number "A".
  • the SAT index counter 28a provides an output of "1"
  • the SAT index counter 30a for Port 1 will likewise produce an output address of "1” and the SAT 30 for Port 1 will provide an output equal to scheduling list number "D”.
  • the Port 2 SAT 32 will provide an output equal to scheduling list number "E”
  • the Port 3 SAT will provide an output equal to 0 (indicating that no scheduling number has been specified for this time slot) and the Port m SAT will provide an output equal to scheduling list number "F”.
  • the SAT index counters 28a, 30a, 32a, 34a and 36a are located within the respective TSPPs 22.
  • the SAT index counters are 14 bits wide thereby allowing for a SAT size of 0 to 16,383 entries.
  • the SAT size is specified by a value stored within a programmable register within the switch fabric 9 in a manner hereinafter discussed.
  • the SATs have 8192 entries, although the number of entries within the SATs may be varied based upon system requirements.
  • the SAT index counters are thus used to address the respective SATs within each TSPP 22 to select one of the possible 8192 entries a SAT in each Input Port 14 and, as indicated above, the SATs are synchronized so that corresponding addresses of each SAT table are selected during each SAT time slot.
  • the SAT index counters 28a, 30a, 32a, 34a ... 36a are incremented in response to a cell clock signal 40 which, in the present embodiment, causes the SAT index counters to increment every 635 nanoseconds.
  • a synchronizing pulse is superimposed on the cell clock signal 40 to cause the SAT index counters to reset to zero on the first cell clock after the detection of the synchronizing pulse.
  • the periodicity of the synchronization pulse is established by a predetermined value which is stored in a programmable register (not shown) and a counter located within the switch fabric 9. In one embodiment, the counter is loaded with the predetermined value stored in the programmable register and the counter is decremented upon the occurrence of each cell clock. The synchronizing pulse is generated when the counter reaches 0.
  • the counter is then reloaded with the predetermined value whereupon the cycle is repeated.
  • the counter may be incremented upon the occurrence of each cell clock and compared to the value stored within the programmable register.
  • the synchronizing pulse is generated and the counter is reset to 0.
  • the size of the SAT's is thus specified by the value stored within the programmable register since cycling through the respective SAT's will be restarted upon recognition of the synchronizing pulse.
  • One cell may be dispatched from each respective input port during each time slot associated with a SAT entry.
  • 16 cells could be launched from the respective input ports to the 16 output ports within the 635 ns cell clock interval.
  • the time slots within the SATs thus contain entries which determine the cells which can be launched to the data switch 10 of the switch fabric 9 for eventual transmittal out of the plurality of output ports 16 under the control of the respective FSPPs 17. Since two cells cannot be transmitted to the same output port during the same interval, the output ports associated with the scheduling list numbers in the respective SATs for any given SAT index counter address output must be unique. Thus, for address 1, the output ports associated with the entries in the respective SAT's for Ports 0 through m are unique.
  • Fig. 5 illustrates the mechanism by which output port conflicts are detected and avoided.
  • the mechanism is depicted for a 4 x 4 switch fabric for illustrative purposes.
  • each input port accesses a SAT entry.
  • the Input Port number is prepended to the scheduling list number retrieved from the respective SAT.
  • the Input Port number and scheduling list number are forwarded to the respective MTC 18.
  • the MTC maintains a lookup table 90 having segments 90a, 90b, 90c and 90c which are assigned to each of the four respective input ports.
  • the Input Port number, as illustrated in Fig. 5 is used to select one segment of the lookup table and the scheduling list number is employed as an offset into the respective segment of the lookup table 90.
  • the lookup table contains bit vectors which identify the Output Port or Ports which are needed for the respective cell traffic. For example, referring to Fig. 5, the bit vector retrieved for Input Port 0, scheduling list number 6, indicates that Input Port 0 has traffic for Output Port 1. The bit vector for Input Port 2, scheduling list number 3 indicates that Input Port 2 seeks to forward a cell to Output Ports 2 and 3. The bit vectors for the respective Input Ports are retrieved from the lookup table 90 and assembled in a matrix 92. The matrix 92 is tested to assure that no column has more than a single entry. In the event a column of the matrix contains two or more entries, such indicates that two or more input ports are requesting access to the same output port during the respective SAT time slot.
  • Call administration software within the network switch is responsible for loading the respective SATs so as to avoid conflicts regarding output port usage and SAT entry assignments.
  • each of the SAT tables repeatedly cycles through the respective entries in a predetermined sequence with a cell clock 40 clocking the respective SAT index counters every 635 nanoseconds.
  • Each timeslot or SAT scheduling list entry corresponds to approximately 64k bits/sec of cell payload bandwidth.
  • the data structures employed to identify a specific cell which will be dispatched to the data switch 10 of the switch fabric 9 from the respective TSPP 22 are illustrated in Fig. 3.
  • a scheduling list number 10 from one the SATs, and identified at 50, is employed as an offset into a scheduling list header table 52.
  • the scheduling list header table 52 includes a plurality of entries each of which includes a head pointer 54 and a tail pointer 56.
  • the scheduling list number (which in the present example is illustrated to be 10) is multiplied by 2 to obtain an offset of 20 to locate the head pointer at the 20th location within the Scheduling List Header Table 52.
  • bandwidth allocation can be assured for a single connection corresponding to a specific VPI/VCI address in an ATM environment, by assigning a single connection to a particular scheduling list which has available to it all of the bandwidth allocated via the SAT and the pacing mechanism.
  • multiple connections may be assigned to a single scheduling list which share the allocated bandwidth among the connections associated with that list.
  • a queue number (5 in the present example) is retrieved from the Scheduling List Header Table 52.
  • the retrieved queue number serves to identify the specific queue from which a cell will be retrieved for dispatch to the data switch 10 of the switch fabric 9.
  • the queue number within the head pointer of the Scheduling List Header Table 52 is also used as a pointer into a Queue Pointer Table 58.
  • the Queue Pointer Table 58 contains the queue number for the next queue on the scheduling list. Thus, in the present example, location 5 of the Queue
  • Pointer Table 58 contains the value 7 which is the queue number for the second queue in the respective scheduling list. Since the queue number 7 equals the queue number of the tail pointer 56 at location 21 of the Scheduling List Header table 52 in the present example, queue number 7 is the last queue on scheduling list number 10.
  • the queue number (such as queue number 5) in the Scheduling List Header Table 52 also serves as an index into a Queue Header Table 60.
  • the Queue Header Table is also organized with head and tail pointer pairs 62 and 64 respectively.
  • the head pointer 62 is used as an offset into the Cell Buffer RAM 23 to locate the cell for dispatch through the data switch 10 of the switch fabric 9.
  • the head pointer 62 also is used as an index into a Cell Pointer Table 66 to identify the location of the next cell within the respective cell queue scheduled for transmission through the data switch 10. In the present example, since the contents of location 100 contain the value of the tail pointer 64 of the queue header table 60, only two cells reside on the queue for transmission through the data switch 10.
  • the queue number such as queue number 5 is also used as an offset into a Queue Descriptor Table 67 which is stored within the Control RAM 21.
  • the Queue Descriptor Table contains one or more queue descriptors such as queue descriptor 68 which occupy five 32 bit entries within the Queue Descriptor Table.
  • the queue number obtained from the Scheduling List Header Table 52 is multiplied by 5 to obtain the offset into the Queue Descriptor Table 67.
  • the queue descriptor contains an identification of the scheduling list number for the respective queue number and additionally a cell count of cells currently buffered on the respective queue. When the cell count goes to 0 following transmission of the last cell on the respective queue, the queue is removed from the Scheduling List Header Table 52 and Queue Pointer Table 58.
  • the cell gets dequeued.
  • the Queue Header Table 60 is updated by loading the Head Pointer 62 with the contents of location 100 of the Cell Pointer Table 66. This points the queue header to the next cell to be transferred. Since there is an additional cell (the 15th cell within the cell buffer) that awaits transmission, queue number 5 within the Scheduling list Header table is not dequeued but rather, pushed to the bottom of the round robin list so that other queue numbers within the scheduling list will receive fair (round robin) access to the allocated bandwidth.
  • the relevant tables are updated after dispatch of a cell in the following manner.
  • the contents of the Head Pointer 54 are written to a temporary register (not shown) .
  • the Head Pointer 54 is next loaded with the value of the next queue number in the scheduling list which is obtained by using the value in the temporary register as an index into the Queue Pointer Table 58 and retrieving the value at the respective location.
  • the value in the temporary register (“5" in the present example) is next written into the location in the Queue Pointer Table 58 specified by the Tail Pointer 56 (i.e. a "5" is written into location 7 of the Queue Pointer Table 58 in the present example) .
  • the value in the temporary register is written into the Tail Pointer 56 to complete the updating of the respective tables.
  • queue number 5 As a consequence of the above described table updates, the next queue on the respective scheduling list with available cells for dispatch is selected in a round robin manner.
  • queue number 5 In the event that queue number 5 only included a single cell for transmission, upon dispatch of that cell to the switch fabric, queue number 5 would be dequeued, or removed, from the Scheduling List Header Table 52 instead of being pushed to the bottom of the round robin list.
  • the foregoing mechanism is employed to locate cells for dispatch at each Input Port 14 within each cell time.
  • the respective SAT entry contains a "0" entry, such indicates that no allocated bandwidth has been assigned for that timeslot for the respective Input Port 14.
  • the Bandwidth Arbiter is signaled that such timeslot is available for the use of dynamic bandwidth, i.e. cell dispatch through the switch fabric for which bandwidth has not been allocated through the SATs.
  • the pacing mechanism is employed in conjunction with the SATs to assure that allocated bandwidth is provided to specified scheduling lists of queues while minimizing cell latency through the network switch.
  • the pace counter in conjunction with the pace limit is employed to permit overallocation of SAT entries to reduce the latency for cells dispatched from the respective scheduling list while preventing a scheduling list from obtaining more than its allocated bandwidth. Latency, or delay through the switch, is a function of the amount of bandwidth allocated for a given queue or group of queues on a scheduling list.
  • Latency is reduced by assigning more, generally evenly spaced, SAT entries for a given scheduling list and only allowing a cell to be dispatched for a particular scheduling list following retrieval of at least a predetermined number of occurrences of the respective scheduling list number in the respective SAT as explained with greater particularity below. More specifically, a pace limit and a pace counter are associated with each scheduling list.
  • a scheduling list descriptor such as scheduling list descriptor 70
  • the Scheduling List Descriptor Table 72 contains all of the scheduling list descriptors for the scheduling lists assigned for the respective SAT.
  • the pace limit comprises a value which, in the present embodiment, is stored in a 10 bit wide pace limit field within the scheduling list descriptor.
  • the pace counter is stored in another 10 bit wide pace counter field of the scheduling list descriptor.
  • the pace limit specifies the number of SAT entries for a particular scheduling list number to be skipped when making allocated requests for scheduling list numbers that are overallocated.
  • the pacing mechanism is employed when the number of SAT entries allocated to a scheduling list is greater than the number of SAT entries needed for the allocated bandwidth requested. Assuming for purposes of discussion that a particular scheduling list has been allocated 32 SAT entries to achieve a specific delay, but only needs four entries to achieve its requested bandwidth, the pace limit is set to 7 and the pace counter is set to zero.
  • the pace counter is set to 0 remains at equal to 0 until a cell is dispatched.
  • the pacing mechanism may be disabled by setting the pace limit field equal to 0. Setting the pace limit field equal to 0 will cause every valid SAT entry for the respective scheduling list to make a request for allocated bandwidth if there is a cell available for transmission from the respective scheduling list.
  • the pace counter When the SAT index counter points to a SAT entry for the respective scheduling list, if the pace counter is equal to zero, and if the list contains no cells for dispatch, nothing is done to the pace counter and the time slot is given up to dynamic bandwidth by signalling the bandwidth arbiter. Thus, after the pace counter has been initialized to zero it remains at zero until a cell is dispatched.
  • the pace counter Upon shipping a cell to the data switch 10 of the switch fabric 9, the pace counter is set to the value specified by the pace limit. Each successive time the respective SAT entry points to the respective scheduling list, the pace counter is tested to determine if it equals zero. If the pace count does not equal zero, the pace counter is decremented and the timeslot is assigned to dynamic bandwidth. After decrementing the pace counter, if the pace counter equals 0 and a cell is enqueued on the scheduling list for dispatch, the cell is dispatched to the data switch 10 of the switch fabric 9 and the pace counter is preset to the pace limit.
  • the pace counter is equal to zero, and no cell is enqueued on the respective scheduling list, the pace counter remains at zero until a cell is enqueued on the respective scheduling list. Such a cell will then be dispatched upon retrieval of the next SAT entry for the respective scheduling list. Following dispatch of the cell the pace counter is again set to the pace limit.
  • the presently disclosed pacing method is further illustrated with reference to the flowchart of Fig. 4. The same method is employed in each of the TSPPs for each of the respective SATs.
  • the SAT index counters are incremented as indicated in step 100 to point to the next entry in the respective SAT.
  • the respective SAT entry is read and, as indicated in step 104, the SAT entry accessed in step 102 is tested to ascertain whether the retrieved entry corresponds to a valid scheduling list.
  • the respective SAT timeslot is assigned to Dynamic Bandwidth.
  • the Bandwidth Arbiter is signaled with respect to the availability of the respective timeslot and as indicated in step 100, the SAT index counter is incremented on the next cell clock.
  • step 104 determines if a cell associated with the respective scheduling list is queued for dispatch. If no cell is queued for dispatch, as indicated in step 110, the pace counter is tested to determine if the counter value equals 0. If the counter value equals 0, the counter value is left unchanged and the respective SAT timeslot is assigned to dynamic bandwidth as illustrated in step 106. The SAT index counters are then incremented upon the arrival of the next cell clock as indicated in step 100. If the test of the pace counter in step 110 reveals that the pace counter is not equal to 0, as indicated in step 112, the pace counter is decremented and the respective SAT timeslot is assigned to dynamic bandwidth as illustrated in step 106. The SAT index counters are then incremented upon the arrival of the next cell clock.
  • step 108 If the test of step 108 reveals that a cell associated with the respective scheduling list is queued for transmission, the pace counter is tested to determine if the counter value equals 0 as illustrated in step 114. If the pace counter is not equal to zero, an enqueued cell for the respective scheduling list is not dispatched to the switch fabric and, as indicated in step 112, the pace counter is decremented. Following the decrementing of the pace counter in step 112, the respective SAT timeslot is assigned to dynamic bandwidth as depicted in step 106. The SAT index counters are then incremented upon the arrival of the next cell clock as illustrated in step 100.
  • the pace counter is preset to the pace limit as illustrated in step 118.
  • the SAT index counter is incremented upon the arrival of the next cell clock. The foregoing method is applied in parallel for each of the SAT's associated with the respective TSPP's 14.
  • the first cell that is scheduled for dispatch will be forwarded to the switch fabric upon recognition of the next SAT entry for the respective scheduling list when the pace counter is equal to 0.
  • the pace counter is decremented each time the respective SAT entry is recognized (unless it is already equal to 0)
  • an arriving cell is more likely (depending upon the SAT entry assignments) to arrive at a time when the pace counter has been decremented to zero thereby permitting the cell to be dispatched upon recognition of the next SAT entry for the respective scheduling list. Since the SAT entries employing the present pacing technique occur more frequently than would occur without the overallocation of bandwidth within the SAT, average cell latency is shorter than would be experienced in a system employing a SAT without the present pacing technique.
  • the presently disclosed pacing mechanism also allows assignment of bandwidth to a scheduling list less than that which would be assignable without this mechanism.
  • the minimum increment of bandwidth assignable in a system using a switch allocation table for bandwidth allocation corresponds to the bandwidth assignable in one time slot within the table.
  • Latency may be further reduced by overallocating bandwidth to the SAT table for the specified scheduling list.
  • latency may be reduced by assigning the specified scheduling list number to 2 SAT entries within the SAT table and setting the pace limit to 3. In this circumstance, cells would be dispatched every 2 SAT table cycles, however, once the pace counter counted down to 0, the latency would be no more than the time to cycle through 1/2 of the SAT table.

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Abstract

L'invention porte sur un procédé et un appareil d'attribution de largeur de bande dans un commutateur de réseau présentant plusieurs ports d'entrée (14) couplés à autant de ports de sortie (16) par l'intermédiaire d'un dispositif de commutation (9) afin d'assurer qu'un minimum de largeur de bande soit assigné à des listes de planification données. Une table d'attribution des commutations est fournie pour chacun des différents ports d'entrée. Chacune de ces tables, du type circulaire, est indexée séquentiellement à l'aide d'un compteur d'indices associé. Les différentes entrées de la table d'attribution des commutations comprennent des numéros de table de programmation qui servent à identifier les cellules demanderesses de largeur de bande de commutation. Les différents compteurs d'indices sont synchronisés de manière à ce que chacune des tables d'attribution de commutation présente une entrée correspondante sélectionnée. La quantité de largeur de bande et le retard dans la commutation du réseau sont établis pour chacune des différentes tables d'attribution de commutation de programmation. Le délai d'attente dû à la commutation du réseau peut être sensiblement réduit par l'utilisation d'un compteur de cadence et d'une limite de cadence, qui, en association avec la table d'attribution des commutations, déterminent si une cellule associée à une table de programmation particulière peut passer par l'intermédiaire du dispositif (9) de commutation en vue de sa transmission sur une ligne du réseau via au moins l'un des ports de sortie (16).
PCT/US1996/011964 1995-07-19 1996-07-18 Controle des attributions de largeur de bande a l'aide d'un compteur de cadence WO1997004570A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU65036/96A AU6503696A (en) 1995-07-19 1996-07-18 Controlling bandwidth allocation using a pace counter
JP9506067A JPH11510324A (ja) 1995-07-19 1996-07-18 ペースカウンタを用いた帯域幅割付けの制御
PCT/US1996/011964 WO1997004570A1 (fr) 1995-07-19 1996-07-18 Controle des attributions de largeur de bande a l'aide d'un compteur de cadence

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US149895P 1995-07-19 1995-07-19
US60/001,498 1995-07-19
PCT/US1996/011964 WO1997004570A1 (fr) 1995-07-19 1996-07-18 Controle des attributions de largeur de bande a l'aide d'un compteur de cadence

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WO1997004570A1 true WO1997004570A1 (fr) 1997-02-06

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EP1170906B1 (fr) * 2000-07-05 2005-12-21 Roke Manor Research Limited Améliorations dans ou pour des dispositifs de commutation

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5465331A (en) * 1992-12-23 1995-11-07 International Business Machines Corporation Apparatus having three separated and decentralized processors for concurrently and independently processing packets in a communication network
US5499238A (en) * 1993-11-06 1996-03-12 Electronics And Telecommunications Research Institute Asynchronous transfer mode (ATM) multiplexing process device and method of the broadband integrated service digital network subscriber access apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5465331A (en) * 1992-12-23 1995-11-07 International Business Machines Corporation Apparatus having three separated and decentralized processors for concurrently and independently processing packets in a communication network
US5499238A (en) * 1993-11-06 1996-03-12 Electronics And Telecommunications Research Institute Asynchronous transfer mode (ATM) multiplexing process device and method of the broadband integrated service digital network subscriber access apparatus

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AU6503696A (en) 1997-02-18
JPH11510324A (ja) 1999-09-07

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