WO1997001888A1

WO1997001888A1 - Transmission system with improved decoding of a block code

Info

Publication number: WO1997001888A1
Application number: PCT/IB1995/000523
Authority: WO
Inventors: Volker Braun
Original assignee: Philips Electronics N.V.; Philips Norden Ab
Priority date: 1995-06-27
Filing date: 1995-06-27
Publication date: 1997-01-16

Abstract

In a transmission system or a recording system codes are often used to make the coded signal (Ck) DC free. To simplify the detector (16), block codes can be preferable. To exploit the redundancy inherently present in such a code a symbol wise Viterbi detector (24, 26) is used to detect the symbols without largely enlarging the complexity of the system.

Description

"Transmission system with improved decoding of a block code"

The invention is related to a transmission system comprising a transmitter for deriving words of coded data symbols from input data symbols, and for applying a coded signal derived from the words of coded data symbols to a transmission channel, a receiver for receiving the coded signal from the transmission channel comprising a decoder for deriving said words of coded data symbols from the received coded signal

The invention is also related to a recording system and a receiver.

A transmission system according to the preamble is known from US patent No. 4,620,311.

Such transmission system can e.g. be applied for the transmission of digital symbols via the public telephone network, for the transmission of multiplex signals between exchanges or for the transmission of digital signals in mobile radio systems. Said recording systems can be used for the recording and reproduction of digital symbols using magnetic tapes or magnetic discs such as hard discs or floppy discs. Said recording system can also be used with optical or opto-magnetic discs.

In order to transmit the input data symbols via the transmission channel, said input data symbols are often transformed into coded data symbols by the transmitter. Coding is performed in order to obtain certain desired properties of the frequency spectrum of the coded signal. An often desired property of the frequency spectrum of the coded data signal is that it does not contain any DC component, because a number of common transmission channels are not able to pass DC. Another reason for coding the input signal is to obtain the possibility of correction of transmission errors. These transmission errors can be caused by thermal noise and all kinds of interference.

To enable the use of an relatively easy decoder often so-called block codes are used. In such a block code, words of input data symbols are transformed into words of coded data symbols. In the block code according to the above mentioned US patent, the words of input data symbols comprise 8 bits, and the block of coded data symbols comprises 10 bits.

In the prior art system the words of coded data symbols are derived from the coded data signal by slicing said coded data signal. In this way an optimum performance can not be obtained because the redundancy present in the words of coded symbols is not exploited for reduction of the error rate.

The object of the present invention is to provide a transmission system in which the redundancy present in the coded data words is exploited to reduce the error rate.

Therefor the transmission system according to the invention is

characterised in that the decoder is arranged for determining a most likely word of coded data by symbol like expanding candidate words of coded data symbols using likelihood measures corresponding to each of said candidate words of coded data symbols, each likelihood measure being derived from the received coded signal.

By determining the most likely codeword by symbol like expansion candidate words of coded data symbols having an associated probability measure, the redundancy inherently present in the words of coded data symbols is utilised. A straightforward way to exploit the redundancy in the words of coded symbols would be the use of a word wise Viterbi detector. For the code according to the above mentioned US patent, 423 different words of coded data symbols exist. If it is assumed that the two most likely sequence of words of coded data symbols are determined, the calculation of the probability measure of said sequence would require n additions for each distinct word of coded data symbols. If n is equal to 10, 4230 additions would be required.

If symbol like extension of the candidate words of coded data symbols is used, only a few distinct extensions are possible. If the number of candidate sequences is equal to 3, the possible number of extensions is never more than 6 if binary symbols are used. In most cases this number is even lower due to the impossibility of some transitions. With 5 possible transitions, the total number of additions required for calculating the probability measures is 50, being substantially lower than the 4230 additions needed if a word wise detection is used.

It is observed that in the paper "On the Performance of a Rate 8/10

Matched Spectral Null Code for Class-4 Partial Response" in IEEE Transactions on

Magnetics, vol. MAG-28, No. 5, pp 2883-2888, September 1992, a Viterbi detector having a reduced complexity with respect to a word wise Viterbi detector is disclosed. However this reduced complexity Viterbi detector does not make use of symbol wise detection of the received signal, according to the present invention.

An embodiment of the invention is characterised in that a running digital sum of the coded data symbols is bounded between a finite minimum and maximum value, and in that the number of candidate words of coded data symbols is smaller than or equal to the number N of different values of the running digital sum, and in that each candidate word of coded data symbols corresponds to a different value of the running digital sum.

A large class of DC free codes are designed to keep a so called running digital sum within specified bounds. The running digital sum RDS is defined as the sum of all past symbol values, under the assumption that the symbols can assume positive and negative values.

A possible choice of the number of candidate words of coded data symbols is smaller or equal to the number of different values for the running digital sum. An equal number of candidate words of coded symbols and running digital sum values is possible if all values of the running digital sum are possible at all instants. This will be in general the case for ternary codes such as the FOMOT code. The FOMOT code is disclosed in US patent 4,606,028. When e.g. binary codes are used, such as the code disclosed in US patent 4,620,311 it is not always possible to obtain all values of the running digital sum at all instants.

A further embodiment of the invention is characterised in that said coded data symbols are binary, in that the number of candidate words of coded data symbols is equal to N/2 if N is even, and in that the number of candidate words of coded symbols is equal to (N+1)/2 if N is odd.

If the coded data symbols are binary the running digital sum will always change after adding a new symbol. In the code according to US patent 4,620,311 the value of the running digital sum for the candidate words of coded data symbols after adding a symbol differs from all values of the running digital sum of the previous candidate words of coded symbols. If N is even then only N/2 candidate words of coded data symbols are possible. If N is odd, the number of candidate words of coded data symbols toggles between (N+1)/2 and (N-l)/2. Using this recognition it is possible to reduce the number of words of candidate coded symbols substantially, resulting in a decreased complexity of the system.

A further embodiment of the invention is characterised in that the decoder is arranged for increasing the number of candidate sequences by the construction of the candidate sequences after the beginning of a new codeword., or in that the decoder is arranged for decreasing the number of candidate sequences at appending the final symbol to the candidate words of coded symbols.

Some codes have a limited number of values of the running digital sum at the boundaries of words of coded data symbols. In order to deal with such codes the decoder is arranged to increase the number of candidate words of coded data symbols after the beginning of a new word of coded data symbols and/or to decrease the number of candidate words of coded data symbols at appending the final symbol to a candidate words of coded data symbols.

The present invention will now be explained with reference to the drawings, in which the same elements are indicated with the same reference number. Herein shows:

Fig. 1, a transmission system according to the present invention;

Fig. 2, a recording system according to the present invention;

Fig. 3, an implementation of the detector 16 in Fig. 1 and Fig. 2;

Fig. 4, a trellis diagram of the 8/10 ETM code, used in the systems according Fig. 1 and Fig. 2;

Fig. 5, a reduced state trellis diagram of the 8/10 ETM code, used in the systems according Fig. 1 and Fig. 2;

Fig. 6, a trellis diagram of a code having an odd number of possible running digital sum values;

Fig. 7, a reduced state trellis diagram of the code according to the trellis diagram according to Fig. 6;

Fig. 8, a trellis diagram for the so called FOMOT code;

Fig. 9, a flow diagram of a program for the processor 24 to detect a received signal coded using a code having a trellis according to Fig. 4.

Fig. 10, a flow diagram of a program for the processor 24 to decode a received signal using the reduced state trellis according to Fig. 5.

Fig. 11, a flow diagram of a program for the processor 24 to decode a received signal coded using the FOMOT code having a trellis according to Fig. 4.

In the transmission system according to Fig. 1, the input data symbols ai are applied to the transmitter 2. In said transmitter 2 the input data symbols % are applied to an input of a series to parallel converter 4. The outputs of the series to parallel converter 4 is connected to corresponding inputs of a block coder 6. The outputs of the block coder 6 are connected to inputs of a parallel to series converter 8. The output of the parallel to series converter 8 carrying output symbols c_k constitutes the output of the transmitter 2.

The output of the transmitter 2 is coupled to an input of the receiver 12 via the transmission channel 10. In the receiver 10, the output signal s(t) of the transmission channel is applied to a sampling circuit 14, and to a clock recovery arrangement 18. An output signal of the clock recovery arrangement 18 is connected to a clock input of the sampling circuit 14. The output of the sampling circuit 14 with output signal s_k is connected to an input of a detector 16. The output of the detector 16, carrying the output data symbols a,.

In the explanation of the transmission system according to Fig. 1 it is assumed the a 8/10 bit block code is used. The input symbols a_! are transformed into words of 8 bits by -the series parallel converter 4. The coder 6 transforms the words of 8 bits at its inputs into 10 bit words of coded data symbols at its output. Each of said 10 bits words of coded data symbols is converted into a sequence of data symbols c_k by the parallel series converter 8. The sequence of data symbols c_k constitutes the coded signal.

The output signal s(t) of the transmission channel 10 is filtered and subsequently sampled with a sampling rate proportional to the symbol rate on the transmission channel 10 by the sampling circuit 14. The timing signal for the sampling circuit 14 is derived from the signal s(t) by the timing recovery arrangement 18. The detector 16 derives the words of coded data symbols from the samples s_k according the invention.

In the recording system according to Fig. 2, the construction of the transmitter 2 and the receiver 12 is in principle the same as the construction of the transmitter 2 and receiver 12 according to Fig. 1. Only the transmission channel 10 is replaced by a recording and play back arrangement 20. The recording arrangement can comprise a write head energized by the coded data signal which records the coded signal on a magnetic tape. The play back arrangement can comprise a read head which transforms the recorded signal into an electric signal s(t).

In the detector 16 according to Fig. 3 the sampled signal s_k is applied to an analog to digital converter 23. The output of the analog to digital converter 23 with output signal r_k is connected to a first input of a processor 24, and to an input of a word

synchroniser 25. An output of the word synchroniser 25 is connected to a second input of the processor 24. The processor 24 is also coupled to a memory unit 26. An output of the processor 24 with output symbols c_k is coupled to a decoder 28. At the output of the decoder 28 the output symbols a, are available.

The analog samples s_k are transformed into digital samples r_k by means of the analog to digital converter 23. Because the used code is a block code, word

synchronisation has to be obtained, to be able to obtain proper detection at the boundaries between two subsequent words. Therefor the word synchroniser detects the presence of a synchronisation word in a preamble of the received data symbols, and generates a reference pulse at the moment the synchronisation word has been detected. This reference pulse is used to initialise the decoding process in the processor 24. The decoding is performed by the processor 24 under control of a suitabl control program which will be discussed later. The memory unit 26 is used to store the control program and the intermediate results needed in the detection process, at an output of the processor 24, symbols ĉ_i of the decoded data. The decoder 28 transforms the words of coded data symbols ĉ_i into a replica â_l of the input symbols.

In the trellis according to Fig. 4 it is assumed that the received word of coded data symbols can start from two possible state differing in the value of the running digital sum. Each of the subsequent symbols â_i in the word of coded data symbols can assume a value +1 or -1 under the restriction that the running digital sum remains between 3 and +2. At adding the final symbol to a word of coded data symbols, the number of running digital sum values is again reduced to two.

If it is assumed that the likelihood measures of the candidate codeword, also called state metrics of the two originating states are equal to g₀ ^-1 and g₀ ⁺¹ respectively (i=0) , for the state metrics g₁ ⁺², g₁ ⁰, and g₁ ^{- 2} (i=1) can be found by adding the corresponding path metric (r_{i+ 1}-c_i+1)² to the state metrics of the originating states:

.

To simplify (1), (2) and (3) the metrics gf are replaced by metrics f_i ^x. Therefor the relation between g_i ^x and f_i ^x is defined as:

Using (4), (1), (2), and (3) change into:

For the relation between the originating state metrics and the new state metrics for a transition from the states for i is odd to the states for i is even, can be written:

Transforming the metrics g_i ^x into the metrics f_i ^x by using (4) changes (8), (9) and (10) into:

For the relation between the state metrics of the originating states and of the new states for the transition from the states for i is even to the states for i is odd, it can be found in the same way:

For the values of the new state metrics at the transitions from the states for i=9 to the final states (i=10) of the trellis according to Fig. 4 can be written:

The trellis according to Fig. 5 is derived from the trellis according to Fig. 4 by transforming the states for i is odd and the states for i is even into new states A, B and C. Using the same derivation as was used in respect of the trellis according to Fig. 4, for the transition between the initial states A, B and the states A,B, and C for i=l, the following path metrics can be found:

For the transition from the states for i is odd to the states for i is even, it can be written:

For the transition from the states for i is even to the states for i is odd, it can be written:

)

For the transitions to the final states (i=10) of the trellis according to Fig. 5 from the states for i =9 can be written:

Fig. 6 shows the trellis for a code having an odd number of possible running digital sum values. Due to the similarity with the trellis according to Fig. 4, the expressions for the state metrics are also very similar. They can easily be derived using the method which was explained with respect to the trellis according to Fig. 4.

In the reduced state trellis according to Fig. 7 corresponding to the trellis according to Fig. 6 it can be seen that the number of states for even is one more than the number of states for odd i. Otherwise the trellis of Fig 7 corresponds to the trellis according to Fig. 5. Consequently the equations for determining the state metrics need to be adapted slightly to take the additional state into account.

In the trellis of the ternary FOMOT code according to Fig. 8 it can be seen that this code has four initial states, and four final stages. The number of intermediate stages is equal to six. From each state a transition to three new states is possible, depending on the value of the appended symbol â_k (-1, 0, + 1). For the values of the state metrics g at the transition from i=0 to 1 can be written:

.

;

Transforming the metrics g_i ^x into the metrics f_i ^x using (4) changes (30) to (35) into:

For the new values of the state metrics after the transition from i=1 to i=2 easily can be found:

For the transitions to the final states (i=3) of the trellis according to Fig. 8 from the states for i=2 can be written:

It is observed that the expressions derived for the relation between the new state metrics g_i+1 ^q and g_i ^p can be expressed in a more general form:

In (46) p and q are the running digital sum values for the corresponding state metrics. (46) has to be evaluating for all existing combinations of p and q as follows from the trellis diagram. To avoid the necessity of calculation a similar transformation as is given by (4) can be performed.

In the flow diagram according Fig. 9 the instructions have the significa- tion according to the table given below.

The flow diagram according Fig 9 shows a program to implement a detector for a code having a trellis according to Fig. 4. In the explanation of the flow diagram according to Fig. 9 it is assumed that the variables f correspond to the state metrics, and the variables s correspond to the most likely sequence of symbols leading to said state. The variable f has a single value, and the corresponding variable s is a ( finite length ) shift register like data structure at which symbol values are appended at updating.

In instruction 30 the program is started. In instruction 32 is waited until the word synchroniser 25 generates a pulse signifying that word synchronisation has been achieved. In instruction all state variables are initialised to a predetermined value, e.g. zero. In instruction 36 a counter i which counts the position in the trellis according to Fig. 4 is set to the value 0. In instruction 38 a value r_i+1 is read from the A/D converter 23.

In instruction 40, the state metrics f², f⁰, and f² are updated according to (5), (6), and (7). s² is extended by + 1 and s^-2 is extended by -1. s⁰ is extended by + 1 if the path originating in f^-1 and ending in f⁰ is the surviving path. s⁰ is extended by -1 if the path originating in f^4-1 and ending in f⁰ is the surviving path. The surviving path is defined as the path trough the trellis whose metric is chosen to be optimal.

In instruction 42 the value of i is incremented, and in instruction 44 the next value of r_i+1 is read. In instruction 46 the state metrics f¹, f ^{- 1}, and f^-3 are updated according to (11), (12), and (13). s¹ is extended by + 1 if the path originating in f⁰ is the surviving path, s¹ is extended by -1 if the path originating in f^{+ 2} and ending in f¹ is the surviving path, s^-1 is extended by + 1 if the path originating in f^-2 is the surviving path, and s^-1 is extended by -1 if the path originating in f⁰ is the surviving path, s^-3 is extended with - 1.

In instruction 48 the value of i is incremented, and in instruction 50 the next value of r_i+1 is read. In instruction 52 the state metrics f², f⁰, and f² are updated according to (14), (15), and (16). s⁺² is extended by +1. s⁰ is extended by +1 if the path originating in f^1-1 is the surviving path, and s⁺² is extended by -1 if the path originating in f-¹ is the surviving path, s^-2 is extended by + 1 if the path originating in f^{- 3} is the surviving path, and s^-2 is extended by -1 if the path originating in f^-1 is the surviving path.

In instruction 54 the value of i is incremented, and in instruction 56 the next value of r_i+1 is read. In instruction 58 it is tested whether the value of i is equal to 9. if this is the case, the one but last states of the trellis according to Fig. 4 has been reached, and the number of states has to be reduced. Otherwise the program is continued at instruction 46.

In instruction 60 the state metrics f⁺¹ and f^-1 are updated according to (17) and (18). s¹ is extended by +1 if the path originating in f⁰ is the surviving path, s¹ is extended by -1 if the path originating in f⁺² is the surviving path, s^-1 is extended by +1 if the path originating in f^-2 is the surviving path, and s^-1 is extended by -1 if the path originating in f⁰ is the surviving path.

In instruction 62 the next word detected is output. This word contains the last 10 symbol values of one of the data structures s. If the memory length of the data structures s is long enough ( a few number of words ), the paths trough the trellis tend to merge to only one path having the oldest symbol values in common. These oldest symbol values constitute the outputted word.

In the flow diagram according Fig. 10 the instructions have the signification according to the table given below.

The flow diagram according Fig 10 shows a program to implement a detector for a code having a reduced state trellis according to Fig. 5. In the explanation of the flow diagram according to Fig. 10 the same is assumed for the variables f and s corresponding to the flow diagram according to Fig. 9.

In instruction 64 the program is started. In instruction 66 is waited until the word synchroniser 25 generates a pulse signifying that word synchronisation has been achieved. In instruction 68 all state variables are initialised to a predetermined value, e.g. zero. In instruction 70 a counter i which counts the position in the trellis according to Fig. 5 is set to the value 0. In instruction 72 a sample r_i+1 is read from the A/D converter 23.

In instruction 74, the state metrics f^A, f^B, and f^C are updated according to (19), (20), and (21). s^A is extended by +1 and s^C is extended by -1. s^B is extended by +1 if the path originating in f^B is the surviving path. s^B is extended by -1 if the path originating in f^A is the surviving path.

In instruction 76 the value of i is incremented, and in instruction 78 the next value of r_i+1 is read. In instruction 80 the state metrics f^A, f^B, and f^C are updated according to (22), (23), and (24). s^A is extended by +1 if the path originating in f⁸ is the surviving path, and s^A is extended by -1 if the path originating in f^A is the surviving path. s^B is extended by +1 if the path originating in f^C is the surviving path, and s^B is extended by -1 if the path originating in f^B is the surviving path. s^C is extended with -1.

In instruction 82 the value of i is incremented, and in instruction 84 the next value of r_i+1 is read. In instruction 86 the state metrics f^A, f⁸, and f ^C are updated according to (25), (26), and (27). s^A is extended by + 1. s^B is extended by + 1 if the path originating in f^B is the surviving part, and s^B is extended by -1 if the path originating in f^A is the surviving path. s^c is extended by + 1 if the path originating in f^C is the surviving path, and s^C is extended by -1 if the path originating in f ^C is the surviving path.

In instruction 88 the value of i is incremented, and in instruction 90 the next value of r_{i+ 1} is read. In instruction 92 it is tested whether the value of i is equal to 9. If this is the case, the one but last states of the trellis according to Fig. 5 has been reached, and the number of states has to be reduced. Otherwise the program is continued at instruction 80.

In instruction 94 the state metrics f^A and f^B are updated according to (28) and (29). s^A is extended by +1 if the path originating in f^B is the surviving path, s¹ is extended by -1 if the path originating in f^A is the surviving path. s^B is extended by +1 if the path originating in f^C is the surviving path, and s^B is extended by -1 if the path originating in f⁸ is the surviving path.

In instruction 96 the next word detected is output. This word contains the last 10 symbol values of one of the data structures s. Using the reduced state metric results in a saving of memory capacity to store the state metrics and the corresponding sequence of symbols.

In the flow diagram according Fig. 11 the instructions have the signification according to the table given below.

The flow diagram according Fig 11 shows a program to implement a detector for the ternary FOMOT code having a trellis according to Fig. 8. In instruction 98 the program is started. In instruction 100 is waited until the word synchroniser 25 generates a pulse signifying that word synchronisation has been achieved. In instruction 102 all state variables are initialised to a predetermined value, e.g. zero. In instruction 104 a value r_i+1 is read from the A/D converter 23.

In instruction 106, the state metrics f²,f¹,f⁰,f¹,f ² and f³ are updated according to (36), (37), (38), (39), (40) and (41). s² is extended by + 1 and s^-3 is extended by -1. s¹ is extended by 0 if the surviving path originates in f¹ and is extended by +1 if the surviving path originates in f⁰. s⁰ is extended by + 1 if the path originating in f^-1 is the surviving path, s⁰ is extended by -1 if the path originating in f^1-1 is the surviving path and s⁰ is extended by 0 if the path originating at f⁰ is the surviving path.

s^-1 is extended by + 1 if the path originating in f^-2 is the surviving path, s-¹ is extended by -1 if the path originating in f⁰ is the surviving path and s^-1 is extended by 0 if the path originating at f ¹ is the surviving path, s^-2 is extended by 0 if the surviving path originates in f^{- 2} and is extended by -1 if the surviving path originates in f^-l.

In instruction 108 the next value of r_{i+ 1} is read. In instruction 110 the state metrics f^-3-f⁺² are updated according to (42), (43), and (44). s² is extended by +1 if the path originating in f¹ is the surviving path, and s¹ is extended by 0 if the path originating in f⁺² is the surviving path. For q having values -2, -1,0, + 1 s^q is extended by +1 if the path originating in f^{q -1} is the surviving path, s^q is extended by -1 if the path originating in f^q+1 is the surviving path and s^q is extended by 0 if the path originating at f^q is the surviving path, s^-3 is extended by -1 if the path originating in f^-2 is the surviving path, and s^-3 is extended by 0 if the path originating in f^-2 is the surviving path.

In instruction 112 the next value of r_i+1 is read. In instruction 114 the state metrics f², f^-1, f⁰, f⁺¹ and f⁺² are updated according to (45). For q having values -2, -1,0, + 1 s^q is extended by + 1 if the path originating in f^q-1 is the surviving path, s^q is extended by -1 if the path originating in f^q+1 is the surviving path and s^q is extended by 0 if the path originating at f^q is the surviving path.

It is observed that the invention is described by referring to a detector having an sapled continuous input signal r_i. It is conceivable that the invention is applied to a decoder having as input signal a hard limited version of the signal r_i.

Claims

1. Transmission system comprising a transmitter (2) for deriving words of coded data symbols from input data symbols, and for applying a coded signal derived from the words of coded data symbols to a transmission channel (10), a receiver (12) for receiving the coded signal from the transmission channel comprising a decoder (16) for deriving said words of coded data symbols from the received coded signal, characterised in that the decoder (16) is arranged for determining a most likely word of coded data by symbol like expanding candidate words of coded data symbols using likelihood measures corresponding to each of said candidate words of coded data symbols, each likelihood measure being derived from the received coded signal.

2. Transmission system according to claim 1, characterised in that a running digital sum (RDS) of the coded data symbols is bounded between a finite minimum (-1) and maximum value (+2), and in that the number of candidate words of coded data symbols is smaller than or equal to the number N of different values of the running digital sum, and in that each candidate word of coded data symbols corresponds to a different value of the running digital sum.

3. Transmission system according to claim 2, characterised in that said coded data symbols are binary, in that tiie number of candidate words of coded data symbols is equal to N/2 if N is even, and in that the number of candidate words of coded symbols is equal to (N+1)/2 if N is odd.

4. Transmission system according to claims 2 or 3, characterised in that the decoder (16) is arranged for increasing the number of candidate sequences by the construction of the candidate sequences after the beginning of a new codeword.

5. Transmission system according to claim 4, characterised in that the decoder (16) is arranged for decreasing the number of candidate sequences at appending the final symbol to the candidate words of coded symbols.

6. Recording system comprising a transmitter (2) for deriving words of coded data symbols from input data symbols, and for applying a coded signal derived from the words of coded data symbols to a recording medium (20), a receiver (12) for receiving a coded signal from the recording medium (20), said receiver comprising a decoder (16) for deriving said words of coded data symbols from the received coded signal, characterised in that the decoder (16) is arranged for determining a most likely word of coded data by symbol like expanding candidate words of coded data symbols using likelihood measures corresponding to each of said candidate words of coded data symbols, each likelihood measure being derived from the received coded signal.

7. Recording system according to claim 6, characterised in that a running digital sum (RDS) of the coded data symbols is bounded between a finite minimum and maximum value, and in that the number of candidate words of coded data symbols is smaller than or equal to the number N of different values of the running digital sum, and in that each candidate word of coded data symbols corresponds to a different value of the running digital sum.

8. Receiver (12) for receiving a block coded signal, said receiver (12) comprising a decoder (16) for deriving said words of coded data symbols from the received coded signal, characterised in that the decoder (16) is arranged for determining a most likely word of coded data by symbol like expanding candidate words of coded data symbols using likelihood measures corresponding to each of said candidate words of coded data symbols, each likelihood measure being derived from the received coded signal.

9. Receiver according to claim 8, characterised in that a running digital sum of the coded data symbols is bounded between a finite minimum and maximum value, and in that the number of candidate words of coded data symbols is smaller than or equal to the number N of different values of the running digital sum, and in that each candidate word of coded data symbols corresponds to a different value of the running digital sum.

10. Receiver according to claim 9, characterised in that said coded data symbols are binary, in that the number of candidate words of coded data symbols is equal to N/2 if N is even, and in that the number of candidate words of coded symbols is equal to (N+1)/2 if N is odd.