WO1996039012A1 - Electrical connection - Google Patents

Electrical connection Download PDF

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Publication number
WO1996039012A1
WO1996039012A1 PCT/US1996/008223 US9608223W WO9639012A1 WO 1996039012 A1 WO1996039012 A1 WO 1996039012A1 US 9608223 W US9608223 W US 9608223W WO 9639012 A1 WO9639012 A1 WO 9639012A1
Authority
WO
WIPO (PCT)
Prior art keywords
pin
transmission line
circuit board
integrated circuit
electrical connection
Prior art date
Application number
PCT/US1996/008223
Other languages
French (fr)
Inventor
Scott B. Doyle
Original Assignee
The Whitaker Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by The Whitaker Corporation filed Critical The Whitaker Corporation
Publication of WO1996039012A1 publication Critical patent/WO1996039012A1/en

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0243—Printed circuits associated with mounted high frequency components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6616—Vertical connections, e.g. vias
    • H01L2223/6622—Coaxial feed-throughs in active or passive substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
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    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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    • H01L2924/30107—Inductance
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0272—Adaptations for fluid transport, e.g. channels, holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09581—Applying an insulating coating on the walls of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09809—Coaxial layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10969—Metallic case or integral heatsink of component electrically connected to a pad on PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3447—Lead-in-hole components

Definitions

  • an electronic component comprises, an integrated circuit within a package, and at least one conducting pin projecting from the package for connection to a circuit board.
  • the integrated circuit is electrically connected to the pin, for example, by a bond wire.
  • the pin has been directly connected to a transmission line on the circuit board.
  • Such a connection can limit the maximum frequency in which signals may be transmitted, due to the inductance of the connection and signal attenuation at high frequency, for example, 5-8 dB at 25-30 GHz.
  • an integrated circuit package is constructed with a pin that has a coaxial construction within the package. A tip of the pin projects outwardly from the coaxial construction for plugging into a circuit board or into a stack of integrated circuit packages. The projecting tip of the pin may also be plugged into an electrical socket.
  • an electrical connection between a transmission line and an integrated circuit package comprises a circuit board on which are mounted the transmission line and the integrated circuit package, the transmission line comprising a ground feed connected to a ground plane on the circuit board and a feed connected to the pin of an integrated circuit package with a dielectric material surrounding the pin between the feed of the transmission line and the integrated circuit package.
  • the pin extends in a through-hole through the circuit board and dielectric material is contained within the through-hole.
  • a portion of a pin that projects from an integrated circuit package extends in a through-hole together with dielectric material surrounding the pin, and a layer of conducting material in the through-hole advantageously provides improved electrical performance along a projecting portion of the pin.
  • the transmission line comprises a waveguide transmission line connected to the pin, and the pin is an E-plane probe within a cavity of the waveguide transmission line.
  • An advantage resides in adapting a projecting pin of an integrated circuit package into an E-plane probe.
  • the circuit board extends between the transmission line and the integrated circuit package, and the projecting portion of the pin extends through the circuit board together with the dielectric material surrounding the pin.
  • An advantage resides in adding a through-hole of a circuit board with a construction to improve the electrical performance of a connection of a projecting portion of a pin on an integrated circuit package.
  • Figure 1 is a cross-section view illustrating the construction of one preferred embodiment of an electronic device made according to the present invention.
  • Figure 2 is a cross-section view illustrating the construction of another preferred embodiment of a device made according to the present invention.
  • Figure 3 is a cross-section view illustrating the construction of yet another preferred embodiment of a device made according to the present invention.
  • Figure 4 is a cross-section view illustrating the construction of still another, preferred embodiment of a device made according to the present invention.
  • Figure 5 is a cross-section view illustrating the construction of another preferred embodiment of a device made according to the present invention.
  • Figure 6 is a block diagram showing the steps of one preferred embodiment of the method of the present invention for use in producing the device of Figure 3.
  • Figure 1 is a cross-section view of one preferred embodiment (100) of an electronic device made according to the present invention.
  • Device (100) comprises a first electronic component which in this embodiment is an integrated circuit package (10) , mounted to a second electronic component which in this embodiment is a printed circuit board (12) , via an electrically conductive pin (14) .
  • Integrated circuit chip (15) of the package (10) is mounted by conventional means to the header substrate (e.g., made of a material having a relatively low coefficient of thermal expansion, such as rolled steel or KovarT material, and having a thickness of about 0.06 in. (20), and the chip (15) is electrically connected to the pin (14) via conventional wire bonds and/or other connections (13) .
  • a conventional metallic protective cover (23) is bonded to the substrate (20) via conventional means (not shown) .
  • a layer (24) of insulative material e.g., a fired glass bead or frit material
  • a layer (26) of conductive material (e.g., copper) is disposed on the inner surface (19) of the through-hole (18) of the circuit board (12) and is electrically connected to conducting solder joint/ground plane (60) which connects the package (10) to the circuit board (12) .
  • pin (14) and through-hole (18) are about 0.045 cm. and 0.0106 cm. in diameter.
  • board (12) is made of a conventional insulating material such as, epoxy-glass, paper phenolic resin, FR-4, and/or composite materials, although other types of insulating materials may be used without departing from this embodiment of the present invention.
  • board (12) has a thickness of about 0.155 cm., although other thickness' may be used without departing from the instant invention.
  • a third component (102) is mounted to the circuit board (12) and has a through-hole (104) that is axially aligned with the through-holes 16, 18 of the package 10 and circuit board (12) , respectively.
  • the third component comprises a low-loss dielectric substrate (105) (e.g., made of TeflonTM polytetrafluroetheleyne) having a conventional transmission line (28) and/or other high frequency circuit elements and/or devices (not shown) .
  • transmission line (28) is a conventional microstrip mode transmission line having a metallic excitation feed line (92) formed on the top (94) of the substrate (105) that is electrically connected to the pin (14) , and a metallic ground feed line (96) that is electrically connected to the ground plane (60) via conducting layer (26) .
  • Pin (14) preferably comprises a cylinder of conducting material (e.g., a material having a relatively low coefficient of thermal expansion, such as KovarTM material, plated with gold, copper, and/or tin) and is mounted in fired glass layer (24) in through-hole (16) of the first component and extends orthogonally therefrom through through-holes (18) and (104) to contact the excitation feed line (92) of transmission line (28) .
  • a cylinder of conducting material e.g., a material having a relatively low coefficient of thermal expansion, such as KovarTM material, plated with gold, copper, and/or tin
  • pin (14) may have other shapes and be made of other materials so long as the various constraints of the present invention are satisfied.
  • Microwave frequency signals are transmitted between the circuit (15) and the transmission line (28) via wire bond (13) , and pin (14) .
  • pin (14) is physically separated and electrically insulated from the conducting layer (26) of the through-hole (18) by at least one dielectric (106) in-between the pin (14) and the conducting layer (26) .
  • Dielectric (106) preferably comprises at least one low loss dielectric material (e.g., with a dielectric constant between 1 and 15) selected from the group consisting of: TeflonTM polytetrafluroetheleyne, RexoliteTM crosslinked polystyrene, TorlonTM polyamide, polyimide, air, or other similar low loss dielectric material.
  • the dielectric (106) comprises at least one annular dielectric plug (108) of 40 mils in length and separated from bead (24) by an air gap (112A) of 5-8 mils in length, although other types and/or configurations of materials made be used to form the at least one dielectric (106) , and if desired the air gap (112A) may be omitted altogether, or gap (112A) may be filled with dielectric material other than air. Further alternatively, air gap (112B) may be omitted altogether, or at least partly filled with dielectric material other than air, which material may either be the same or different from that used for dielectric (108) .
  • the materials and physical dimensions of the at least one dielectric (106) , bead (24) , conducting layer (26) , and pin (14) , as well as the dimensions of the through-hole (18) are selected so as to ensure that the signal transmission impedance of the pin (14) closely matches that of the transmission line (28) .
  • use of dielectric (106) to separate the pin (14) from the layer (26) greatly reduces the inductance generated by pin (14) and layer (26) when high frequency electrical signals are being transmitted through pin (14) .
  • FIG. 2 Another embodiment (200) of the structure of the present invention is shown in Figure 2.
  • the pin (14) extends into a cavity (204) of a conventional waveguide transmission line (202) formed in the third component (206) , and serves as the E-plane probe for the waveguide (202) and is orthogonal to the plane of components (12 and 202) .
  • a metallic conducting layer (208) is formed on the surface (210) of the board (12) and is connected to the ground plane (60) via the conducting layer (26) , and serves as the bottom wall for the waveguide (202) .
  • the pin (14) extends above the bottom wall (210) of the waveguide about 0.09 in., and the cavity (204) comprises both a full height waveguide region (212) (e.g., which has a height of about 0.347 cm. above the bottom (210)) and a half-height waveguide region (214) , however, depending upon particular design constraints, other configurations are possible without departing from this embodiment of the present invention.
  • Figure 3 illustrates the construction of yet another embodiment (300) of the present invention, in which the third component (302) comprises a conventional coaxial transmission line (304) connected to the pin (14) via a conventional mating coaxial connector (306) .
  • Connector (306) is mounted to the board (12) by a block (308) of conducting material attached to the board (12) , which block (308) includes a hole (310) that is axially aligned with the connector (306) and the pin (14) whereby to permit the pin (14) to be inserted into the connector (306) of the third component (302) via conventional threaded fasteners (314,316) which body (312) encloses the connector (306) and transmission line (304) .
  • Figure 4 is a cross-sectional view of another preferred embodiment (400) of the structure of the present invention.
  • the pin (14) extends to a conventional stripline transmission line
  • Stripline (402) comprises an excitation feed line (404) sandwiched between two low dielectric loss and.dielectric constant substrates (e.g., made of
  • TeflonTM polytetrafluroethelyne material (408,410)
  • two ground planes (412,414)
  • Ground metallization (412) is connected to the ground plane (60) via conducting layer (26)
  • metallization (414) is connected to ground (60) via another connection (not shown) .
  • pin (14) is electrically connected to the excitation metallization (404) of the transmission line (402) via a conventional wire bond connection (406) .
  • Figure 5 illustrates yet another preferred embodiment (500) of the structure of the present invention.
  • Embodiment (500) includes two pins (14A,14B) which are electrically connected to the chip (15) via wire bonds (13A, 13B) , respectively.
  • the third component (502) comprises two identical internal waveguide transmission lines (503,505) whose construction is substantially similar to that of waveguide (202) of embodiment (200) .
  • Pins (14A, 14B) extend into cavities (504,506), respectively, and form the E-plane probes of the waveguides (503,505) .
  • Metallic conducting layers (508,510) are connected to the conducting layers (26A,26B) of through-holes (18A,18B) , respectively, and form the bottom ground planes of the waveguides.
  • One preferred method (800) for forming the electronic structure (100) of Figure 1 begins by forming a through-hole (16) in substrate (20) (see block 802) .
  • a frit of glass bead material is disposed in through-hole (16) and pin (14) is placed therethrough (see block 802)
  • the substrate (20) , pin (14) and frit (24) are then fired to bond the pin (14) to the integrated base plate (20) (see block 806) .
  • the integrated circuit (15) is then mounted to the header substrate (20) using conventional techniques with either solder or silver- filled conductive epoxy (see block 808) .
  • Conventional wire bonds (13) are then formed to connect pin (14) to the circuit (15) (see block 810) .
  • the metallic package cover (23) is then metallurgically attached (e.g., cold welded) to the integrated circuit base plate (20) (see block 812) .
  • Circuit board (12) having conventionally- formed conductive traces and features is then patterned using solder and paste in a conventional silk-screened patterning process (see block 814) .
  • the amount and pattern of solder paste are carefully controlled to prevent excess solder form flowing into hole (18) during the silk-screening process.
  • the package (10) is then placed onto board (12) along surface (60) , either with or without additional components (not shown) (see block 816) .
  • the board (12) and package (10) are then controllably heated in an infrared reflow furnace to cause the solder to melt (see 818) .
  • the board and package (10) are then allowed to cool so as to mechanically and electrically attach the package (10) to the circuit board (12) (see block 820) .
  • the package (10) is preferably held in place on the circuit board by using mounting pins, in a known manner.
  • conventional jig-type structures may be used to hold the package (10) in place on the board (12) during reflow.
  • the package (10) may be mounted to the board (12) using conductive epoxy paste.
  • the epoxy is cured using a conventional cure cycle thereby obviating the need to use the infrared reflow furnace.
  • dielectric plug (106) Prior to bonding of the substrate (20) to the circuit board (12) , dielectric plug (106) may be formed in hole (18) by conventional techniques such as, extrusion, machining and/or molding of the dielectric material, followed by mounting the formed material using conventional techniques in the through-hole (18) .
  • the plug may be formed in place in the through-hole (18) by pouring an epoxy-based dielectric material of the type previously described, and allowing the plug (16) to cure and harden (see block 830) .
  • the microstrip board (102) is mounted to the circuit board (12) -using conventional solder and/or adhesive material.
  • the adhesive material comprises a double-sided membrane which may either be conductive or non-conductive depending upon particular design constraints (see block 832) .
  • a conventional solder joint is formed between pin (14) and transmission line (28) (see block 834) .

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

An electrical connection between a transmission line and an integrated circuit package comprises, a circuit board (12) on which are mounted a transmission line (28, 402, 202, 503, 505) and an integrated circuit package (10), a projecting portion of a pin (14, 14A, 14B) projecting from an integrated circuit package (10), a transmission line feed (32, 404) that further comprises a waveguide cavity (204, 504, 506) connected to the pin (14, 14A, 14B) and a dielectric material (106) surrounding the pin (14, 14A, 14B), the dielectric material being between the pin and a ground feed (92, 412, 414, 208, 508, 510) of the transmission line (28, 402, 202, 503, 505).

Description

ELECTRICAL CONNECTION
The invention relates to an electrical connection between a transmission line and an integrated circuit package. According to integrated circuit technology, an electronic component comprises, an integrated circuit within a package, and at least one conducting pin projecting from the package for connection to a circuit board. The integrated circuit is electrically connected to the pin, for example, by a bond wire. In the past, the pin has been directly connected to a transmission line on the circuit board. Such a connection can limit the maximum frequency in which signals may be transmitted, due to the inductance of the connection and signal attenuation at high frequency, for example, 5-8 dB at 25-30 GHz. According to U.S. Patent 5,266,912, an integrated circuit package is constructed with a pin that has a coaxial construction within the package. A tip of the pin projects outwardly from the coaxial construction for plugging into a circuit board or into a stack of integrated circuit packages. The projecting tip of the pin may also be plugged into an electrical socket.
A need exists for a technique or for a connection between a projecting pin on* an integrated circuit package and a transmission line on a circuit board wherein the transmission line comprises both a ground feed connected to a ground point on the circuit board, and a feed of the transmission line being connected to the pin. A need exists to reduce inductance in the connection between the pin of the integrated circuit package and the transmission line on the circuit board.
According to the invention, an electrical connection between a transmission line and an integrated circuit package comprises a circuit board on which are mounted the transmission line and the integrated circuit package, the transmission line comprising a ground feed connected to a ground plane on the circuit board and a feed connected to the pin of an integrated circuit package with a dielectric material surrounding the pin between the feed of the transmission line and the integrated circuit package. An advantage resides in the pin being surrounded with a dielectric material from the feed of the transmission line on the circuit board to the integrated circuit package.
According to an embodiment, the pin extends in a through-hole through the circuit board and dielectric material is contained within the through-hole. An advantage resides in a portion of the pin that projects from the integrated circuit package being surrounded by dielectric material. Another advantage resides in the portion of the pin that projects from the integrated circuit package having a dielectrical material that can be selected to control the electrical performance of the connection between the pin and a feed of a transmission line on the circuit board.
According to an embodiment, a portion of a pin that projects from an integrated circuit package extends in a through-hole together with dielectric material surrounding the pin, and a layer of conducting material in the through-hole advantageously provides improved electrical performance along a projecting portion of the pin.
According to an embodiment the transmission line comprises a waveguide transmission line connected to the pin, and the pin is an E-plane probe within a cavity of the waveguide transmission line. An advantage resides in adapting a projecting pin of an integrated circuit package into an E-plane probe. According to an embodiment, the circuit board extends between the transmission line and the integrated circuit package, and the projecting portion of the pin extends through the circuit board together with the dielectric material surrounding the pin. An advantage resides in adding a through-hole of a circuit board with a construction to improve the electrical performance of a connection of a projecting portion of a pin on an integrated circuit package. Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, according to which:
Figure 1 is a cross-section view illustrating the construction of one preferred embodiment of an electronic device made according to the present invention.
Figure 2 is a cross-section view illustrating the construction of another preferred embodiment of a device made according to the present invention. Figure 3 is a cross-section view illustrating the construction of yet another preferred embodiment of a device made according to the present invention.
Figure 4 is a cross-section view illustrating the construction of still another, preferred embodiment of a device made according to the present invention.
Figure 5 is a cross-section view illustrating the construction of another preferred embodiment of a device made according to the present invention. Figure 6 is a block diagram showing the steps of one preferred embodiment of the method of the present invention for use in producing the device of Figure 3. Figure 1 is a cross-section view of one preferred embodiment (100) of an electronic device made according to the present invention. Device (100) comprises a first electronic component which in this embodiment is an integrated circuit package (10) , mounted to a second electronic component which in this embodiment is a printed circuit board (12) , via an electrically conductive pin (14) . Integrated circuit chip (15) of the package (10) is mounted by conventional means to the header substrate (e.g., made of a material having a relatively low coefficient of thermal expansion, such as rolled steel or KovarT material, and having a thickness of about 0.06 in. (20), and the chip (15) is electrically connected to the pin (14) via conventional wire bonds and/or other connections (13) . A conventional metallic protective cover (23) is bonded to the substrate (20) via conventional means (not shown) . A layer (24) of insulative material (e.g., a fired glass bead or frit material) is disposed on the inner surface (11) of the through-hole (16) of the package (10) for electrically insulating the pin (14) from the substrate (20) of package (10) . A layer (26) of conductive material (e.g., copper) is disposed on the inner surface (19) of the through-hole (18) of the circuit board (12) and is electrically connected to conducting solder joint/ground plane (60) which connects the package (10) to the circuit board (12) . Preferably, pin (14) and through-hole (18) are about 0.045 cm. and 0.0106 cm. in diameter.
Preferably, board (12) is made of a conventional insulating material such as, epoxy-glass, paper phenolic resin, FR-4, and/or composite materials, although other types of insulating materials may be used without departing from this embodiment of the present invention. Preferably, in this embodiment, board (12) has a thickness of about 0.155 cm., although other thickness' may be used without departing from the instant invention.
A third component (102) is mounted to the circuit board (12) and has a through-hole (104) that is axially aligned with the through-holes 16, 18 of the package 10 and circuit board (12) , respectively. Preferably, the third component comprises a low-loss dielectric substrate (105) (e.g., made of TeflonTM polytetrafluroetheleyne) having a conventional transmission line (28) and/or other high frequency circuit elements and/or devices (not shown) . In this embodiment, transmission line (28) is a conventional microstrip mode transmission line having a metallic excitation feed line (92) formed on the top (94) of the substrate (105) that is electrically connected to the pin (14) , and a metallic ground feed line (96) that is electrically connected to the ground plane (60) via conducting layer (26) .
Pin (14) preferably comprises a cylinder of conducting material (e.g., a material having a relatively low coefficient of thermal expansion, such as KovarTM material, plated with gold, copper, and/or tin) and is mounted in fired glass layer (24) in through-hole (16) of the first component and extends orthogonally therefrom through through-holes (18) and (104) to contact the excitation feed line (92) of transmission line (28) . Of course, pin (14) may have other shapes and be made of other materials so long as the various constraints of the present invention are satisfied. Microwave frequency signals are transmitted between the circuit (15) and the transmission line (28) via wire bond (13) , and pin (14) .
According to the present invention, pin (14) is physically separated and electrically insulated from the conducting layer (26) of the through-hole (18) by at least one dielectric (106) in-between the pin (14) and the conducting layer (26) . Dielectric (106) preferably comprises at least one low loss dielectric material (e.g., with a dielectric constant between 1 and 15) selected from the group consisting of: TeflonTM polytetrafluroetheleyne, RexoliteTM crosslinked polystyrene, TorlonTM polyamide, polyimide, air, or other similar low loss dielectric material. Most preferably, the dielectric (106) comprises at least one annular dielectric plug (108) of 40 mils in length and separated from bead (24) by an air gap (112A) of 5-8 mils in length, although other types and/or configurations of materials made be used to form the at least one dielectric (106) , and if desired the air gap (112A) may be omitted altogether, or gap (112A) may be filled with dielectric material other than air. Further alternatively, air gap (112B) may be omitted altogether, or at least partly filled with dielectric material other than air, which material may either be the same or different from that used for dielectric (108) . Preferably, the materials and physical dimensions of the at least one dielectric (106) , bead (24) , conducting layer (26) , and pin (14) , as well as the dimensions of the through-hole (18) are selected so as to ensure that the signal transmission impedance of the pin (14) closely matches that of the transmission line (28) . Advantageously, use of dielectric (106) to separate the pin (14) from the layer (26) greatly reduces the inductance generated by pin (14) and layer (26) when high frequency electrical signals are being transmitted through pin (14) . Indeed, it has been found that by separating the conducting layer (26) and pin (14) with the dielectric (106) , signal losses through the pin (14) may be reduced to only 0.5 dB at a frequency of 25-30 GHz, without necessitating thinning of the circuit board (12) and without increasing signal crosstalk. Another embodiment (200) of the structure of the present invention is shown in Figure 2. In embodiment (200) , the pin (14) extends into a cavity (204) of a conventional waveguide transmission line (202) formed in the third component (206) , and serves as the E-plane probe for the waveguide (202) and is orthogonal to the plane of components (12 and 202) . A metallic conducting layer (208) is formed on the surface (210) of the board (12) and is connected to the ground plane (60) via the conducting layer (26) , and serves as the bottom wall for the waveguide (202) . In embodiment (200) , the pin (14) extends above the bottom wall (210) of the waveguide about 0.09 in., and the cavity (204) comprises both a full height waveguide region (212) (e.g., which has a height of about 0.347 cm. above the bottom (210)) and a half-height waveguide region (214) , however, depending upon particular design constraints, other configurations are possible without departing from this embodiment of the present invention. Figure 3 illustrates the construction of yet another embodiment (300) of the present invention, in which the third component (302) comprises a conventional coaxial transmission line (304) connected to the pin (14) via a conventional mating coaxial connector (306) . Connector (306) is mounted to the board (12) by a block (308) of conducting material attached to the board (12) , which block (308) includes a hole (310) that is axially aligned with the connector (306) and the pin (14) whereby to permit the pin (14) to be inserted into the connector (306) of the third component (302) via conventional threaded fasteners (314,316) which body (312) encloses the connector (306) and transmission line (304) .
Figure 4 is a cross-sectional view of another preferred embodiment (400) of the structure of the present invention. In embodiment (400) , the pin (14) extends to a conventional stripline transmission line
(402) . Stripline (402) comprises an excitation feed line (404) sandwiched between two low dielectric loss and.dielectric constant substrates (e.g., made of
TeflonTM polytetrafluroethelyne material) (408,410) , and two ground planes (412,414) . Ground metallization (412) is connected to the ground plane (60) via conducting layer (26) , and metallization (414) is connected to ground (60) via another connection (not shown) .
Preferably, pin (14) is electrically connected to the excitation metallization (404) of the transmission line (402) via a conventional wire bond connection (406) . Figure 5 illustrates yet another preferred embodiment (500) of the structure of the present invention. Embodiment (500) includes two pins (14A,14B) which are electrically connected to the chip (15) via wire bonds (13A, 13B) , respectively. In embodiment (500) , the third component (502) comprises two identical internal waveguide transmission lines (503,505) whose construction is substantially similar to that of waveguide (202) of embodiment (200) . Pins (14A, 14B) extend into cavities (504,506), respectively, and form the E-plane probes of the waveguides (503,505) . Metallic conducting layers (508,510) are connected to the conducting layers (26A,26B) of through-holes (18A,18B) , respectively, and form the bottom ground planes of the waveguides.
Turning now to Figure 6, a preferred method for forming the electronic device of Figure 1 will be discussed. It should be appreciated that the formation method that is described hereafter is merely illustrative, and any combination of conventional fabrication techniques may be used to construct the electronic structure (100) of Figure 1.
One preferred method (800) for forming the electronic structure (100) of Figure 1 begins by forming a through-hole (16) in substrate (20) (see block 802) . A frit of glass bead material is disposed in through-hole (16) and pin (14) is placed therethrough (see block
(804) . The substrate (20) , pin (14) and frit (24) are then fired to bond the pin (14) to the integrated base plate (20) (see block 806) . The integrated circuit (15) is then mounted to the header substrate (20) using conventional techniques with either solder or silver- filled conductive epoxy (see block 808) . Conventional wire bonds (13) are then formed to connect pin (14) to the circuit (15) (see block 810) . The metallic package cover (23) is then metallurgically attached (e.g., cold welded) to the integrated circuit base plate (20) (see block 812) . Circuit board (12) having conventionally- formed conductive traces and features is then patterned using solder and paste in a conventional silk-screened patterning process (see block 814) . Preferably, the amount and pattern of solder paste are carefully controlled to prevent excess solder form flowing into hole (18) during the silk-screening process.
The package (10) is then placed onto board (12) along surface (60) , either with or without additional components (not shown) (see block 816) . The board (12) and package (10) are then controllably heated in an infrared reflow furnace to cause the solder to melt (see 818) . The board and package (10) are then allowed to cool so as to mechanically and electrically attach the package (10) to the circuit board (12) (see block 820) . During this reflow process, the package (10) is preferably held in place on the circuit board by using mounting pins, in a known manner. Alternatively, conventional jig-type structures may be used to hold the package (10) in place on the board (12) during reflow. Alternatively, the package (10) may be mounted to the board (12) using conductive epoxy paste. The epoxy is cured using a conventional cure cycle thereby obviating the need to use the infrared reflow furnace. Prior to bonding of the substrate (20) to the circuit board (12) , dielectric plug (106) may be formed in hole (18) by conventional techniques such as, extrusion, machining and/or molding of the dielectric material, followed by mounting the formed material using conventional techniques in the through-hole (18) .
Alternatively, the plug may be formed in place in the through-hole (18) by pouring an epoxy-based dielectric material of the type previously described, and allowing the plug (16) to cure and harden (see block 830) . Thereafter, the microstrip board (102) is mounted to the circuit board (12) -using conventional solder and/or adhesive material. Preferably, the adhesive material comprises a double-sided membrane which may either be conductive or non-conductive depending upon particular design constraints (see block 832) . After the board (102) is mounted to circuit board (12) , a conventional solder joint is formed between pin (14) and transmission line (28) (see block 834) .

Claims

1. An electrical connection between a transmission line and an integrated circuit package comprises the circuit board on which are mounted the transmission line and the integrated circuit package, and a projecting pin of the integrated circuit package connected to a feed of the transmission line, characterized in that; a dielectric material surrounds a projecting portion of the pin, the dielectric material being between the pin and a ground plane on the circuit board to which a ground feed of the transmission line is connected.
2. An electrical connection as recited in claim 1 wherein, the pin extends in a through-hole through the circuit board, and the dielectric material is contained within the through-hole.
3. An electrical connection as recited in claim 1, further characterized in that; a layer of conducting material is in the through-hole and connects to the ground feed of the transmission line.
4. An electrical connection as recited in claim 1 wherein, the circuit board extends between the transmission line and the integrated circuit package, and the conducting pin extends through the circuit board together with the dielectric material surrounding the pin.
5. An electrical connection as recited in claim 1 wherein, the transmission line is a strip transmission line having a feed line connected to a projecting portion of the pin.
6. An electrical connection as recited in claim 1 wherein, the transmission line is a waveguide transmission line connected to the projecting portion of the pin, and the projecting portion of the pin is an E- plane probe within the cavity of the waveguide transmission line.
PCT/US1996/008223 1995-06-01 1996-05-31 Electrical connection WO1996039012A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US45654295A 1995-06-01 1995-06-01
US08/456,542 1995-06-01

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WO2003077316A1 (en) * 2002-03-13 2003-09-18 Optillion Ab Impedance matching
US9123738B1 (en) 2014-05-16 2015-09-01 Xilinx, Inc. Transmission line via structure

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WO2003077316A1 (en) * 2002-03-13 2003-09-18 Optillion Ab Impedance matching
US9123738B1 (en) 2014-05-16 2015-09-01 Xilinx, Inc. Transmission line via structure
WO2015175023A1 (en) * 2014-05-16 2015-11-19 Xilinx, Inc. Transmission line via structure

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