WO1996030951A1 - Photoemetteurs et photodetecteurs - Google Patents

Photoemetteurs et photodetecteurs Download PDF

Info

Publication number
WO1996030951A1
WO1996030951A1 PCT/GB1996/000767 GB9600767W WO9630951A1 WO 1996030951 A1 WO1996030951 A1 WO 1996030951A1 GB 9600767 W GB9600767 W GB 9600767W WO 9630951 A1 WO9630951 A1 WO 9630951A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon
dots
quantum dots
germanium
layers
Prior art date
Application number
PCT/GB1996/000767
Other languages
English (en)
Inventor
Yin Sheng Tang
Clivia Marfa Sotomayor-Torres
Original Assignee
The University Court Of The University Of Glasgow
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by The University Court Of The University Of Glasgow filed Critical The University Court Of The University Of Glasgow
Publication of WO1996030951A1 publication Critical patent/WO1996030951A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035236—Superlattices; Multiple quantum well structures
    • H01L31/035254—Superlattices; Multiple quantum well structures including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table, e.g. Si-SiGe superlattices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y20/00—Nanooptics, e.g. quantum optics or photonic crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H01L33/18—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/34—Materials of the light emitting region containing only elements of Group IV of the Periodic Table

Definitions

  • the present invention relates to light emitting and detecting devices and in particular to light emitting and detecting devices fabricated from silicon/silicon-germanium material.
  • Si/Ge strained layer superlattices which comprise alternating layers of silicon and germanium, each layer being only a few atoms thick. These layers are generally grown on a silicon substrate using molecular beam epitaxy (MBE) although other growth techniques are known.
  • MBE molecular beam epitaxy
  • EP-A1-0535293 considers the fabrication of multiple quantum wire or dot structures in Si/Ge strained layer superlattice material but there is no disclosure of structures providing practical optical devices.
  • a silicon compatible light emitting or detecting device comprising a substrate, a multiplicity of quantum dots provided on the substrate and each comprising a plurality of alternate silicon and silicon-germanium layers, each quantum dot having a transverse cross- sectional area of less than 8,000nm : , and respective electrical connections to the substrate and upper regions of the dots to enable electrical current to flow through the dots.
  • the plurality of layers constitute strained layer superlattice (SLS) material which during manufacturing gives rise to a number of quantum dots each of which is capable of converting light into electric current or vice versa.
  • SLS strained layer superlattice
  • the transverse cross-sectional area of each quantum dot is greater than 200nm : . More preferably, the transverse cross-sectional area is greater than 700nm 2 , for example 2,000nm ** for dots about 50nm in diameter.
  • the dots have the shape of a circular cylinder having a height to diameter ratio of at least 1:1, where the diameter is between 10 and lOOn , e.g. 50nm.
  • the device comprises at least 10-15 silicon layers alternating with 10-15 silicon-germanium layers.
  • each layer has a thickness of about 2-10nm.
  • the silicon-germanium layers have a composition which is 70% silicon and 30% germanium.
  • the substrate is silicon and the base layer of the quantum dots is a silicon buffer or a graded silicon-germanium buffer, e.g. 200nm thick.
  • the substrate is heavily doped P-type (Boron, Antimony) or N-type (Phosphorous) material.
  • a support material for example polyimide, silicon dioxide, or silicon nitride, is disposed between the dots of the array.
  • the support material has a dielectric constant smaller than that of the superlattice structure and is substantially electrically insulating so that electric current present within the quantum dots is substantially confined therein.
  • the dielectric support material provides a mechanical support for an electrode layer making electrical contact with the upper surfaces of the quantum dots.
  • the support material is preferably deposited so as to have a substantially stress free configuration.
  • a method of fabricating a silicon compatible light emitting or detecting device comprising the steps of: providing a plurality of alternate layers of silicon and silicon-germanium on a support, said alternate layers constituting a strained layer superlattice; defining on the exposed surface of the alternate layers an etch mask which leaves uncovered areas of the superlattice which are to be removed; etching through the exposed areas of the superlattice substantially down to the support to define an array of quantum dots; and making respective electrical connections to the support and to upper regions of the quantum dots to enable electric current to flow through the quantum dots.
  • the plurality of alternate layers of silicon and silicon-germanium are grown using molecular beam epitaxy or metal-organic chemical vapour deposition (MOCVD) .
  • the support comprises a buffer layer grown on a semiconductor substrate.
  • the method of the above second aspect of the present invention comprises the step of filling the spaces between the quantum dots with a dielectric support material.
  • the method may comprise the further step of etching away some of the dielectric material to expose an upper surface or end face of each of the dots to which electrical connections may be made, e.g. by evaporating a metal onto the upper surface of the structure.
  • the step of defining an etch mask comprises depositing a resist on the surface of the superlattice, which resist can be exposed using electromagnetic radiation, e.g x-rays or an electron beam. This step further comprises exposing an appropriate pattern in the resist using electromagnetic radiation or an electron beam and developing the sample to remove exposed (in the case of a positive resist) or unexposed (in the case of a negative resist) areas.
  • the resist is an electron beam sensitive resist and areas to be exposed are exposed to an electron beam exposure of between 1,000 and 2,000 ⁇ C/ cm 2 , for a 50KeV beam and between 2,000 and 4,000 ⁇ C/cm 2 for a lOOKeV beam.
  • the electron beam resist is developed using an iso-propyl alcohol/mixture MiBK (iso-butyl-methylketone, e.g. in a 3:1 ratio mixture for 30 seconds.
  • the etch mask may be defined by evaporating a suitable metal (metal alloy) , for example NiChrome (NiCr) , at a thickness of between 10 and 50nm, preferably 30nm, over the developed resist and 'lifting- off the NiChrome from the unwanted areas using acetone.
  • a suitable metal metal alloy
  • NiChrome NiCr
  • the step of etching the superlattice material to define the quantum dots comprises using reactive ion etching.
  • a preferred etching gas is silicon tetrachloride (SiCl.) .
  • Suitable etch conditions are an RF power of 10 to 50 watts (at 13.56MHz), a gas flow rate of 2 to 3sccm, a pressure of 3 to 15mTorr, and a DC bias of 50 to 300volts, to give an etch rate of 20 to 25nm/min for a planar chamber etching system.
  • Figure 1 is a diagrammatic representation of a light emitting device embodying the present invention
  • Figure 2 shows an enlarged cross-section through a part of the device of Figure 1;
  • Figures 3 (a) to (f) shows the main fabrication steps involved in producing the light emitting device shown in Figure 1;
  • Figure 4 shows a typical photoluminescence (PL) spectra for an array of 60nm diameter pure germanium quantum dots and for a sample of 'as grown' material;
  • Figure 5 is a graph of photoluminescence intensity of a 50nm dot array for a Si-Si 0f ,Ge 02 composition
  • Figure 6 shows the relationship between quantum dot diameter and normalised peak PL intensity for different Si- Si,. x Ge_ superlattices
  • Figure 7 is a graph of electroluminescence versus wavelength and energy for a Si-Si tl7 Ge 03 superlattice p-i-n quantum dot diode showing temperature dependence;
  • Figure 8 shows the photoluminescence vs stress characteristic for a light emitting device of the type shown in Figures 1 and 2 where device dots are in-filled with silicon nitride;
  • a light emitting device 1 comprising twenty discrete quantum dot structures 2 fabricated on a heavily N-doped (phosphorous) (>10 18 cm '3 ) silicon substrate 3 which is oriented in the ⁇ 100> direction.
  • Each dot is in the shape of a circular cylinder having a diameter of 60nm and a height of 250nm.
  • the dots each comprise a plurality of undoped silicon layers 4 alternating with a plurality of silicon-germanium layers 5, where the silicon- germanium composition is Si t)7 Ge honor,.
  • each layer has a thickness of 6nm giving a total dot height of 180nm, which together form a strained layer superlattice quantum dot.
  • An additional heavily doped p-type silicon layer 12 (e.g. 43nm thick) is provided on top of the quantum dots. This top layer enables electrical contacts to be formed with the dots.
  • a practical quantum dot array will comprise many more than 12 quantum dots to produce sufficient electroluminescence for the intended application, although the dots should not generally occupy more than 25% of the surface of the device.
  • the regions between the dots are in-filled with a polyimide dielectric material 6 which serves to isolate electrically the dots from one another forming a composite matrix.
  • the dielectric material also provides additional mechanical strength to the device.
  • Electrodes 7, 8 are formed on both the upper surfaces of the composite matrix and the lower surface of the substrate to allow electric current to flow through the dots when a potential is applied across the electrodes or to receive electrical current generated within the dots in response to light radiation incident on the dots.
  • the quantum dots are structures which are sized to confine electron quantum mechanical-type waves.
  • the restriction of the trapped waves in all three dimensions results in changes in the band structure of the dot material which in turn results in changes in the optical properties of the material as will be described hereinbelow.
  • the process required to fabricate a device of the type shown in Figures 1 and 2, having dot diameters of 60nm, will now be described with reference to Figure 3.
  • the process begins with a chip comprising an N-doped (Phosphorous) ⁇ 100> oriented silicon substrate 3 on which has been grown a silicon buffer layer 9 followed by a strained layer superlattice comprising 15 silicon layers 4 alternating with 15 silicon-germanium layers 5 (Si ⁇ 7 Ge 03 ) , each layer being 6nm thick as described above.
  • the material used to obtain the results described hereinbelow was provided by the University of Link ⁇ ping, Sweden (see Journal of Crystal Growth, 1995, Vol. 157, No 1-4, pp. 285- 294 and Journal of Crystal Growth, 1995, Vol. 157, No 1-4, pp 242-247) .
  • An alternative superlattice material has alternating layers each 3nm thick.
  • a further p-type silicon layer 12 is provided on top of the supperlattive structure.
  • the sample is first cleaned and an electron beam resist 10 is coated onto the upper surface of the strained layer superlattice by, for example, spinning.
  • the electron beam resist is PMMA (polymethylmethacrylate) which comprises 2.5% BDH spun on as a first layer (5krpm for 60 seconds and baked at 180°C for 2hrs) followed by a second layer of 2.5% ELV (5krpm and baked for 2hrs or longer, e.g. overnight) to produce a resist layer 64nm thick.
  • PMMA polymethylmethacrylate
  • ELV 5.5% ELV
  • a suitable apparatus for carrying out this exposure is a modified scanning electron microscope or an electron (Phillips) Beamwriter.
  • the electron beam exposure is set to 2000 ⁇ C/cm 2 with a beam energy of 50KeV.
  • the exposed resist is then removed by developing the sample in iso-propyl alcohol (IPA) mixed with MiBK in a ratio of 3:1, for 30 seconds [Figure 3(b)].
  • IPA iso-propyl alcohol
  • the sample is then placed in an evacuated chamber at a pressure of less than 2 x 10 " ° Torr and a 10 to 30nm layer of NiChrome 11 (90% Ni) is evaporated onto the upper surface of the sample [Figure 3 (c) ] .
  • the remaining resist on the upper surface of the sample is removed by soaking the sample in acetone for a suitable period of time.
  • the dissolution of the resist causes the NiChrome overlying the resist to be lifted-off, leaving only those areas of NiChrome which are directly adhered to the upper surface of the strained layer superlattice as shown in Figure 3(d) .
  • the lattice is etched using a reactive ion etching machine, for example [PlasmaTech RIE80, RF frequency of 13.6MHz].
  • a preferred etch gas is silicon tetrachloride (SiCl 4 ) and suitable etch parameters are a radio frequency power of 30 watts, a gas flow rate of 2.25sccm, a pressure of 10.8mTorr and a DC bias voltage of 190 volts, giving an etch rate of 25nm/min. Etching under these conditions is carried out for a time of 10 minutes in order to ensure that the sample is etched through the strained layer superlattice to the silicon buffer layer.
  • the NiChrome mask is removed using hydrochloric acid (>40% for 3 hours) to create the structure shown in Figure 3(e).
  • the next step in the process is to in-fill the spaces between the quantum dots with a dielectric material which is both electrically insulating and which has a dielectric constant smaller than those of the quantum dot materials.
  • the dielectric material should also have a lattice constant and a thermal expansion coefficient close to those of the Si/Si-Ge layers so as to minimise the external stress applied to the superlattice.
  • Suitable dielectric materials include silicon dioxide (SiO : ) , silicon nitride (Si,N 4 ) and polyimide.
  • SiO and Si,N may be deposited using plasma assisted chemical vapour deposition (see below)
  • polyimide is generally spun onto the surface of the device to an appropriate thickness and subsequently cured. Following deposition, the dielectric is etched back to expose the upper surfaces of the dots.
  • a layer of indium tin oxide (ITO) 7 is grown on the surface of the device (ITO being both electrically conductive and optically transparent) and a layer of aluminium 8 is deposited on the bottom surface of the substrate to create the structure show in Figure 3(f).
  • ITO indium tin oxide
  • Ni-chrome may be evaporated onto the upper surface of the device to provide electrical contact to the upper surfaces of the dots.
  • Figure 4 spectrum (a) has a width of 0.05eV and arises from strongly localized excitons in the zero-dimensional (0D) structures.
  • Figure 5 spectrum (a) shows a graph of the photoluminescence (PL) versus wavelength (nm) of a 50nm quantum dot array made from a Si-Siliens copy Ge 2 single quantum well grown on an undoped Si substrate under the same conditions as the material from which the data shown in Figure 4 was obtained (4K, Ivantage 0.5w/cm 2 ).
  • the PL spectrum for the dot array is also some orders of magnitude greater than the MBE as-grown material with a peak (1) at a wavelength of 1150nm corresponding to l.08eV.
  • This peak also corresponds to the exciton no-phonon emission (X NP ) .
  • the PL spectrum of the as-grown material (spectrum (b) in Figure 5) has a peak for X sv at 1180nm (1.05eV) and a peak which is almost as large for X ⁇ o (transverse optical phonon assisted excition) at 1250nm (l.OOeV).
  • Figure 6 shows the relationship between dot diameter (nm) and the normalised peak 1 emission intensity (arbitrary units) on logarithmic axes for different Si-Ge compositions. It will be seen that the relationship is substantially independent for the three compositions shown.
  • the peak intensity increases slowly by one order of magnitude with reducing dot size to about 200nm. Further reducing the dot diameter to about 60-l00nm causes a sudden and pronounced additional increase in intensity of up to an order of magnitude.
  • the dot sizes are less than 60nm diameter
  • the peak intensity is increased by more than two orders of magnitude compared to dot diameters of 200nm or more.
  • the quantum efficiency is correspondingly enhanced by more than two orders of magnitude in going from the as- grown material to the quantum dot arrays.
  • Figure 7 depicts a graph of Electroluminescence (EL) versus wavelength (nm) of one of three quantum dot p-i-n diodes from a Si-Si t)7 Ge 3 superlattice which were measured at temperatures between 4K and 293K (room temperature) by injecting a current of lpA/50nm dot.
  • the EL current injecting threshold for all three devices was 0.1pA/50nm dot (5mA/cm 2 ) . It will be seen that at 4K, as with Figures 4,5, there is a sharp peak at about 1200nm and 1.05eV with the EL magnitude falling slightly with increasing temperature until room temperature where the emission wavelength increases to I300nm at 0.95eV.
  • the recognised coupling wavelengths for low band loss fibre-optic communications are 1.31 and 1.55 ⁇ m.
  • the composition can be tuned so that the PL or EL is at one of these wavelengths or any other desired wavelength between 1.0 and 1.6 ⁇ m.
  • silicon nitride one alternative to polyimide as an in-fill dielectric material.
  • Figure 8 shows the PL intensity vs stress (in the nitride layer) characteristic for devices of the type shown in Figures 1 and 2 where the in-fill dielectric material is silicon nitride. It can be seen that the PL intensity is a maximum when the silicon nitride is substantially stress free.
  • the process described above with reference to Figure 3 is modified by depositing a layer of silicon nitride onto the intermediate device of Figure 3(e) using PECVD.
  • the process uses an RF frequency of 13.56MHZ, RF power of 18 to 23W, gas flows of SiH 4 at lOsccm, NH 3 at 44sccm, N : at 25.5sccm and He at 144.5sccm (total flow 224sccm) , and a temperature of 300°C.
  • silicon oxide and titanium oxide Possible alternatives to silicon nitride, and which enable the production of stress free in-fill layers, are silicon oxide and titanium oxide. Other alternatives include boron oxide and Lang uir-Blodgett films.
  • the dots may have cross-sections other than circular, e.g. square or hexagonal, providing that the transverse cross- sectional area meets the above requirements.
  • the sidewalls of the dots may deviate from the vertical, for example the dots may be frustoconical in shape.
  • the number of layers in the quantum dots may vary and may be as few as three, i.e. one silicon-germanium layer sandwiched between two silicon layers.
  • the device structure described above may be used to provide a light detector, where light photons impinging on the dots are converted into electric current flowing between the top and the bottom electrodes.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biophysics (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Led Devices (AREA)

Abstract

La présente invention concerne un photoémetteur photodétecteur compatible avec le silicium qui se compose d'un substrat (3) et d'une multiplicité de points quantiques (2) disposés sur le substrat. Chaque point quantique (2) est constitué d'une pluralité de couches alternant en silicium et silicium-germanium (4, 5) et sa coupe présente une superficie de moins de 8000 nm2. Les régions entre les points quantiques (2) sont remplies d'un matériau diélectrique (6), des connexions électriques (7, 8) étant établies respectivement avec le substrat et les surfaces supérieures des points (2) pour permettre au courant électrique de passer au travers des points (2).
PCT/GB1996/000767 1995-03-31 1996-03-29 Photoemetteurs et photodetecteurs WO1996030951A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9506735.1 1995-03-31
GBGB9506735.1A GB9506735D0 (en) 1995-03-31 1995-03-31 Light emitters and detectors

Publications (1)

Publication Number Publication Date
WO1996030951A1 true WO1996030951A1 (fr) 1996-10-03

Family

ID=10772310

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1996/000767 WO1996030951A1 (fr) 1995-03-31 1996-03-29 Photoemetteurs et photodetecteurs

Country Status (2)

Country Link
GB (1) GB9506735D0 (fr)
WO (1) WO1996030951A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0899796A2 (fr) * 1997-08-29 1999-03-03 Toshiba Corporation Dispositif semi-conducteur émetteur de lumière comprenant des nanocristaux
US6027666A (en) * 1998-06-05 2000-02-22 The Governing Council Of The University Of Toronto Fast luminescent silicon
WO2001008225A1 (fr) * 1999-07-26 2001-02-01 France Telecom Procede de realisation d'un dispositif comprenant un empilement de plans de boites quantiques
WO2002073527A2 (fr) * 2001-03-09 2002-09-19 Wisconsin Alumni Research Foundation Dispositifs a points quantiques a l'etat solide et calcul quantique utilisant des portes logiques nanostructurees

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0535293A1 (fr) * 1991-01-29 1993-04-07 Max-Planck-Gesellschaft zur Förderung der Wissenschaften e.V. Procédé de fabrication d'un dispositif semiconducteur compositionnel
US5244828A (en) * 1991-08-27 1993-09-14 Matsushita Electric Industrial Co., Ltd. Method of fabricating a quantum device
US5293050A (en) * 1993-03-25 1994-03-08 International Business Machines Corporation Semiconductor quantum dot light emitting/detecting devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0535293A1 (fr) * 1991-01-29 1993-04-07 Max-Planck-Gesellschaft zur Förderung der Wissenschaften e.V. Procédé de fabrication d'un dispositif semiconducteur compositionnel
US5244828A (en) * 1991-08-27 1993-09-14 Matsushita Electric Industrial Co., Ltd. Method of fabricating a quantum device
US5293050A (en) * 1993-03-25 1994-03-08 International Business Machines Corporation Semiconductor quantum dot light emitting/detecting devices

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
NI ET AL.: "a silicon molecular beam epitaxy system dedicated to device oriented material research", JOURNAL OF CRYSTAL GROWTH, vol. 157, 1995, AMSTERDAM NL, pages 285 - 294, XP000572502 *
PRESTING H: "ULTRATHIN SIMGEN STRAINED LAYER SUPERLATTICES-A STEP TOWARDS SI OPTOELECTRONICS", SEMICONDUCTOR SCIENCE AND TECHNOLOGY, vol. 7, no. 9, 1 September 1992 (1992-09-01), pages 1127 - 1148, XP000335234 *
TANG Y S ET AL: "Fabrication and characterisation of Si-Si/sub 0.7/Ge/sub 0.3/ quantum dot light emitting diodes", ELECTRONICS LETTERS, 3 AUG. 1995, UK, vol. 31, no. 16, ISSN 0013-5194, pages 1385 - 1386, XP000525002 *
TANG Y S ET AL: "Optical emission from Si/Si/sub 1-x/Ge/sub x/ quantum wires and dots", 22ND INTERNATIONAL CONFERENCE ON THE PHYSICS OF SEMICONDUCTORS, PROCEEDINGS OF 22ND INTERNATIONAL CONFERENCE ON THE PHYSICS OF SEMICONDUCTORS, VANCOUVER, BC, CANADA, 15-19 AUG. 1994, ISBN 981-02-2979-8, 1995, SINGAPORE, WORLD SCIENTIFIC, SINGAPORE, pages 1735 - 1738 vol.2, XP000577797 *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0899796A2 (fr) * 1997-08-29 1999-03-03 Toshiba Corporation Dispositif semi-conducteur émetteur de lumière comprenant des nanocristaux
EP0899796A3 (fr) * 1997-08-29 2001-04-04 Toshiba Corporation Dispositif semi-conducteur émetteur de lumière comprenant des nanocristaux
US6027666A (en) * 1998-06-05 2000-02-22 The Governing Council Of The University Of Toronto Fast luminescent silicon
US6319427B1 (en) 1998-06-05 2001-11-20 Geoffrey A. Ozin Fast luminescent silicon
WO2001008225A1 (fr) * 1999-07-26 2001-02-01 France Telecom Procede de realisation d'un dispositif comprenant un empilement de plans de boites quantiques
FR2797093A1 (fr) * 1999-07-26 2001-02-02 France Telecom Procede de realisation d'un dispositif comprenant un empilement de plans de boites quantiques sur un substrat de silicium ou germanium monocristallin
US6690027B1 (en) 1999-07-26 2004-02-10 FRANCE TéLéCOM Method for making a device comprising layers of planes of quantum dots
WO2002073527A2 (fr) * 2001-03-09 2002-09-19 Wisconsin Alumni Research Foundation Dispositifs a points quantiques a l'etat solide et calcul quantique utilisant des portes logiques nanostructurees
WO2002073527A3 (fr) * 2001-03-09 2003-11-27 Wisconsin Alumni Res Found Dispositifs a points quantiques a l'etat solide et calcul quantique utilisant des portes logiques nanostructurees

Also Published As

Publication number Publication date
GB9506735D0 (en) 1995-05-24

Similar Documents

Publication Publication Date Title
US5427977A (en) Method for manufacturing porous semiconductor light emitting device
EP1735838B1 (fr) Dispositif optiques comportant des couches semi-conductrices texturees
Shcheglov et al. Electroluminescence and photoluminescence of Ge‐implanted Si/SiO2/Si structures
US6544870B2 (en) Silicon nitride film comprising amorphous silicon quantum dots embedded therein, its fabrication method and light-emitting device using the same
US7180648B2 (en) Electro-absorption modulator device and methods for fabricating the same
US9117954B2 (en) High efficiency nanostructured photovoltaic device manufacturing
US20120058586A1 (en) Optical devices featuring textured semiconductor layers
US6984538B2 (en) Method for quantum well intermixing using pre-annealing enhanced defects diffusion
JP2002141531A (ja) 太陽電池およびその製造方法
US9490318B2 (en) Three dimensional strained semiconductors
US20090280625A1 (en) Method for separating semiconductor layer from substrate
US6049090A (en) Semiconductor particle electroluminescent display
Zvonkov et al. Surfactant effect of bismuth in the MOVPE growth of the InAs quantum dots on GaAs
US20140116502A1 (en) Quantum nanodots, two-dimensional quantum nanodot array as well as semiconductor device using the same and production method therefor
JP4260480B2 (ja) 光学装置を製造する方法及び関係する改良
Helmy et al. Control of silica cap properties by oxygen plasma treatment for single-cap selective impurity free vacancy disordering
JP4514964B2 (ja) 光学用シリコン層を基板上に形成する方法および該方法による光学素材の製造方法
Semenova et al. Epitaxial growth of Quantum Dots on InP for device applications operating in the 1.55 µm wavelength range
WO1996030951A1 (fr) Photoemetteurs et photodetecteurs
JP2000188443A (ja) 半導体量子ドット素子とその製造方法
US7205624B2 (en) Self-aligned implanted waveguide detector
Yurasov et al. Enhancing the photoluminescence response of thick Ge-on-Si layers using photonic crystals
US7087923B2 (en) Photon source and a method of fabricating a photon source
EP1401028A2 (fr) Elément d'émission de lumière comprenant du diamant et son procédé de fabrication
Lockwood et al. Visible light from Si/SiO 2 superlattices in planar microcavities

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CA JP KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: CA