WO1996030801A1 - Liquid crystal display - Google Patents

Liquid crystal display Download PDF

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Publication number
WO1996030801A1
WO1996030801A1 PCT/JP1995/000590 JP9500590W WO9630801A1 WO 1996030801 A1 WO1996030801 A1 WO 1996030801A1 JP 9500590 W JP9500590 W JP 9500590W WO 9630801 A1 WO9630801 A1 WO 9630801A1
Authority
WO
WIPO (PCT)
Prior art keywords
film
liquid crystal
crystal display
display device
scanning wiring
Prior art date
Application number
PCT/JP1995/000590
Other languages
French (fr)
Japanese (ja)
Inventor
Kazuhiro Ogawa
Kikuo Ono
Nobutake Konishi
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1995/000590 priority Critical patent/WO1996030801A1/en
Publication of WO1996030801A1 publication Critical patent/WO1996030801A1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells

Definitions

  • the present invention relates to a structure of an active matrix type liquid crystal display device having a thin film transistor used as a display device for image information and character information of an office automation apparatus or the like as a switching element.
  • a thin film transistor used as a display device for image information and character information of an office automation apparatus or the like as a switching element.
  • An active matrix substrate equipped with a thin-film transistor (hereafter abbreviated as FT) as a switching element is protected on the top layer to prevent electrolytic corrosion of the metal material used for wiring and to stabilize the electrical conductivity of the TF.
  • a film is formed.
  • the protective film is formed on the entire surface of the image display area, and has a structure in which only the terminal portions of the scanning wiring and the video signal wiring are removed to connect an external circuit.
  • a protective film is present on the pixel electrode, electric charges are accumulated in the protective film during an image display period, and there is a problem that an afterimage is easily generated. Therefore, a structure in which the protective film on the pixel electrode is removed is applied for the purpose of reducing the afterimage.
  • the opening of the protective film on the pixel electrode is smaller than the pixel electrode pattern, and covers all wiring.
  • the main defects in the manufacturing process of the active matrix substrate are disconnection of scanning wiring and video signal wiring, short-circuiting of scanning wiring and video signal wiring, short-circuiting between video signal wirings, and point defects of display pixels. Is this point defect external?
  • the image cannot be controlled by the voltage supplied from the camera, and it always lights up in one of RGB, or refers to a defect in a pixel unit that always displays black or white.
  • the present invention pays particular attention to short-circuit defects between video signal lines and point defects.
  • short-circuit defects and point defect defects between video signal wirings There are several causes of short-circuit defects and point defect defects between video signal wirings. Among them, a large percentage are caused by amorphous silicon (hereinafter abbreviated as a-S i) and patterning defects of video signal wirings. This is mainly caused by adhesion of foreign matter before and after resist coating and defective development after exposure.
  • the defect rate can be reduced to some extent by devising the structure of the active matrix substrate, such as increasing the distance between the pixel electrode and the video signal wiring.
  • patterning defects of a-Si and video signal wiring occur with a substantially constant probability due to the cleanliness of the production line and the like. It is difficult to reduce the defects caused by the defect.
  • An object of the present invention is to provide a liquid crystal display device capable of reducing short circuit defects between video signal lines and point defect defects. Disclosure of the invention
  • the protective film is also separated on the pixel electrode.
  • the scanning wiring is covered with an insulating film, and the coated insulating film is exposed to the liquid crystal layer on a scanning wiring region between signal wirings where the protective film is separated.
  • the scanning wiring constitutes a gate electrode of the thin film transistor, and a gate insulating film having a ridge layer is formed on the gate electrode.
  • one end of the pixel electrode has a protective film separated from the scanning electrode.
  • the additional capacitance is formed by the extended portion extending over the scan wiring region, the extended portion, the scanning line formed below the portion, and the insulating layer covering the scanning line.
  • an additional capacitor upper electrode connected to one end of the pixel electrode and formed on the scanning wiring region from which the protective film is separated.
  • An additional capacitance is formed by the scanning wiring formed below this portion and the insulating layer covered by the scanning wiring.
  • the occurrence locations are extremely large on the scanning lines. Since the a-Si pattern exists at the TFT section or at the intersection of the scanning wiring and the video signal wiring, it is formed on or near the scanning wiring. Therefore, more defective patterns of a-Si connected to the video signal wiring occur on the scanning wiring than on the pixel electrode.
  • the protective film has an opening crossing at least a part of the scanning wiring of each pixel.
  • the protective film in the image display area is separated between the video signal wirings.
  • This has a structure in which the video signal wiring and the TFT section are covered with a protective film, and the pixel electrodes and the scanning wiring are opened in a substantially linear shape. With such a configuration, the defective pattern of a—Si remaining on the scanning wiring can be separated, and a short-circuit failure and a point defect failure between the video signal wirings can be relieved.
  • the above configuration is realized by, for example, etching a-Si again after processing the protective film.
  • the protective film is a silicon nitride Ya silicon oxide, by Etsuchin grayed said protective film by SF S-based dry etching method, can be removed failure pattern of self-aligned manner a- S i.
  • ITO indium oxide monoxide film
  • the gate insulating film constituting the thin film transistor is formed of a laminated film made of a plurality of different materials.
  • at least one layer of the gate insulating film is formed of a material different from the protective film.
  • the protective film can be selectively etched while leaving at least one layer of the gate insulating film. Therefore, all the gate insulating films are not etched when the protective film is etched, and there is no concern that the scanning wiring is exposed.
  • an alumina film as a laminated film constituting the gate insulating film.
  • a protective film made of SiN or the like is processed by a dry etching method using a fluorine-based gas.
  • the alumina film has excellent resistance to fluorine-based gas, and can be selectively etched with the protective film.
  • Specific examples of the laminated film include an alumina film and a SiN structure from the scanning wiring side. In this structure, when the etching time of the protective film is increased in consideration of the process margin, the gate insulating film SIN is etched at the removed portion of the protective film, but the scanning wiring is covered with the alumina film and the exposed portion is exposed. There is nothing to do.
  • the scanning wiring may be made of A 1, an alloy containing A 1 as a main component, or A 1 or A self-oxidizing film of the scanning wiring is formed as a laminated wiring coated with an alloy containing A A as a main component.
  • An alumina film can be easily formed by the anodic oxidation method, and an insulating film excellent in withstand voltage with few pinholes can be obtained.
  • the protective film in the image display area has a structure separated from the video signal wiring, and the scanning wiring is A 1, or an alloy containing A 1 as a main component, or A1 or a laminated wiring covered with an alloy containing A1 as a main component, and an insulating film constituting the additional capacitance is an alumina film which is a self-oxidized film of the scanning wiring.
  • This structure has two effects. One is that, similarly to the above operation, a defective pattern of a-Si or a video signal wiring can be removed, and a short circuit failure and a point defect failure between video signal wirings can be significantly reduced.
  • the insulating film (alumina film), which forms the additional capacitance is more likely to be side-etched than the upper electrode, which forms the additional capacitance. . Therefore, a substantially uniform additional capacitance can be formed over the entire image display area.
  • the upper electrode of the additional capacitance a conductive film containing Cr or A 1 as a main component, or a laminated film in which the conductive film is disposed as an upper layer is preferable.
  • the conductive film has excellent resistance to a fluorine-based gas. Therefore, by using a dry etching method using a fluorine-based gas for processing the protective film, the reduction in the film thickness of the upper electrode can be made very small, and an additional capacitance with very little variation can be formed over the entire image display area.
  • I T0 is a conductive film having excellent chemical resistance, and can sufficiently secure an etching selectivity even in dry etching using a fluorine-based gas.
  • One of the causes of the point defect is that a-Si connected to the video signal wiring material or the video signal electrode remains on the pixel electrode due to poor patterning.
  • at least a part of the end of the pixel electrode positioned substantially parallel to the video signal wiring is located in the opening of the protective film.
  • the defective pattern connected to the pixel electrode can be removed.
  • This structure can be realized by performing the etching process of a-Si or the video signal wiring material again after processing the protective film.
  • an insulating film having a small etching selectivity with respect to a—S i is used for the protective film, the bad buttery of a—S i is removed in a self-aligned manner when the protective film is etched.
  • the effect of relieving the above-described point defect increases as the length of the edge of the pixel electrode located at the opening of the protective film increases.
  • the protective film is desirably made of silicon nitride or silicon oxide. These films can be easily etched with a fluorine-based gas. Furthermore, since the fluorine-based gas also etches a-Si, the defective pattern of a-Si is also etched at the time of etching of the protective film, so that an additional process such as re-etching is not required.
  • FIG. 1 is a plan view of a unit pixel according to the liquid crystal display device of the first embodiment of the present invention:
  • FIG. 3 is a sectional view of a video signal wiring portion according to the liquid crystal display device of the first embodiment of the present invention.
  • FIG. 4 is a cross-sectional view of the additional capacitance section according to the liquid crystal display device of the first embodiment of the present invention.
  • FIG. 5 is a plan view of a unit pixel according to a liquid crystal display device of a second embodiment of the present invention.
  • FIG. 6 is a sectional view of an additional capacitance section according to the liquid crystal display device of the second embodiment of the present invention.
  • FIG. 7 is a sectional view of an additional capacitance section according to the liquid crystal display device of the second embodiment of the present invention.
  • FIG. 8 is a plan view of a unit pixel of a liquid crystal display device according to a third embodiment of the present invention.
  • FIG. 9 is a plan view of a unit pixel of a liquid crystal display device according to a fourth embodiment of the present invention.
  • FIG. 10 is a sectional view of a scanning wiring section according to a liquid crystal display device of a fourth embodiment of the present invention.
  • FIG. 11 is a sectional view of an additional capacitance section according to a liquid crystal display device of a fourth embodiment of the present invention.
  • FIG. 12 is a plan view of a unit pixel of a liquid crystal display device according to a fifth embodiment of the present invention.
  • FIG. 13 is a sectional view of the liquid crystal display device of the present invention.
  • FIG. 14 is an equivalent circuit diagram of the entire liquid crystal display device of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a plan view of a unit pixel showing a first embodiment of the present invention.
  • a scanning wiring 2 made of A 1 is formed on a glass substrate 1, and the surface thereof is covered with an alumina film 3.
  • the alumina film 3 can be formed in a self-aligned manner by an anodic oxidation method after the formation of the scanning wiring 2.
  • a gate insulating film 5 made of a SiN film, an intrinsic amorphous silicon (a-Si) film 6, an n-type a-Si film, a video signal wiring 7, and a source electrode 8 Become TFT formed Have been.
  • a pixel electrode 4 made of an indium-tin oxide film (IT 0) is formed on a glass substrate 1, and one end of the pixel electrode 4 is connected to a source electrode 8. The other end of the pixel electrode 4 extends over the scanning wiring of an adjacent pixel having an alumina film formed on the surface to form an additional capacitance.
  • FIG. 2 and FIG. 3 show the cross-sectional shapes of the section AA ′ and the section BB ′ in FIG.
  • a protective film 9 made of Si is formed on the video signal wiring and the FT.
  • the gate insulating film SIN5 and the a-Si film 6 have substantially the same planar shape. By making the plane shapes substantially the same, these films can be processed by one photo-etching step, and the manufacturing process can be shortened.
  • the feature of the present embodiment is that the protective film 9 has a structure separated between the video signal wirings 7, and the protective film 9 is removed on the pixel electrode 4 and the scanning wiring 2. It is.
  • the registration pattern defect at the time of the a-Si not- It often occurs on the above.
  • the protective film 9 is formed into the structure shown in Fig. 1 and applying a dry etching method using SF to process the protective film, a pattern defect remains on the scanning wiring 2 when the protective film 9 is processed.
  • A—S i is also automatically removed.
  • SiN is used for the protective film 9, but the same effect can be obtained even when Si ⁇ X.
  • the patterning failure of the video signal wiring is the same as the patterning failure of a-Si described above. Similarly on scan wiring 2 Many occur. As shown in FIG. 1, this can also be removed by removing the protective film 9 on the scanning wiring 2 and etching the material of the video signal wiring 7 again after processing the protective film 9. At this time, if the scanning wiring and the video signal wiring 7 are exposed at the terminal portion, the terminal portion may disappear when the etching is performed again.
  • a force of covering the scanning wiring or the video signal wiring 7 of the terminal portion with ITO constituting the pixel electrode 4 or a conductive film constituting the scanning wiring or the video signal wiring 7 is formed inside the protective film 9.
  • the above problem can be solved by disposing the terminal with ITO connected to the conductive film. This is because ITO has excellent chemical resistance and can secure a sufficient etching ratio with respect to the protective film even in dry etching using a fluorine-based gas.
  • a short circuit defect and a point defect defect between video signal lines in a liquid crystal display device can be significantly reduced, and the production yield of the liquid crystal display device can be improved.
  • an alumina film 3 was employed as a part of the gate insulating film.
  • the alumina film has a sufficient resistance to dry etching using a fluorine-based gas, and can selectively etch only the protective film 9 formed on the alumina film 3. Generally, the etching is performed for a longer time than the end time in order to prevent the etching residue of the protective film 9 from being generated. Even under such conditions, the scanning wiring 2 is covered with the alumina film 3 and is not exposed. In this embodiment, the scanning wiring 2 is made of A 1, and the A 1 is anodized to form an alumina film 3. By using the anodic oxidation method, an alumina film having few defects such as pinholes and excellent in withstand voltage can be obtained.
  • Fig. 4 shows the cross-sectional structure of the additional capacitance section (C-C 'section in Fig. 1).
  • IT 0 extending from the pixel electrode 4 is used as the upper electrode of the additional capacitance.
  • IT ⁇ is a conductive film having excellent chemical resistance, and the SiO 2 film 9 as a protective film on IT ⁇ can be selectively removed by dry etching using a fluorine-based gas. Therefore, the pattern of the IT ⁇ pattern is not changed due to the etching of the IT ⁇ ⁇ pattern when the protective film 9 is processed, and the variation of the additional capacitance in the panel surface can be reduced.
  • the structure is such that the protective film in the image display area is separated between the video signal wirings. Further, as a means for improving the production yield of the liquid crystal display device, a protective film at the terminal portion is also separated between the video signal wirings. Can be remedied: Example 2
  • FIG. 5 is a plan view of a unit pixel showing a second embodiment of the present invention:
  • a scanning wiring 2 made of A 1 is formed on a glass substrate 1, and the surface thereof is covered with an alumina film 3. .
  • the alumina film 3 can be formed in a self-aligned manner by anodizing after patterning the scanning electrode 2.
  • a TFT composed of a gate insulating film 5 made of an S 1 X film, an a-Si film 6, an n-type a-Si film, a video signal wiring 7, and a source electrode 8 is formed. I have.
  • a pixel electrode 4 made of an indium tin oxide film (I-cho) is formed, and one end thereof is connected to a source electrode 8.
  • the other end of the pixel electrode 4 is connected to an upper electrode 20 for additional capacitance, and forms an additional capacitance with the scanning wiring 2 of an adjacent pixel having an alumina film 3 formed on the surface.
  • the upper electrode 20 for additional capacity is composed of Cr.
  • a protective film 9 made of SiN is formed on the video signal wiring 7 and the TFT.
  • the gate insulating film S i ⁇ ′ film 5 and the a-S i film 6 have substantially the same planar shape, thereby simplifying the manufacturing process.
  • FIG. 6 shows a cross-sectional shape of a portion D-D 'in FIG.
  • the additional capacitance is formed from the glass substrate 1 side in the order of the scanning wiring 2 of A1, the alumina film 3, and the upper electrode 20 for additional capacitance composed of Cr.
  • the additional electrode 20 for additional capacitance is composed of Cr. That is the point.
  • Cr has a very low etching rate in dry etching using a fluorine-based gas, so that the pattern of the upper electrode 20 for the additional capacitance does not disappear or shrink during processing of the protective film 9, and is formed within the substrate. An additional capacitance with less variation can be formed.
  • Cr is used as the upper electrode 20 of the additional capacitor.
  • a similar effect can be obtained with a conductive film containing Cr or A 1 as a main component.
  • FIG. 6 shows a specific example.
  • the scan electrode 2 of A 1 is used as a lower electrode of the additional capacitor 2
  • the insulating film is composed of the alumina film 3 which is the anodic oxide film of the above A 1
  • the upper electrode is an upper electrode for additional capacitor consisting of Ti from the alumina film side.
  • the lower electrode 20 ′ and the upper electrode for additional capacitance 20 ′ composed of A 1. It is the surface of the laminated wiring that is exposed to the etching gas when processing the protective film 9. Since the surface layer is made of A ⁇ , the upper electrodes 20 ′ and 20 ′′ of the additional capacitance do not disappear when the protective film 9 is processed.
  • FIG. 8 is a plan view of a unit pixel showing a third embodiment of the present invention.
  • a scan wiring 2 'made of Cr is formed on a glass substrate 1, and a gate insulating film 5, a-Si film 6, an n-type a-Si film, an n-type a-Si film, A TFT composed of the signal wiring 7 and the source electrode 8 is formed.
  • Glass substrate 1 A pixel electrode 4 made of an indium-tin oxide film (ITO) is formed on the upper side, and one end thereof is connected to a source electrode 8. The other end of the pixel electrode 4 is connected to the upper electrode 20 of the additional capacitance, and forms an additional capacitance with the scanning wiring 2 of the adjacent pixel.
  • a protective film 9 made of Si is formed on the video signal wiring 7 and the TF ⁇ , and the protective film 9 is separated from the video signal wiring 7. .
  • the present embodiment is characterized in that the gate insulating film 5 is made of S 1 X which is the same material as the protective film 9.
  • the structure of this embodiment is manufactured according to the following procedure.
  • a film of Cr is formed on a glass substrate 1 to form a scanning wiring 2 'pattern.
  • a SiO x film 5, an a-Si film 6, and an n-type a-Si are continuously formed by the Frosma CVD method, and the TFT portion and the a at the intersection of the scanning wiring 2 ′ and the video signal wiring 7 are formed.
  • Six on the pixel electrode 4 is dry-etched into a pattern shown by a dotted line in FIG.
  • a film of the video signal wiring 7 material is formed and processed into the video signal wiring 7 pattern.
  • S IX is formed as a protective film 9 and processed into a pattern shown by a dotted line in (b) of FIG. At this time, comparing the film thicknesses of the SiN in the portions A and B in FIG. 8, the portion B is thicker by the thickness of the gate insulating film. Accordingly, the etching time of the protective film 9 is By setting the time between the etching end time of the portion S i.
  • the planar shape of the protective film 9 according to the present invention can be manufactured without any problem by the above manufacturing method.
  • the structure of this embodiment can remove the defective pattern of a-Si and the defective pattern of the video signal wiring 7 remaining on the scanning wiring 2 ′. Short circuit failure between video signal wiring 7 and point defect failure can be remedied: Embodiment 4
  • FIG. 9 is a plan view of a unit pixel showing a fourth embodiment of the present invention.
  • a scanning electrode 2 ⁇ made of Ta is formed, and on its surface, a gate insulating film consisting of a Ta 0 X film 5 ′ and a Si X film 5 is formed from the scanning electrode 2 ⁇ side.
  • a TFT comprising an Si film 6, an n-type a-Si film, a video signal wiring 7, and a source electrode 8 is formed.
  • a pixel electrode 4 made of an indium monotin oxide film (ITO) is formed on a glass substrate 1, and one end of the pixel electrode 4 is connected to a source electrode 8.
  • ITO indium monotin oxide film
  • the other end of the pixel electrode 4 is connected to Cr, which is the upper electrode 20 for the additional capacitance, and forms an additional capacitance between itself and the scanning electrode 2 of the adjacent pixel.
  • a protection film 9 made of SiN is formed on the video signal wiring 7 and the TFT, and the protection film 9 is separated between the video signal wirings 7.
  • the feature of the present embodiment is a structure in which the protective film 9 on the pixel electrode 4 and the scanning wiring 2 is partially removed, and the protective film 9 is separated between the video signal wirings 7 and the gate.
  • the insulating film is composed of a laminated film of the SiN film 5ZTaOx film 5 '.
  • the protective film 9 is separated between the video signal wirings 7, short-circuit defects and point defects due to a-Si and poor patterning of the video signal wiring can be reduced as in the first embodiment.
  • FIG. 10 shows a cross-sectional shape of a portion EE ′ in FIG.
  • the 3 1 ′ film 5 T a O x film 5 ′ is formed so as to cover at least the scanning wiring 2 before forming the protective film 9.
  • the SiN film 5 as the gate insulating film located at a portion where the SiN film 9 as the protective film is removed is removed when the SiM film 9 as the protective film is etched.
  • the scanning wiring 2 ′ is covered with the Ta ⁇ X film 5 ′, which is another insulating film constituting the gate insulating film, and is not exposed.
  • FIG. 11 shows a cross-sectional shape of the additional capacitance section (section FF ′ in FIG. 10).
  • the gate insulating film at the portion where the protective SiN film 9 is to be removed, the SiN film 5 which is the film to be removed is a force to be removed. 20 serves as a mask, and the SiOx film 5 as a gate insulating film remains.
  • the insulating film of the additional capacitance is formed by a laminated film of the Six film 5ZTa0x film 5 '.
  • the present structure has a structure in which the SIX film 5 as the gate insulating film remains only under the protective film and under the upper electrode of the additional capacitor.
  • the gate insulating film of the present embodiment In addition to the structure of the gate insulating film of the present embodiment, similar effects can be obtained by forming a laminated film composed of a plurality of different materials. This is because at least one layer of the gate insulating film is made of a material different from that of the protective film, so that the protective film can be selectively etched and the scanning wiring is not exposed.
  • I 2 [2 is a plan view of a unit pixel showing a fifth embodiment of the present invention.
  • the alumina film 3 can be formed in a self-aligned manner by anodizing after the patterning of the scanning wiring 2.
  • a TFT composed of a gate insulating film 5, composed of a Si— ⁇ 'film, a—Si film 5, an n-type a—Si film, a video signal wiring 7, and a source electrode 8 is formed. ing.
  • a pixel electrode 4 made of an indium tin oxide film (IT ⁇ ) is formed, and one end thereof is connected to a source electrode 8.
  • the other end of the pixel electrode 4 extends to above the scanning wiring 2 of an adjacent pixel having the alumina film 3 formed on the surface, and forms an additional capacitance.
  • a protection film 9 made of SIX is formed on the video signal wiring 7 and the TFT, and the protection film 9 is separated between the video signal wirings 7. 1 ⁇
  • at least a part of the end of the pixel electrode 4 parallel to the video signal wiring 7 is located at the opening of the protective film 9 as shown in the part C in FIG. It is characterized by being located.
  • This embodiment has the following effects in addition to the effects shown in the first embodiment.
  • One of the causes of the point defect is that a-Si connected to the video signal wiring material or the video signal wiring 7 on the pixel electrode 4 remains due to a pattern defect.
  • the defective pattern of a—S i that connects the video signal line 7 and the pixel electrode 4 during the processing of the S i X film 9 serving as the protection film can be removed.
  • the defective pattern of the video signal wiring 7 connected to the pixel electrode 4 can be removed. This effect increases as the length of the edge of the pixel electrode 4 located at the opening of the protective film 9 increases.
  • FIG. 13 is a schematic sectional view of a liquid crystal display device showing the structure of this embodiment.
  • the scanning wiring 2 and the video signal wiring 7 are formed in a matrix, and are made of ITO via the TFT formed near the intersection.
  • the opposing electrode 104 made of IT ⁇ and the color filter 102, the color filter protective film 103, the black matrix for shading A light-shielding film 101 for forming a pattern is formed. No.
  • the central part in Fig. 13 is a cross section of one pixel part, the left part is a cross section of the part where the external lead-out terminal is present at the left edge part of a pair of glass substrates, and the right part is a external part at the right side part of a pair of glass substrates.
  • the cross section of a portion where no terminal is present is shown.
  • the sealing material SL shown on the left and right sides of FIG. 13 is configured to seal the liquid crystal layer 2 ⁇ 0, excluding the liquid crystal filling port (not shown) It is formed along the entire edge of the glass substrate 1, 100.
  • the sealing material is made of, for example, epoxy resin.
  • the counter electrode 104 on the side of the counter glass substrate 100 is connected at least at one position to an external lead wire formed on the glass substrate 1 by a silver paste material SIL.
  • This external lead-out wiring is formed in the same manufacturing process as each of the scanning wiring 2, the source electrode 8, and the video signal wiring 7.
  • Each layer of alignment film 0 RI 1, 0 RI 2, pixel electrode 4, protective film 9, color filter protective film 103, and gate insulating film SIN film 5 are inside the sealing material SL.
  • the polarizing plates 105, 105 ' are formed on the outer surfaces of a pair of glass substrates 1, 100, respectively.
  • the liquid crystal layer 200 is sealed between a lower alignment film R i1 for setting the direction of liquid crystal molecules of the liquid crystal layer 200 and the upper alignment film ⁇ RI2, and is sealed with a sealing material SL.
  • the lower alignment film RI 1 is formed on the protective film 9 on the glass substrate 1 side or on the pixel electrode 4.
  • a D-drive type liquid crystal display device is constructed.
  • the TFT substrate employing the TF T substrate illustrated in FIG. 1 has the following structure.
  • a scanning wiring 2 made of A 1 is formed on a glass substrate 1, and the surface thereof is covered with an alumina film 3.
  • the alumina film 3 can be formed in a self-aligned manner by anodic oxidation after patterning the scanning wiring 2.
  • a gate insulating film ⁇ consisting of a SiN film, a-Si film 6, an n-type a-Si film, a video signal wiring 7, and a TFT consisting of a source electrode 8 Is formed.
  • a pixel electrode 4 made of (IT 0) is formed, and one end of the pixel electrode 4 is connected to the source electrode 8.
  • the other end of the pixel electrode 4 extends to the scanning wiring 2 of an adjacent pixel having an alumina film formed on the surface to form an additional capacitance: a protective film made of Si on the video signal wiring 7 and the TFT. 9 are formed and are separated between the video signal wirings 7 in the image display area.
  • the TF-cables shown in FIG. 5, FIG. 8, FIG. 9, FIG. Fig. 14 shows the equivalent circuit of the whole display device.
  • X: G is the video signal wiring connected to the pixel on which the green filter G is formed.
  • the video signal wiring is connected to the video signal activation circuit ⁇ .
  • S-J converts the information for the cathode ray tube from the power supply circuit and the host (upper processing unit) to obtain multiple divided and stabilized voltage sources from one voltage source to the information for the liquid crystal panel. It is a circuit including a circuit.
  • the liquid crystal display device configured as described above can significantly reduce short circuit defects and point defect defects between video signal wirings, and can manufacture liquid crystal display devices with high yield.
  • liquid crystal display device As described above, according to the present invention, short-circuit defects and point defect defects between video signal wirings caused by patterning defects of a-Si films and video signal wirings can be significantly reduced. Therefore, a liquid crystal display device can be manufactured with a high yield. Industrial applicability As described above, the liquid crystal display device according to the present invention reduces short circuit defects and point defect defects between video signal lines, and is useful for improving the production yield.

Abstract

On an active matrix substrate constituting a liquid crystal display, protective films which are separated from each other in a scanning wiring area between adjacent signal lines are formed to protect video signal lines and a thin film transistor. The protective films are separated from each other on picture element electrodes. The scanning wires are coated with insulating films and the insulating films are exposed from a liquid crystal layer in the scanning wire area. The scanning wiring constitutes the gate electrode of the thin film transistor and a laminated gate insulating film is formed on the gate electrode.

Description

明 細 書  Specification
液晶表示装置 技術分野  Liquid crystal display technology
本発明は O A機器等の画像情報, 文字情報の表示装置と て用いる薄 膜トランジスタをスイッチング素子として備えたアクティ ブマ ト リクス 方式の液晶表示装置の構造に関する。 冃 JP, &. fer  The present invention relates to a structure of an active matrix type liquid crystal display device having a thin film transistor used as a display device for image information and character information of an office automation apparatus or the like as a switching element.冃 JP, &. Fer
薄膜卜ランジスタ(以下、 丁 F Tと略記)をスィ ッチング素子として備 えたアクティブマ 卜 リクス基板は、 配線に使用する金属材 の電食防止 や T F丁の電気的安定化のために最上層に保護膜を形成している。 従来、 前記保護膜は画像表示領域の全面に形成され、 外部回路を接続するため に走査配線及び映像信号配線の端子部のみ除去する構造であった。 しか し、 画素電極上に保護膜が存在すると、 画像の表示期間中に前記保護膜 に電荷が蓄積され、 残像が発生しやすいという問題が生じた。 そこで、 残像を低減する目的から、 画素電極上の保護膜を除去した構造が適用さ れている。 このような例として、 テレビジョン学会技術報告 1 9 8 8年 8月発行、 1 〜 6頁 (I TEJ Techni cal Report V ol . 1 2 . o. 3 2 . pp. 1 〜 6 , I D ' 8 8 - 7 0 (Aug. 1 9 8 8 ) ) )に記載がある。 この例 では、 画素電極上の保護膜の開口部は画素電極バターンよりも小さく、 すべての配線上を被覆している。  An active matrix substrate equipped with a thin-film transistor (hereafter abbreviated as FT) as a switching element is protected on the top layer to prevent electrolytic corrosion of the metal material used for wiring and to stabilize the electrical conductivity of the TF. A film is formed. Conventionally, the protective film is formed on the entire surface of the image display area, and has a structure in which only the terminal portions of the scanning wiring and the video signal wiring are removed to connect an external circuit. However, if a protective film is present on the pixel electrode, electric charges are accumulated in the protective film during an image display period, and there is a problem that an afterimage is easily generated. Therefore, a structure in which the protective film on the pixel electrode is removed is applied for the purpose of reducing the afterimage. As an example of this, the Technical Report of the Institute of Television Engineers of Japan, August 1998, pp. 1-6 (ITE Technical Report Vol. 12. O. 32. Pp. 1-6, ID '8 8-70 (Aug. 1 988)))). In this example, the opening of the protective film on the pixel electrode is smaller than the pixel electrode pattern, and covers all wiring.
液晶表示装置の課題の 1つに、 製造歩留まりの向上が挙げられる。 ァ クティブマ トリクス基板の製造工程における不良の主なものとしては、 走査配線及び映像信号配線の断線, 走査配線と映像信号配線の短絡, 映 像信号配線間の短絡, 表示画素の点欠陥がある。 この点欠陥は、 外部か ら供給される電圧で画像を制御できず、 常に R G Bの何れかに点灯して いたり、 常に黒表示或いは白表示になる画素単位の欠陥を指す。 One of the issues with liquid crystal display devices is improving the production yield. The main defects in the manufacturing process of the active matrix substrate are disconnection of scanning wiring and video signal wiring, short-circuiting of scanning wiring and video signal wiring, short-circuiting between video signal wirings, and point defects of display pixels. Is this point defect external? The image cannot be controlled by the voltage supplied from the camera, and it always lights up in one of RGB, or refers to a defect in a pixel unit that always displays black or white.
本発明では、 特に映像信号配線間の短絡不良と点欠陥に注目する。 映 像信号配線間の短絡不良や点欠陥不良の発生原因はいくつかあり、 その 中でも非晶質シリコン (以下、 a— S i と略記) 並びに映像信号配線の パターニング不良に起因する割合が多い。 これは主に、 レジス 卜塗布前 後の異物付着や露光後の現像不良が原因となり発生する。 点欠陥不良を 低減する対策として、 画素電極と映像信号配線間の距離を大きくするな ど、 アクティブマ ト リクス基板の構造を工夫することで、 不良率をある 程度削減できる。 しかし、 a— S i や映像信号配線のパターニング不良 は、 製造ラインのク リーン度などに起因してほぼ一定の確率で発生し、 上記従来技術に示すァクティブマ 卜リクス基板の構造では前記パタ一二 ング不良に起因する不良を削減することは困難である。  The present invention pays particular attention to short-circuit defects between video signal lines and point defects. There are several causes of short-circuit defects and point defect defects between video signal wirings. Among them, a large percentage are caused by amorphous silicon (hereinafter abbreviated as a-S i) and patterning defects of video signal wirings. This is mainly caused by adhesion of foreign matter before and after resist coating and defective development after exposure. As a measure to reduce point defect defects, the defect rate can be reduced to some extent by devising the structure of the active matrix substrate, such as increasing the distance between the pixel electrode and the video signal wiring. However, patterning defects of a-Si and video signal wiring occur with a substantially constant probability due to the cleanliness of the production line and the like. It is difficult to reduce the defects caused by the defect.
本発明の目的は、 映像信号配線間の短絡不良並びに点欠陥不良を削減 できる液晶表示装置を提供することにある。 発明の開示  An object of the present invention is to provide a liquid crystal display device capable of reducing short circuit defects between video signal lines and point defect defects. Disclosure of the invention
本発明の液晶表示装置を構成するアクティブマ ト リクス基板には、 隣 接する信号配線間の走査配線領域上で分離された、 映像信号配線及び薄 膜トランジスタとを保護する保護膜が形成されている。  On the active matrix substrate constituting the liquid crystal display device of the present invention, a protective film for protecting the video signal wiring and the thin film transistor, which is separated on the scanning wiring area between adjacent signal wirings, is formed. .
保護膜は、 また、 画素電極上で分離されている。  The protective film is also separated on the pixel electrode.
走査配線は絶縁膜で被覆されており、 被覆された絶縁膜は保護膜が分 離される信号配線間の走査配線領域上で上記液晶層に露出している。 走査配線は薄膜トランジスタのゲー 卜電極を構成し、 このゲー 卜電極 上には稜層されたゲー 卜絶縁膜が形成されている。  The scanning wiring is covered with an insulating film, and the coated insulating film is exposed to the liquid crystal layer on a scanning wiring region between signal wirings where the protective film is separated. The scanning wiring constitutes a gate electrode of the thin film transistor, and a gate insulating film having a ridge layer is formed on the gate electrode.
本発明の実施態様によれば、 画素電極の一端は保護膜が分離された走 査配線領域上に延在され、 この延在された部分と、 この部分の下に形成 された走査配線と、 及び、 この走査配線に被覆された絶縁層とにより付 加容量が形成される。 According to the embodiment of the present invention, one end of the pixel electrode has a protective film separated from the scanning electrode. The additional capacitance is formed by the extended portion extending over the scan wiring region, the extended portion, the scanning line formed below the portion, and the insulating layer covering the scanning line.
更に、 本発明の実施態様によれば、 画素電極の一端に接続され、 保護 膜が分離された走査配線領域上に形成された付加容量用上部電極を有.し、 この付加容量用上部電極、 この部分の下に形成された走査配線と、 及び、 この走査配線に被覆された絶縁層とにより付加容量が形成される。  Further, according to an embodiment of the present invention, there is provided an additional capacitor upper electrode connected to one end of the pixel electrode and formed on the scanning wiring region from which the protective film is separated. An additional capacitance is formed by the scanning wiring formed below this portion and the insulating layer covered by the scanning wiring.
映像信号配線間の短絡不良や点欠陥不良が a — S i のパターニング不 良で発生する場合、 その発生場所は走査配線上に非常に多い。 a— S i パターンは、 T F T部や走査配線と映像信号配線の交差部に存在するた め、 走査配線上もしくはその近傍に形成される。 従って、 映像信号配線 に接続された a - S i の不良パターンも画素電極上と比較して、 走査配 線上で多く発生する。  When short-circuit defects and point defect defects between video signal lines occur due to poor patterning of a-Si, the occurrence locations are extremely large on the scanning lines. Since the a-Si pattern exists at the TFT section or at the intersection of the scanning wiring and the video signal wiring, it is formed on or near the scanning wiring. Therefore, more defective patterns of a-Si connected to the video signal wiring occur on the scanning wiring than on the pixel electrode.
本発明によれば、 保護膜は各画素の走査配線上の少なく とも一部を横 切る開口部を有することになる。 また、 画像表示領域内の保護膜は映像 信号配線間で分離される。 これは、 映像信号配線上及び T F T部は保護 膜で被覆し、 画素電極及び走査配線上を略線状に開口した構造である。 このように構成することにより、 走査配線上に残った a— S i の不良パ ターンを分離でき、 映像信号配線間の短絡不良や点欠陥不良を救済でき る。  According to the present invention, the protective film has an opening crossing at least a part of the scanning wiring of each pixel. The protective film in the image display area is separated between the video signal wirings. This has a structure in which the video signal wiring and the TFT section are covered with a protective film, and the pixel electrodes and the scanning wiring are opened in a substantially linear shape. With such a configuration, the defective pattern of a—Si remaining on the scanning wiring can be separated, and a short-circuit failure and a point defect failure between the video signal wirings can be relieved.
上述の構成は例えば、 保護膜の加工後に再度 a — S i をエッチングす ることで実現される。 保護膜を窒化シリコンゃ酸化シリコンで構成した 場合には、 S F S 系の ドライエッチング法により前記保護膜をエツチン グすることで、 自己整合的に a— S i の不良パターンを除去できる。 こ の場合、 端子部は I T O (インジウムースズ一酸化膜) で被覆しておき、 a - S iの再エッチング時に悪影響を及ぼさない構造にすることが望ま しい。 The above configuration is realized by, for example, etching a-Si again after processing the protective film. The case where the protective film is a silicon nitride Ya silicon oxide, by Etsuchin grayed said protective film by SF S-based dry etching method, can be removed failure pattern of self-aligned manner a- S i. In this case, it is desirable to cover the terminals with ITO (indium oxide monoxide film) so that they do not adversely affect the re-etching of a-Si. New
映像信号配線間の短絡不良の別の原因として、 映像信号配線のバタ一 ニング不良によリ隣合う映像信号配線が接続されるものがある。 本発明 の適用に際し保護膜の加工後に再度映像信号配線の加工時と同一のエツ チング処理を施すことで、 映像信号配線の不良パターンを除去でき、 映 像信号配線間の短絡不良を救済できる。 さらに、 液晶表示装置の製造歩 留ま りを向上する手段としては、 端子部における保護膜も映像信号配線 間で分離させる。 これにより、 端子部で発生する映像信号配線間の短絡 不良も救済できる。  As another cause of the short circuit failure between the video signal wirings, there is one in which adjacent video signal wirings are connected due to poor patterning of the video signal wirings. By applying the same etching process as when processing the video signal wiring again after processing the protective film when applying the present invention, a defective pattern of the video signal wiring can be removed, and a short-circuit failure between the video signal wirings can be relieved. Further, as a means for improving the manufacturing yield of the liquid crystal display device, a protective film in the terminal portion is also separated between the video signal wirings. As a result, a short circuit between the video signal wirings at the terminal can be remedied.
薄膜トランジスタを構成するゲー 卜絶縁膜は、 複数の異なる材料から なる積層膜で構成することが望ましい: この場合、 ゲー ト絶縁膜の少な く とも 1層は保護膜と異なる材料で構成されるため、 ゲ一 卜絶緣膜の少 なく とも 1層は残して保護膜を選択的にエッチングできる。 従って、 保 護膜のエッチング時にすべてのゲー 卜絶縁膜がエッチングされることは なく、 走査配線が露出する懸念はなくなる。  It is desirable that the gate insulating film constituting the thin film transistor is formed of a laminated film made of a plurality of different materials. In this case, at least one layer of the gate insulating film is formed of a material different from the protective film. The protective film can be selectively etched while leaving at least one layer of the gate insulating film. Therefore, all the gate insulating films are not etched when the protective film is etched, and there is no concern that the scanning wiring is exposed.
ゲ一 ト絶緣膜を構成する積層膜として、 アルミナ膜を用いることが望 ましい。 一般に、 S i Nなどで構成する保護膜は、 フッ素系ガスを用い た ドライエッチング法で加工する。 アルミナ膜はフッ素系ガスに対する 耐性に優れており、 保護膜との選択エッチングが可能となる。 積層膜の 具体的な例としては、 走査配線側からアルミナ膜、 S i Nの構造が挙げ られる。 本構造では、 プロセスマージンを考慮して保護膜のエッチング 時間を增加すると、 前記保護膜の除去部では前記ゲー ト絶縁膜 S i Nは エッチングされるが、 走査配線はアルミナ膜で被覆され、 露出すること はない。  It is desirable to use an alumina film as a laminated film constituting the gate insulating film. Generally, a protective film made of SiN or the like is processed by a dry etching method using a fluorine-based gas. The alumina film has excellent resistance to fluorine-based gas, and can be selectively etched with the protective film. Specific examples of the laminated film include an alumina film and a SiN structure from the scanning wiring side. In this structure, when the etching time of the protective film is increased in consideration of the process margin, the gate insulating film SIN is etched at the removed portion of the protective film, but the scanning wiring is covered with the alumina film and the exposed portion is exposed. There is nothing to do.
ゲー 卜絶縁膜を構成する積層膜にアルミナ膜を適用する例として、 走 査配線を A 1、 或いは A 1 を主成分とする合金、 或いは前記 A 1 または A 丄 を主成分とする合金で被覆した積層配線として、 かつ、 前記走査配 線の自己酸化膜を形成する。 陽極酸化法により容易にアルミナ膜を形成 でき、 ピンホールなどの少ない絶縁耐圧に優れた絶縁膜が得られる。 付加容量を備える場合、 少なく とも画像表示領域内の保護膜が、 映像 信号配線間で分離された構造と し、 かつ、 前記走査配線を A 1 、 或いは A 1 を主成分とする合金、 或いは前記 A 1 または A 1 を主成分とする合 金で被覆した積層配線とし、 かつ、 前記付加容量を構成する絶縁膜を前 記走査配線の自己酸化膜であるアルミナ膜とする。 この構造により 2つ の効果が得られる。 1 つは、 上記作用と同様に a— S i或いは映像信号 配線の不良パタ一ンを除去でき、 映像信号配線間の短絡不良並びに点欠 陥不良を著しく削減できる。 もう 1 つは、 保護膜の加工時にアルミナ膜 は殆ど膜減り しないため、 付加容量を構成する上部電極に対して付加容 量を構成する絶緣膜 (アルミナ膜) がサイ ドエッチングする二とがない。 従って、 画像表示領域全面において、 ほぼ均一な付加容量を形成できる。 付加容量の上部電極としては、 C r或いは A 1 を主成分とする導電膜、 或いは前記導電膜を上層に配置した積層膜が望ましい。 前記導電膜はフ ッ素系ガスに対する耐性に優れている。 従って、 保護膜の加工をフッ素 系ガスを用いた ドライエッチング法を用いることで、 前記上部電極の膜 減りを非常に小さくでき、 画像表示領域全面においてばらつきの非常に 小さい付加容量を形成できる。 As an example of applying an alumina film to the laminated film constituting the gate insulating film, the scanning wiring may be made of A 1, an alloy containing A 1 as a main component, or A 1 or A self-oxidizing film of the scanning wiring is formed as a laminated wiring coated with an alloy containing A A as a main component. An alumina film can be easily formed by the anodic oxidation method, and an insulating film excellent in withstand voltage with few pinholes can be obtained. When the additional capacitance is provided, at least the protective film in the image display area has a structure separated from the video signal wiring, and the scanning wiring is A 1, or an alloy containing A 1 as a main component, or A1 or a laminated wiring covered with an alloy containing A1 as a main component, and an insulating film constituting the additional capacitance is an alumina film which is a self-oxidized film of the scanning wiring. This structure has two effects. One is that, similarly to the above operation, a defective pattern of a-Si or a video signal wiring can be removed, and a short circuit failure and a point defect failure between video signal wirings can be significantly reduced. Secondly, since the alumina film is hardly reduced during the processing of the protective film, the insulating film (alumina film), which forms the additional capacitance, is more likely to be side-etched than the upper electrode, which forms the additional capacitance. . Therefore, a substantially uniform additional capacitance can be formed over the entire image display area. As the upper electrode of the additional capacitance, a conductive film containing Cr or A 1 as a main component, or a laminated film in which the conductive film is disposed as an upper layer is preferable. The conductive film has excellent resistance to a fluorine-based gas. Therefore, by using a dry etching method using a fluorine-based gas for processing the protective film, the reduction in the film thickness of the upper electrode can be made very small, and an additional capacitance with very little variation can be formed over the entire image display area.
さらに、 付加容量の上部電極を画素電極から延在する I T Oを用いる ことで付加容量のばらつきを小さくできる。 I T 0は耐薬品性に優れた 導電膜であり、 フッ素系ガスを用いた ドライエッチングに対しても十分 にエッチングの選択比を確保できるからである。  Further, by using the ITO extending from the pixel electrode to the upper electrode of the additional capacitance, the variation of the additional capacitance can be reduced. This is because I T0 is a conductive film having excellent chemical resistance, and can sufficiently secure an etching selectivity even in dry etching using a fluorine-based gas.
また、 点欠陥の発生原因の 1 つに、 画素電極上に映像信号配線材料や 映像信号電極と接続された a— S i がパターニング不良によリ残るもの がある。 本発明によれば、 映像信号配線と略平行に位置する画素電極の 端部のうち少なく とも一部が、 保護膜の開口部に位置する構造とする。 この構造により、 画素電極と接続していた不良パターンを除去できる。 この構造は保護膜の加工後に a— S i 或いは映像信号配線材料のエッチ ング処理を再度実施することで実現できる。 a— S i に対してエツチン グの選択比が小さい絶縁膜を保護膜に採用した場合、 保護膜のエツチン グ時に自己整合的に a— S iの不良バタ一ンは除去される。 以上の点欠 陥を救済する効果は、 保護膜の開口部に位置する画素電極の端部の長さ を大きくするほど大きい。 One of the causes of the point defect is that a-Si connected to the video signal wiring material or the video signal electrode remains on the pixel electrode due to poor patterning. There is. According to the present invention, at least a part of the end of the pixel electrode positioned substantially parallel to the video signal wiring is located in the opening of the protective film. With this structure, the defective pattern connected to the pixel electrode can be removed. This structure can be realized by performing the etching process of a-Si or the video signal wiring material again after processing the protective film. When an insulating film having a small etching selectivity with respect to a—S i is used for the protective film, the bad buttery of a—S i is removed in a self-aligned manner when the protective film is etched. The effect of relieving the above-described point defect increases as the length of the edge of the pixel electrode located at the opening of the protective film increases.
保護膜は窒化シリコン或いは酸化シリコンで構成することが望ましい。 これらの膜はフッ素系ガスで容易にエッチングできる。 さらに、 フッ素 系ガスは a— S i もエッチングするため、 保護膜のエツチング時に a— S i の不良パターンも同時にエッチングされ、 再エッチングなどの追加 プロセスを必要としない。 図面の簡単な説明  The protective film is desirably made of silicon nitride or silicon oxide. These films can be easily etched with a fluorine-based gas. Furthermore, since the fluorine-based gas also etches a-Si, the defective pattern of a-Si is also etched at the time of etching of the protective film, so that an additional process such as re-etching is not required. BRIEF DESCRIPTION OF THE FIGURES
第 1 図は本発明の第 1 の実施例の液晶表示装置にかかる単位画素の平 面図である:  FIG. 1 is a plan view of a unit pixel according to the liquid crystal display device of the first embodiment of the present invention:
第 2図は本発明の第 1 の実施例の液晶表示装置にかかる丁 F丁部の断 面図である = Figure 2 is a cross-sectional view of Ding F Ding unit according to the liquid crystal display device of the first embodiment of the present invention =
第 3図は本発明の第 1 の実施例の液晶表示装置にかかる映像信号配線 部の断面図である。  FIG. 3 is a sectional view of a video signal wiring portion according to the liquid crystal display device of the first embodiment of the present invention.
第 4図は本発明の第 1 の実施例の液晶表示装置にかかる付加容量部の 断面図である。  FIG. 4 is a cross-sectional view of the additional capacitance section according to the liquid crystal display device of the first embodiment of the present invention.
第 5図は本発明の第 2の実施例の液晶表示装置にかかる単位画素の平 面図である。 第 6図は本発明の第 2の実施例の液晶表示装置にかかる付加容量部の 断面図である。 FIG. 5 is a plan view of a unit pixel according to a liquid crystal display device of a second embodiment of the present invention. FIG. 6 is a sectional view of an additional capacitance section according to the liquid crystal display device of the second embodiment of the present invention.
第 7図は本発明の第 2の実施例の液晶表示装置にかかる付加容量部の 断面図である。  FIG. 7 is a sectional view of an additional capacitance section according to the liquid crystal display device of the second embodiment of the present invention.
第 8図は本発明の第 3の実施例の液晶表示装置にかかる単位画素の平 面図である。  FIG. 8 is a plan view of a unit pixel of a liquid crystal display device according to a third embodiment of the present invention.
第 9図は本発明の第 4の実施例の液晶表示装置にかかる単位画素の平 面図である。  FIG. 9 is a plan view of a unit pixel of a liquid crystal display device according to a fourth embodiment of the present invention.
第 1 0図は本発明の第 4の実施例の液晶表示装置にかかる走査配線部 の断面図である。  FIG. 10 is a sectional view of a scanning wiring section according to a liquid crystal display device of a fourth embodiment of the present invention.
第 1 1 図は本発明の第 4の実施例の液晶表示装置にかかる付加容量部 の断面図である。  FIG. 11 is a sectional view of an additional capacitance section according to a liquid crystal display device of a fourth embodiment of the present invention.
第 1 2図は本発明の第 5の実施例の液晶表示装置にかかる単位画素の 平面図である。  FIG. 12 is a plan view of a unit pixel of a liquid crystal display device according to a fifth embodiment of the present invention.
第 1 3図は本発明の液晶表示装置の断面図である。  FIG. 13 is a sectional view of the liquid crystal display device of the present invention.
第 1 4図は本発明の液晶表示装置全体の等価回路図である。 発明を実施するための最良の形態  FIG. 14 is an equivalent circuit diagram of the entire liquid crystal display device of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
以下に本発明の実施例を図面を用いて説明する。  Hereinafter, embodiments of the present invention will be described with reference to the drawings.
実施例 1 Example 1
第 1 図は本発明の第 1 の実施例を示す単位画素の平面図である。 ガラ ス基板 1上に A 1 よりなる走査配線 2が形成され、 その表面はアルミナ 膜 3で被覆されている。 前記アルミナ膜 3は前記走査配線 2の形成後に 陽極酸化法によリ自己整合的に形成できる。 アルミナ膜 3上には S i N 膜よりなるゲー 卜絶縁膜 5, 真性非晶質シリ コン ( a — S i ) 膜 6, n 型 a — S i膜, 映像信号配線 7, ソース電極 8よりなる T F Tが形成さ れている。 ガラス基板 1 上には、 インジウム一スズ—酸化膜 ( I T 0 ) よりなる画素電極 4が形成され、 その一端はソース電極 8に接続されて いる。 画素電極 4の他端は表面にアルミナ膜を形成した隣接画素の走査 配線上まで延在され、 付加容量を形成している。 FIG. 1 is a plan view of a unit pixel showing a first embodiment of the present invention. A scanning wiring 2 made of A 1 is formed on a glass substrate 1, and the surface thereof is covered with an alumina film 3. The alumina film 3 can be formed in a self-aligned manner by an anodic oxidation method after the formation of the scanning wiring 2. On the alumina film 3, a gate insulating film 5 made of a SiN film, an intrinsic amorphous silicon (a-Si) film 6, an n-type a-Si film, a video signal wiring 7, and a source electrode 8 Become TFT formed Have been. A pixel electrode 4 made of an indium-tin oxide film (IT 0) is formed on a glass substrate 1, and one end of the pixel electrode 4 is connected to a source electrode 8. The other end of the pixel electrode 4 extends over the scanning wiring of an adjacent pixel having an alumina film formed on the surface to form an additional capacitance.
第 2図及び第 3図は、 第 1 図中の A— A ' 部及び B— B ' 部の断面形 状を示す。 同図に示すように、 映像信号配線上及び丁 F T上には S i よりなる保護膜 9が形成されている。 さらに、 本実施例ではゲ一 卜絶縁 膜 S i N 5 と a— S i膜 6 を略同一の平面形状にした。 略同一の平面形 状にすることにより、 これらの膜を 1 回のホ 卜ノエッチング工程により 加工できるので、 製造工程を短縮できる。  FIG. 2 and FIG. 3 show the cross-sectional shapes of the section AA ′ and the section BB ′ in FIG. As shown in the figure, a protective film 9 made of Si is formed on the video signal wiring and the FT. Further, in this embodiment, the gate insulating film SIN5 and the a-Si film 6 have substantially the same planar shape. By making the plane shapes substantially the same, these films can be processed by one photo-etching step, and the manufacturing process can be shortened.
本実施例の特徴は、 前記保護膜 9が映像信号配線 7間で分離された構 造を有し、 画素電極 4上及び走査配線 2上で前記保護膜 9がー部除去さ れている点である。  The feature of the present embodiment is that the protective film 9 has a structure separated between the video signal wirings 7, and the protective film 9 is removed on the pixel electrode 4 and the scanning wiring 2. It is.
a — S i バターンは T F T部や走査配線と映像信号配線の交差部に配 置されるため、 a — S iノ ターニング時のレジス 卜パターン不良も画素 電極 4上と比較して、 走査配線 2上で多く発生する。 しかし、 保護膜 9 の形状を第 1 図に示す構造とし、 保護膜の加工を S F を用いた ドライ エッチング法を適用することで、 保護膜 9の加工時に走査配線 2上にバ ターン不良で残った a— S i も自動的に除去される。 本実施例では、 保 護膜 9に S i Nを用いたが、 S i 〇 Xでも同様な効果が得られる。 又、 保護膜 9の加工に、 a — S i がエツチングされない方法を用いる場合は、 前記保護膜 9の加工後に再度 a— S i のエツチング処理を施すことで、 隣接する映像信号配線 7間を接続していた a— S i を除去できる。  Since the a-Si pattern is located at the intersection of the TFT section and the scanning wiring and the video signal wiring, the registration pattern defect at the time of the a-Si not- It often occurs on the above. However, by forming the protective film 9 into the structure shown in Fig. 1 and applying a dry etching method using SF to process the protective film, a pattern defect remains on the scanning wiring 2 when the protective film 9 is processed. A—S i is also automatically removed. In the present embodiment, SiN is used for the protective film 9, but the same effect can be obtained even when Si〇X. When a method in which a—S i is not etched is used for processing of the protective film 9, the etching process of a—S i is performed again after the processing of the protective film 9, so that the distance between the adjacent video signal wirings 7 is reduced. The connected a—S i can be removed.
映像信号配線 7材料は、 走査配線上に T F Tのソース 8 ドレイン電 極や付加容量の上部電極と して配置されるため、 映像信号配線のパタ一 ニング不良も上記 a— S i のパターニング不良と同様に走査配線 2上で 多く発生する。 これも第 1 図に示すように、 走査配線 2上の保護膜 9 を 除去しておき、 保護膜 9の加工後に再度映像信号配線 7材料のエツチン グ処理をすることで除去できる。 この時、 端子部で走査配線や映像信号 配線 7が露出していると再度エッチングした時に前記端子部が消失して しまうことがある。 しかし、 画素電極 4 を構成する I T Oで前記端子部 の走査配線或いは映像信号配線 7 を被覆しておく力、、 或いは前記走査配 線或いは映像信号配線 7 を構成する導電膜を保護膜 9の内側に配置し、 前記導電膜と接続した I T Oで端子を構成すれば、 上記問題は解消でき る。 これは、 I T Oが耐薬品性に優れ、 フッ素系ガスを使用した ドライ エツチングにも保護膜に対して十分にエツチンゲの選択比を確保できる ためである。 Since the material of the video signal wiring 7 is arranged on the scanning wiring as the source 8 drain electrode of the TFT and the upper electrode of the additional capacitance, the patterning failure of the video signal wiring is the same as the patterning failure of a-Si described above. Similarly on scan wiring 2 Many occur. As shown in FIG. 1, this can also be removed by removing the protective film 9 on the scanning wiring 2 and etching the material of the video signal wiring 7 again after processing the protective film 9. At this time, if the scanning wiring and the video signal wiring 7 are exposed at the terminal portion, the terminal portion may disappear when the etching is performed again. However, a force of covering the scanning wiring or the video signal wiring 7 of the terminal portion with ITO constituting the pixel electrode 4 or a conductive film constituting the scanning wiring or the video signal wiring 7 is formed inside the protective film 9. The above problem can be solved by disposing the terminal with ITO connected to the conductive film. This is because ITO has excellent chemical resistance and can secure a sufficient etching ratio with respect to the protective film even in dry etching using a fluorine-based gas.
以上に示すように、 本発明の構造を適用することで、 液晶表示装置に おける映像信号配線間の短絡不良及び点欠陥不良を著しく削減でき、 液 晶表示装置の製造歩留ま りを向上できる。  As described above, by applying the structure of the present invention, a short circuit defect and a point defect defect between video signal lines in a liquid crystal display device can be significantly reduced, and the production yield of the liquid crystal display device can be improved. .
本実施例では、 ゲー ト絶縁膜の一部にアルミナ膜 3 を採用した。 アル ミナ膜はフッ素系ガスを用いた ドライエツチングに対して十分な耐性が あり、 アルミナ膜 3上に形成された保護膜 9のみを選択的にエッチング できる。 一般に、 保護膜 9のエッチング残りを発生させないために、 終 点時間よりも長い時間でエッチングする。 このような条件においても、 走査配線 2はアルミナ膜 3で被覆されており、 露出することはない。 本実施例では、 走査配線 2 を A 1 で構成し、 前記 A 1 を陽極酸化して アルミナ膜 3 を形成している。 陽極酸化法を用いることにより、 ピンホ ールなどの欠陥の少ない絶縁耐圧に優れたアルミナ膜が得られる。 又、 走査配線 2材料としては、 前記 A 1 の他に、 A 1 を主成分とする合金や、 前記 A 1或いは A 1 を主成分とする合金で被覆した積層配線により構成 することで、 上記 A 1配線と同様な効果が得られる。 第 4図は付加容量部 (第 1 図中の C— C ' 部) の断面構造を示す。 本 実施例では、 画素電極 4から延在した I T 0を付加容量の上部電極に採 用している。 I T〇は耐薬品性に優れた導電膜であり、 I T〇上の保護 膜として S i N膜 9 をフッ素系ガスを用いたドライエッチングにより選 択的に除去できる。 従って、 保護膜 9の加工時に I T〇パターンがエツ チングされてパターン寸法が変化することがなく、 パネル面内において 付加容量のばらつきを小さくできる。 In the present embodiment, an alumina film 3 was employed as a part of the gate insulating film. The alumina film has a sufficient resistance to dry etching using a fluorine-based gas, and can selectively etch only the protective film 9 formed on the alumina film 3. Generally, the etching is performed for a longer time than the end time in order to prevent the etching residue of the protective film 9 from being generated. Even under such conditions, the scanning wiring 2 is covered with the alumina film 3 and is not exposed. In this embodiment, the scanning wiring 2 is made of A 1, and the A 1 is anodized to form an alumina film 3. By using the anodic oxidation method, an alumina film having few defects such as pinholes and excellent in withstand voltage can be obtained. In addition, as the scanning wiring 2 material, in addition to the above-mentioned A 1, an alloy mainly containing A 1, or a multilayer wiring covered with the above-mentioned A 1 or an alloy mainly containing A 1, is used. The same effect as that of the A1 wiring can be obtained. Fig. 4 shows the cross-sectional structure of the additional capacitance section (C-C 'section in Fig. 1). In this embodiment, IT 0 extending from the pixel electrode 4 is used as the upper electrode of the additional capacitance. IT〇 is a conductive film having excellent chemical resistance, and the SiO 2 film 9 as a protective film on IT〇 can be selectively removed by dry etching using a fluorine-based gas. Therefore, the pattern of the IT〇 pattern is not changed due to the etching of the IT 時 に pattern when the protective film 9 is processed, and the variation of the additional capacitance in the panel surface can be reduced.
本実施例では、 画像表示領域内の保護膜が映像信号配線間で分離して いる構造と した。 さらに液晶表示装置の製造歩留ま りを向上する手段と しては、 端子部における保護膜も映像信号配線間で分離させる: これに より、 端子部で発生する映像信号配線間の短絡不良も救済できる: 実施例 2  In the present embodiment, the structure is such that the protective film in the image display area is separated between the video signal wirings. Further, as a means for improving the production yield of the liquid crystal display device, a protective film at the terminal portion is also separated between the video signal wirings. Can be remedied: Example 2
第 5図は本発明の第 2の実施例を示す単位画素の平面図である: ガラ ス基板 1 上に A 1 よりなる走査配線 2が形成され、 その表面はアルミナ 膜 3で被覆されている。 前記アルミナ膜 3は走査電極 2パターニング後 に陽極酸化法により、 自己整合的に形成できる。 アルミナ膜 3上には S 1 X膜よ りなるゲー 卜絶縁膜 5 , a — S i膜 6 , n型 a— S i 膜, 映 像信号配線 7, ソース電極 8よりなる T F Tが形成されている。 ガラス 基板 1 上には、 ィンジゥムースズ一酸化膜 ( I 丁〇) よりなる画素電極 4が形成され、 その一端はソース電極 8に接続されている。 画素電極 4 の他端は付加容量用上部電極 2 0に接続され、 表面にアルミナ膜 3 を形 成した隣接画素の走査配線 2 との間で付加容量を形成している。 付加容 量用上部電極 2 0は C rより構成されている。 さらに、 映像信号配線 7 上及び T F T上には S i Nよりなる保護膜 9が形成されている。 本実施 例では、 上記第 1 の実施例と同様に、 ゲー ト絶縁膜である S i ヽ'膜 5 と a - S i膜 6は略同一の平面形状とし、 製造工程を簡略化している。 第 6図は付加容量を構成する第 5図中の D— D ' 部の断面形状を示す。 付加容量はガラス基板 1側から A 1の走査配線 2, アルミナ膜 3, C r よりなる付加容量用上部電極 2 0の順で構成されている。 FIG. 5 is a plan view of a unit pixel showing a second embodiment of the present invention: A scanning wiring 2 made of A 1 is formed on a glass substrate 1, and the surface thereof is covered with an alumina film 3. . The alumina film 3 can be formed in a self-aligned manner by anodizing after patterning the scanning electrode 2. On the alumina film 3, a TFT composed of a gate insulating film 5 made of an S 1 X film, an a-Si film 6, an n-type a-Si film, a video signal wiring 7, and a source electrode 8 is formed. I have. On the glass substrate 1, a pixel electrode 4 made of an indium tin oxide film (I-cho) is formed, and one end thereof is connected to a source electrode 8. The other end of the pixel electrode 4 is connected to an upper electrode 20 for additional capacitance, and forms an additional capacitance with the scanning wiring 2 of an adjacent pixel having an alumina film 3 formed on the surface. The upper electrode 20 for additional capacity is composed of Cr. Further, a protective film 9 made of SiN is formed on the video signal wiring 7 and the TFT. In this embodiment, as in the first embodiment, the gate insulating film S i ヽ ′ film 5 and the a-S i film 6 have substantially the same planar shape, thereby simplifying the manufacturing process. FIG. 6 shows a cross-sectional shape of a portion D-D 'in FIG. The additional capacitance is formed from the glass substrate 1 side in the order of the scanning wiring 2 of A1, the alumina film 3, and the upper electrode 20 for additional capacitance composed of Cr.
本実施例の特徴は、 第 1 の実施例で示した前記保護膜 9が映像信号配 線 7間で分離している点に加えて、 付加容量用上部電極 2 0 を C rによ り構成した点である。  The feature of this embodiment is that, in addition to the point that the protective film 9 is separated between the video signal lines 7 shown in the first embodiment, the additional electrode 20 for additional capacitance is composed of Cr. That is the point.
C rは、 フッ素系ガスを用いた ドライエッチングではエッチング速度 が非常に小さいため、 保護膜 9の加工時に付加容量用上部電極 2 0のパ ターンが消失或いは縮小化することがなく、 基板内でばらつきの少ない 付加容量を形成できる。  Cr has a very low etching rate in dry etching using a fluorine-based gas, so that the pattern of the upper electrode 20 for the additional capacitance does not disappear or shrink during processing of the protective film 9, and is formed within the substrate. An additional capacitance with less variation can be formed.
本実施例では、 付加容量の上部電極 2 0として C r を用いたが、 C r 或いは A 1 を主成分とする導電膜ならば、 同様な効果が得られる。  In this embodiment, Cr is used as the upper electrode 20 of the additional capacitor. However, a similar effect can be obtained with a conductive film containing Cr or A 1 as a main component.
さらに、 付加容量用上部電極 2 0として前記 C r或いは A 1 を主成分 とする導電膜を上層に配置した積層膜を用いても同様な効果が得られる。 第 Ί図はその具体的な一例を示す。 付加容量の下部電極として A 1 の走 査配線 2 , 絶縁膜は前記 A 1の陽極酸化膜であるアルミナ膜 3で構成し、 上部電極はアルミナ膜側から T i よリなる付加容量用上部電極の下層電 極 2 0 ' 、 A 1 よりなる付加容量用上部電極 2 0〃 で構成している。 保 護膜 9の加工時にエッチングガスに曝されるのは、 前記積層配線の表面 である。 その表面層を A 〗 で構成しているため、 前記保護膜 9の加工時 に付加容量の上部電極 2 0 ' , 2 0 " が消失することはない。  Further, a similar effect can be obtained by using a laminated film in which the conductive film containing Cr or A 1 as a main component is disposed as an upper layer as the upper electrode 20 for the additional capacitance. FIG. 6 shows a specific example. The scan electrode 2 of A 1 is used as a lower electrode of the additional capacitor 2, the insulating film is composed of the alumina film 3 which is the anodic oxide film of the above A 1, and the upper electrode is an upper electrode for additional capacitor consisting of Ti from the alumina film side. The lower electrode 20 ′ and the upper electrode for additional capacitance 20 ′ composed of A 1. It is the surface of the laminated wiring that is exposed to the etching gas when processing the protective film 9. Since the surface layer is made of A〗, the upper electrodes 20 ′ and 20 ″ of the additional capacitance do not disappear when the protective film 9 is processed.
実施例 3 Example 3
第 8図は本発明の第 3の実施例を示す単位画素の平面図である。 ガラ ス基板 1上に C rよりなる走査配線 2 ' が形成され、 その上部には S i N 膜よりなるゲー 卜絶縁膜 5, a — S i膜 6 , n型 a — S i膜, 映像信号 配線 7, ソース電極 8よりなる T F Tが形成されている。 ガラス基板 1 上には、 インジウム一スズ—酸化膜 ( I T O ) よりなる画素電極 4が形 成され、 その一端はソース電極 8に接続されている。 画素電極 4の他端 は付加容量の上部電極 2 0に接続され、 隣接画素の走査配線 2 との間で 付加容量を形成している。 同図に示すように、 映像 ί言号配線 7上及び T F Τ上には S i Νよりなる保護膜 9が形成され、 前記保護膜 9は映像 信号配線 7間で分離している構造である。 FIG. 8 is a plan view of a unit pixel showing a third embodiment of the present invention. A scan wiring 2 'made of Cr is formed on a glass substrate 1, and a gate insulating film 5, a-Si film 6, an n-type a-Si film, an n-type a-Si film, A TFT composed of the signal wiring 7 and the source electrode 8 is formed. Glass substrate 1 A pixel electrode 4 made of an indium-tin oxide film (ITO) is formed on the upper side, and one end thereof is connected to a source electrode 8. The other end of the pixel electrode 4 is connected to the upper electrode 20 of the additional capacitance, and forms an additional capacitance with the scanning wiring 2 of the adjacent pixel. As shown in the figure, a protective film 9 made of Si is formed on the video signal wiring 7 and the TF 、, and the protective film 9 is separated from the video signal wiring 7. .
本実施例は、 ゲー 卜絶縁膜 5 を保護膜 9 と同一材料である S 1 Xで構 成している点が特徴である。  The present embodiment is characterized in that the gate insulating film 5 is made of S 1 X which is the same material as the protective film 9.
本実施例の構造は、 以下の手順によ り製造する。 ガラス基板 1 上に C r を成膜し、 走査配線 2 ' パターンを形成する。 続いて、 フロズマ C V D法で S i X膜 5 , a— S i膜 6 , n型 a— S i を連続成膜し、 T F T部及び走査配線 2 ' と映像信号配線 7の交差部の a — S i膜 6 , n型 a— S i膜を島状加工する。 その後、 画素電極 4上の S i Xを第 8 図中 ( a ) の点線で示したパターンに ドライエッチングして開口する。 そして、 映像信号配線 7材料を成膜し、 映像信号配線 7パター ン に加工 する。 最後に、 保護膜 9 として S i Xを成膜し、 第 8図中( b )の点線で 示したパターンに加工する。 この時、 第 8図中の A部と B部の S i Nの 膜厚を比較すると B部の方がゲー ト絶縁膜の膜厚だけ厚い- 従って、 保 護膜 9のエツチング時間を、 A部の S i .\のエツチング終点時間から B 部の S i Nのエッチング終点時間の範囲に設定することで、 画素電極 4 上の S i Nは除去され、 走査配線 2 ' は S i Xで被覆されることになる c 上記製造方法により、 ゲー 卜絶縁膜 5 を保護膜 9 と同一材料で構成した 場合においても、 本発明に示す保護膜 9の平面形状を何ら問題なく製造 できる。  The structure of this embodiment is manufactured according to the following procedure. A film of Cr is formed on a glass substrate 1 to form a scanning wiring 2 'pattern. Subsequently, a SiO x film 5, an a-Si film 6, and an n-type a-Si are continuously formed by the Frosma CVD method, and the TFT portion and the a at the intersection of the scanning wiring 2 ′ and the video signal wiring 7 are formed. Si film 6, n-type a—Island Si film. Thereafter, Six on the pixel electrode 4 is dry-etched into a pattern shown by a dotted line in FIG. Then, a film of the video signal wiring 7 material is formed and processed into the video signal wiring 7 pattern. Finally, S IX is formed as a protective film 9 and processed into a pattern shown by a dotted line in (b) of FIG. At this time, comparing the film thicknesses of the SiN in the portions A and B in FIG. 8, the portion B is thicker by the thickness of the gate insulating film. Accordingly, the etching time of the protective film 9 is By setting the time between the etching end time of the portion S i. \ To the etching end time of the portion S i N, the S i N on the pixel electrode 4 is removed, and the scanning wiring 2 ′ is C) Even when the gate insulating film 5 is made of the same material as the protective film 9, the planar shape of the protective film 9 according to the present invention can be manufactured without any problem by the above manufacturing method.
本実施例の構造は、 第 1 の実施例と同様に、 走査配線 2 ' 上に残る a 一 S i の不良パターン及び映像信号配線 7の不良パターンを除去でき、 映像信号配線 7間の短絡不良並びに点欠陥不良を救済できる: 実施例 4 As in the first embodiment, the structure of this embodiment can remove the defective pattern of a-Si and the defective pattern of the video signal wiring 7 remaining on the scanning wiring 2 ′. Short circuit failure between video signal wiring 7 and point defect failure can be remedied: Embodiment 4
第 9図は本発明の第 4の実施例を示す単位画素の平面図である。 ガラ ス基板 1 上に T aよりなる走査電極 2〃 が形成され、 その表面には走査 電極 2〃 側から T a 0 X膜 5 ' , S i X膜 5よりなるゲー ト絶縁膜, a 一 S i膜 6 , n型 a — S i膜, 映像信号配線 7 , ソース電極 8よりなる T F Tが形成されている。 ガラス基板 1 上には、 インジウム一スズー酸 化膜 ( I T O ) よりなる画素電極 4が形成され、 その一端はソース 極 8に接続されている。 画素電極 4の他端は付加容量用上部電極 2 0をな す C rに接続され、 隣接画素の走査電極 2〃 との間に付加容量を形成し ている。 映像信号配線 7上及び T F T上には S i Nよ りなる保護膜 9 お 形成されており、 前記保護膜 9は映像信号配線 7間で分離されている。 本実施例の特徴は、 画素電極上 4及び走査配線 2〃 上の保護膜 9 を一 部除去した構造であり、 前記保護膜 9が映像信号配線 7間で分離してい る点、 並びにゲー ト絶縁膜が S i N膜 5 Z T a O x膜 5 ' の積層膜で構 成されている点である。  FIG. 9 is a plan view of a unit pixel showing a fourth embodiment of the present invention. On a glass substrate 1, a scanning electrode 2〃 made of Ta is formed, and on its surface, a gate insulating film consisting of a Ta 0 X film 5 ′ and a Si X film 5 is formed from the scanning electrode 2〃 side. A TFT comprising an Si film 6, an n-type a-Si film, a video signal wiring 7, and a source electrode 8 is formed. A pixel electrode 4 made of an indium monotin oxide film (ITO) is formed on a glass substrate 1, and one end of the pixel electrode 4 is connected to a source electrode 8. The other end of the pixel electrode 4 is connected to Cr, which is the upper electrode 20 for the additional capacitance, and forms an additional capacitance between itself and the scanning electrode 2 of the adjacent pixel. A protection film 9 made of SiN is formed on the video signal wiring 7 and the TFT, and the protection film 9 is separated between the video signal wirings 7. The feature of the present embodiment is a structure in which the protective film 9 on the pixel electrode 4 and the scanning wiring 2 is partially removed, and the protective film 9 is separated between the video signal wirings 7 and the gate. The point is that the insulating film is composed of a laminated film of the SiN film 5ZTaOx film 5 '.
保護膜 9が映像信号配線 7間で分離しているため、 第 1 の実施例と同 様に a — S i 及び映像信号配線のバタ一ニング不良に伴う短絡不良や点 欠陥を低減できる。  Since the protective film 9 is separated between the video signal wirings 7, short-circuit defects and point defects due to a-Si and poor patterning of the video signal wiring can be reduced as in the first embodiment.
第 1 0図は、 第 9図中の E— E ' 部の断面形状を示す。 3 1 '膜 5 T a O x膜 5 ' は保護膜 9の形成前には少なく とも走査配線 2〃 を被覆 するように形成しておく。 そして、 保護膜である S i N膜 9が除去され る部分に位置するゲー ト絶縁膜である S i N膜 5は、 保護膜である SiM 膜 9のエッチング時に除去される。 しかし、 走査配線 2〃 上はゲー ト絶 縁膜を構成するもう 1つの絶縁膜である T a 〇 X膜 5 ' で被覆され、 露 出することはない。 第 1 1 図は付加容量部の断面形状を示す (第 1 0図中の F— F ' 部)。 上記に示すように、 保護膜である S i N膜 9 を除去する部分のゲー 卜絶 緣膜である S i N膜 5は除去される力 付加容量用上部電極 2 0の下層 も前記上部電極 2 0がマスクとなり、 ゲー ト絶縁膜である S i X膜 5が 残る。 本実施例では、 付加容量の絶縁膜は S i X膜 5 Z T a 0 X膜 5 ' の積層膜で構成される。 FIG. 10 shows a cross-sectional shape of a portion EE ′ in FIG. The 3 1 ′ film 5 T a O x film 5 ′ is formed so as to cover at least the scanning wiring 2 before forming the protective film 9. Then, the SiN film 5 as the gate insulating film located at a portion where the SiN film 9 as the protective film is removed is removed when the SiM film 9 as the protective film is etched. However, the scanning wiring 2 ′ is covered with the Ta〇X film 5 ′, which is another insulating film constituting the gate insulating film, and is not exposed. FIG. 11 shows a cross-sectional shape of the additional capacitance section (section FF ′ in FIG. 10). As described above, the gate insulating film at the portion where the protective SiN film 9 is to be removed, the SiN film 5 which is the film to be removed is a force to be removed. 20 serves as a mask, and the SiOx film 5 as a gate insulating film remains. In this embodiment, the insulating film of the additional capacitance is formed by a laminated film of the Six film 5ZTa0x film 5 '.
第 1 0図及び第 1 1 図に示したように、 本構造ではゲー ト絶縁膜であ る S i X膜 5は保護膜の下層及び付加容量の上部電極の下層のみに残る 構造となる。  As shown in FIGS. 10 and 11, the present structure has a structure in which the SIX film 5 as the gate insulating film remains only under the protective film and under the upper electrode of the additional capacitor.
本実施例のゲー 卜絶縁膜の構造の他にも、 複数の異なる材料からなる 積層膜で構成すれば同様な効果が得られる。 これは、 ゲー ト絶縁膜の少 なく とも 1 層は保護膜と異なる材料で構成されるため、 保護膜を選択的 にエツチングでき、 走査配線を露出することはない。  In addition to the structure of the gate insulating film of the present embodiment, similar effects can be obtained by forming a laminated film composed of a plurality of different materials. This is because at least one layer of the gate insulating film is made of a material different from that of the protective film, so that the protective film can be selectively etched and the scanning wiring is not exposed.
実施例 5 Example 5
第 I 2 [2は本発明の第 5の実施例を示す単位画素の平面図である ガ ラス基板 : 上に A 1 よりなる走査配線 2が形成され、 その表面はアルミ ナ膜 3で被覆されている。 前記アルミナ膜 3は走査配線 2パターニン グ 後に陽極酸化法により、 自己整合的に形成できる。 アルミナ膜 3上には S i —\'膜よりなるゲー ト絶縁膜 5, a — S i膜 5, n型 a — S i膜, 映 像信号配線 7, ソース電極 8よりなる T F Tが形成されている。 ガラス 基板 1 上には、 ィンジゥムースズ—酸化膜 ( I T〇) よりなる画素電極 4が形成され、 その一端はソース電極 8に接続されている。 画素電極 4 の他端は表面にアルミナ膜 3 を形成した隣接画素の走査配線 2上まで延 在され、 付加容量を形成している。 映像信号配線 7上及び T F T上には S i Xよりなる保護膜 9が形成され、 前記保護膜 9は映像信号配線 7間 で分離している。 1 δ 本実施例は、 第 1 2図中の C部に示すように、 映像信号配線 7 と平行 である画素電極 4の端部のうち少なく とも一部が、 前記保護膜 9の開口 部に位置することが特徴である。 I 2 [2 is a plan view of a unit pixel showing a fifth embodiment of the present invention. Glass substrate: A scanning wiring 2 made of A 1 is formed thereon, and the surface thereof is covered with an alumina film 3. ing. The alumina film 3 can be formed in a self-aligned manner by anodizing after the patterning of the scanning wiring 2. On the alumina film 3, a TFT composed of a gate insulating film 5, composed of a Si— \ 'film, a—Si film 5, an n-type a—Si film, a video signal wiring 7, and a source electrode 8 is formed. ing. On the glass substrate 1, a pixel electrode 4 made of an indium tin oxide film (IT〇) is formed, and one end thereof is connected to a source electrode 8. The other end of the pixel electrode 4 extends to above the scanning wiring 2 of an adjacent pixel having the alumina film 3 formed on the surface, and forms an additional capacitance. A protection film 9 made of SIX is formed on the video signal wiring 7 and the TFT, and the protection film 9 is separated between the video signal wirings 7. 1 δ In the present embodiment, at least a part of the end of the pixel electrode 4 parallel to the video signal wiring 7 is located at the opening of the protective film 9 as shown in the part C in FIG. It is characterized by being located.
本実施例は、 第 1の実施例に示した効果の他に以下に示す効果がある。 点欠陥の発生原因の 1 つに、 画素電極 4上に映像信号配線材料や映像 信号配線 7 と接続された a— S i がパターン不良により残るものがある。 本実施例の構造により、 保護膜である S i X膜 9の加工時に映像信号配 線 7 と画素電極 4 を接続していた a— S i の不良パタ一ンは除去でき、 さらに保護膜 9加工後に再度映像信号配線材料のエッチングをすること で、 画素電極 4 と接続していた映像信号配線 7の不良パタ一ンを除去で きる。 これは、 保護膜 9の開口部に位置する画素電極 4の端部の長さを 大きくするほど効果が大きくなる。  This embodiment has the following effects in addition to the effects shown in the first embodiment. One of the causes of the point defect is that a-Si connected to the video signal wiring material or the video signal wiring 7 on the pixel electrode 4 remains due to a pattern defect. According to the structure of this embodiment, the defective pattern of a—S i that connects the video signal line 7 and the pixel electrode 4 during the processing of the S i X film 9 serving as the protection film can be removed. By etching the video signal wiring material again after the processing, the defective pattern of the video signal wiring 7 connected to the pixel electrode 4 can be removed. This effect increases as the length of the edge of the pixel electrode 4 located at the opening of the protective film 9 increases.
実施例 6  Example 6
以下に、 本発明の液晶表示装置の実施例を示す。  Hereinafter, examples of the liquid crystal display device of the present invention will be described.
第 1 3図は本実施例の構造を示す液晶表示装置の断面模式図である。 液晶層 2 0 0 を基準に下部のガラス基板 1 上には、 走査配線 2 と映像信 号配線 7 とがマ 卜 リクス状に形成され、 その交点近傍に形成された TFT を介して I T Oよりなる画素電極 4 を駆動する。 液晶層 2 0 0を挟んで 対向する対向ガラス基板 1 0 0上には I T〇よりなる対向電極 1 0 4及 びカラーフィルタ 1 0 2 , カラーフィルタ保護膜 1 0 3 , 遮光用ブラッ クマ 卜リクスパターンを形成する遮光膜 1 0 1 が形成されている。 第  FIG. 13 is a schematic sectional view of a liquid crystal display device showing the structure of this embodiment. On the lower glass substrate 1 with reference to the liquid crystal layer 200, the scanning wiring 2 and the video signal wiring 7 are formed in a matrix, and are made of ITO via the TFT formed near the intersection. Drive pixel electrode 4. On the opposing glass substrate 100 opposing across the liquid crystal layer 200, the opposing electrode 104 made of IT〇 and the color filter 102, the color filter protective film 103, the black matrix for shading A light-shielding film 101 for forming a pattern is formed. No.
1 3図の中央部は 1 画素部分の断面を、 左側は一対のガラス基板の左側 縁部分で外部引出端子の存在する部分の断面を、 右側は一対のガラス基 板の右側縁部分で外部引出端子の存在しない部分の断面を示している。 第 1 3図の左側, 右側のそれぞれに示すシール材 S Lは液晶層 2 ◦ 0を 封止するように構成されており、 液晶封入口 (図示していない) を除く ガラス基板 1, 1 0 0 の縁全体に沿って形成されている。 シール材は例 えばエポキシ樹脂で形成されている。 対向ガラス基板 1 0 0側の対向電 極 1 0 4は少なく とも一箇所において、 銀ペース 卜材 S I Lによってガ ラス基板 1 に形成された外部引出配線に接続されている。 この外部引出 配線は走査配線 2, ソース電極 8, 映像信号配線 7のそれぞれと同一製 造工程で形成される。 配向膜 0 R I 1 , 0 R I 2, 画素電極 4, 保護膜 9 , カラーフィルタ保護膜 1 0 3 , ゲー 卜絶縁膜である S i N膜 5のそ れぞれの層はシール材 S Lの内側に形成される... 偏光板 1 0 5, 105' はそれぞれ一対のガラス基板 1 , 1 0 0 の外側の表面に形成されている。 液晶層 2 0 0の液晶分子の向きを設定する下部配向膜◦ R i 1 と上部 配向膜〇 R I 2の間に封入され、 シール材 S Lによってシールされてい る。 下部配向膜〇 R I 1 はガラス基板 1 側の保護膜 9或いは画素電極 4 の上部に形成される。 対向ガラス基板 1 0 0の内側の表面には、 遮光膜 1 0 1 , カラ一フィルタ 1 0 2 , カラ一フ ィ ルタ保護膜 1 0 3 , 対向電 極 1 0 4及び上部配向膜〇 1¾ 1 2が順次積層して設けられている = この 液晶表示装置はガラス基板 1側と対向ガラス基板 1 ) ϋ側の層を別々に 形成し、 その後上下ガラス基板 1 , 1 0 0 を重ね合わせ、 両者間に液晶 2 0 0 を封入することによって組み立てられる。 バックライ 卜 B Lから の光の透過を画素電極 4部分で調節することにより丁 F Τ駆動型のカラ 一液晶表示装置が構成される。 13 The central part in Fig. 13 is a cross section of one pixel part, the left part is a cross section of the part where the external lead-out terminal is present at the left edge part of a pair of glass substrates, and the right part is a external part at the right side part of a pair of glass substrates. The cross section of a portion where no terminal is present is shown. The sealing material SL shown on the left and right sides of FIG. 13 is configured to seal the liquid crystal layer 2 ◦ 0, excluding the liquid crystal filling port (not shown) It is formed along the entire edge of the glass substrate 1, 100. The sealing material is made of, for example, epoxy resin. The counter electrode 104 on the side of the counter glass substrate 100 is connected at least at one position to an external lead wire formed on the glass substrate 1 by a silver paste material SIL. This external lead-out wiring is formed in the same manufacturing process as each of the scanning wiring 2, the source electrode 8, and the video signal wiring 7. Each layer of alignment film 0 RI 1, 0 RI 2, pixel electrode 4, protective film 9, color filter protective film 103, and gate insulating film SIN film 5 are inside the sealing material SL. The polarizing plates 105, 105 'are formed on the outer surfaces of a pair of glass substrates 1, 100, respectively. The liquid crystal layer 200 is sealed between a lower alignment film R i1 for setting the direction of liquid crystal molecules of the liquid crystal layer 200 and the upper alignment film 〇RI2, and is sealed with a sealing material SL. The lower alignment film RI 1 is formed on the protective film 9 on the glass substrate 1 side or on the pixel electrode 4. On the inner surface of the opposite glass substrate 100, a light-shielding film 101, a color filter 102, a color filter protective film 103, a counter electrode 104 and an upper alignment film 〇1¾1 2 are sequentially laminated to provided = the liquid crystal display device to form a layer of the glass substrate 1 side and the opposing glass substrate 1) Y side separately and then superimposing the upper and lower glass substrates 1, 1 0 0, both It is assembled by enclosing liquid crystal 200 in between. By controlling the transmission of light from the backlight BL at the pixel electrodes 4, a D-drive type liquid crystal display device is constructed.
本実施例では、 第 1 図に示す T F Τ基板を採用した = 前記 T F T基板 は以下の構造を有する。 ガラス基板 1 上に A 1 よりなる走査配線 2が形 成され、 その表面はアルミナ膜 3で被覆されている。 前記アルミナ膜 3 は走査配線 2パターニング後に陽極酸化法により、 自己整合的に形成で きる。 アルミナ膜 3上には S i N膜よりなるゲー 卜絶縁膜 δ、 a - S i 膜 6, n型 a — S i膜, 映像信号配線 7, ソース電極 8よりなる T F T が形成されている。 ガラス基板 1 上には、 インジウム—スズ一酸化膜In this embodiment, = the TFT substrate employing the TF T substrate illustrated in FIG. 1 has the following structure. A scanning wiring 2 made of A 1 is formed on a glass substrate 1, and the surface thereof is covered with an alumina film 3. The alumina film 3 can be formed in a self-aligned manner by anodic oxidation after patterning the scanning wiring 2. On the alumina film 3, a gate insulating film δ consisting of a SiN film, a-Si film 6, an n-type a-Si film, a video signal wiring 7, and a TFT consisting of a source electrode 8 Is formed. Indium-tin monoxide film on glass substrate 1
( I T 0 ) よりなる画素電極 4が形成され、 その一端はソース電極 8に 接続されている。 画素電極 4の他端は表面にアルミナ膜を形成した隣接 画素の走査配線 2上まで延在され、 付加容量を形成している: 映像信号 配線 7上及び T F T上には S i よりなる保護膜 9が形成され、 画像表 示領域内において映像信号配線 7間で分離している, 上記構造の T F丁 基板の他に、 第 5図, 第 8図, 第 9図, 第 1 1 図などの構造を採用して も良い- 第 1 4図は表示装置全体の等価回路を示す X: G は緑色フィルタ G が形成される画素に接続された映像信号配線である: 同様に、 X : B は 青色フィルタ B力;、 X ; R は赤色フィルタ Rが形成される画素に接続さ れた映像信号配線である。 Υ , Υ 2 , …は各画素列を選択する走査配線 であり、 これらの走査配線は垂直走査回路 Vに接続されている 映像信 号配線は映像信号起動回路 Ηに接続されている。 Sじ Ρは 1 つの電圧源 から複数の分圧した安定化された電圧源を得るための電源回路やホス ト (上位演算処理装置) からの陰極線管用の情報を液晶パネル用の情報に 変換する回路を含む回路である。 A pixel electrode 4 made of (IT 0) is formed, and one end of the pixel electrode 4 is connected to the source electrode 8. The other end of the pixel electrode 4 extends to the scanning wiring 2 of an adjacent pixel having an alumina film formed on the surface to form an additional capacitance: a protective film made of Si on the video signal wiring 7 and the TFT. 9 are formed and are separated between the video signal wirings 7 in the image display area. In addition to the TF board having the above structure, the TF-cables shown in FIG. 5, FIG. 8, FIG. 9, FIG. Fig. 14 shows the equivalent circuit of the whole display device. X: G is the video signal wiring connected to the pixel on which the green filter G is formed. Similarly, X: B is X ; R are the video signal lines connected to the pixels where the red filter R is formed.走 査, Υ 2 ,... Are scanning wirings for selecting each pixel column. These scanning wirings are connected to the vertical scanning circuit V. The video signal wiring is connected to the video signal activation circuit Η. S-J converts the information for the cathode ray tube from the power supply circuit and the host (upper processing unit) to obtain multiple divided and stabilized voltage sources from one voltage source to the information for the liquid crystal panel. It is a circuit including a circuit.
以上のように構成した液晶表示装置は、 映像信号配線間の短絡不良及 び点欠陥不良を著しく削減でき、 高歩留ま リで液晶表示装置を製造でき る。  The liquid crystal display device configured as described above can significantly reduce short circuit defects and point defect defects between video signal wirings, and can manufacture liquid crystal display devices with high yield.
以上述べたように、 本発明によれば、 a— S i 膜や映像信号配線のパ タ一二ング不良に起因して発生する映像信号配線間の短絡不良及び点欠 陥不良を著しく削減できるので、 高歩留ま りで液晶表示装置を製造でき る。 産業上の利用可能性 以上のように、 本発明にかかる液晶表示装置は映像信号配線間の短絡 不良ならびに点欠陥不良を削減し、 製造の歩留ま り向上に有用である。 As described above, according to the present invention, short-circuit defects and point defect defects between video signal wirings caused by patterning defects of a-Si films and video signal wirings can be significantly reduced. Therefore, a liquid crystal display device can be manufactured with a high yield. Industrial applicability As described above, the liquid crystal display device according to the present invention reduces short circuit defects and point defect defects between video signal lines, and is useful for improving the production yield.

Claims

1 . 複数の走査配線と、 それらにマ ト リクス状に交差する複数の映像信 号配線と、 これらの配線のそれぞれの交点に対応して形成された複数の 薄膜トランジスタと、 これらの複数の薄膜トランジスタのそれぞれに接 続された複数の画素電極とを有するアクティブマ 卜 リクス基板と、 上記ァクティブマ 卜リクス基板に対向して設けられ、 上記それぞれの 画素電極に対向する対向電極を有する対向基板と、 1. A plurality of scanning wirings, a plurality of video signal wirings intersecting them in a matrix, a plurality of thin film transistors formed corresponding to intersections of these wirings, and a plurality of An active matrix substrate having a plurality of pixel electrodes connected thereto, and a counter substrate provided to face the active matrix substrate and having a counter electrode facing each of the pixel electrodes;
上記アクティブマ ト リ クス基板及び対向基板間に封入された液晶層と を有し、  A liquid crystal layer sealed between the active matrix substrate and the opposing substrate,
上記アクティブマ 卜 リクス基板には、 隣接する上記信号配線間の上記 走査配線領域上で分離された、 上記複数の映像信号配線及び複数の薄膜 トランジスタ とを保護する保護膜が形成されていることを特徴とする液 晶表示装置。  On the active matrix substrate, a protective film for protecting the plurality of video signal lines and the plurality of thin film transistors separated on the scanning wiring region between the adjacent signal lines is formed. Characteristic liquid crystal display device.
2 . 請求項 1 において、 上記複数の画素電極のそれぞれは上記走査配線 と上記映像配線とに囲まれた領域内に形成され、 上記保護膜はこれらの 画素電極上で分離されていることを特徴とする液晶表示装置。  2. The method according to claim 1, wherein each of the plurality of pixel electrodes is formed in a region surrounded by the scanning wiring and the video wiring, and the protective film is separated on the pixel electrodes. Liquid crystal display device.
3 . 請求項 1 又は 2において、 上記走査配線は絶緣膜で被覆されている ことを特徴とする液晶表示装置。  3. The liquid crystal display device according to claim 1, wherein the scanning wiring is covered with an insulating film.
4 . 請求項 3において、 上記絶縁膜は上記保護膜が分離される上記信号 配線間の上記走査配線領域上で上記液晶層に露出していることを特徴と する液晶表示装置。  4. The liquid crystal display device according to claim 3, wherein the insulating film is exposed to the liquid crystal layer on the scanning wiring region between the signal wirings from which the protective film is separated.
5 . 請求項 4において、 上記走査配線は A 1 を主成分とする金属で構成 され、 上記絶縁膜はアルミナで構成されていることを特徴とする液晶表 示装置。  5. The liquid crystal display device according to claim 4, wherein the scanning wiring is made of a metal containing A 1 as a main component, and the insulating film is made of alumina.
6 . 請求項 5において、 上記走査配線は A 1 、 及び、 A 1 を主成分とす る合金の積層構造になっていることを特徴とする液晶表示装置。 6. The liquid crystal display device according to claim 5, wherein the scanning wiring has a laminated structure of A 1 and an alloy having A 1 as a main component.
7 . 請求項 4において、 上記走査配線は T aを主成分とする金属で構成 され、 上記絶縁膜は T a O xで構成されていることを特徴とする液晶表 示装置。 7. The liquid crystal display device according to claim 4, wherein the scanning wiring is made of metal containing Ta as a main component, and the insulating film is made of TaOx.
8 . 請求項 1 において、 上記走査配線は上記薄膜トランジスタのゲ一 卜 電極を構成し、 このゲー 卜電極上には積層されたゲー 卜絶縁膜が形成さ れていることを特徴とする液晶表示装置。  8. The liquid crystal display device according to claim 1, wherein the scanning wiring forms a gate electrode of the thin film transistor, and a stacked gate insulating film is formed on the gate electrode. .
9 . 請求項 8において、 上記ゲー 卜絶縁膜はアルミナ膜、 及び、 S i 膜を含むことを特徴とする液晶表示装置。  9. The liquid crystal display device according to claim 8, wherein the gate insulating film includes an alumina film and a Si film.
1 0 . 請求項 8において、 上記ゲー ト絶縁膜は丁 a 〇 X膜、 及び、  10. The claim 8, wherein the gate insulating film is a 〇 X film, and
S i X膜を含むことを特徴とする液晶表示装置。  A liquid crystal display device comprising a SiX film.
1 1 . 請求項 3において、 上記画素電極の一端は保護膜が分離された上 記走査配線領域上に延在され、 この延在された部分と、 この部分の下に 形成された走査配線と、 及び、 この走査配線に被覆された絶縁層とによ り付加容量が形成されることを特徴とする液晶表示装置- 11. The claim 3, wherein one end of the pixel electrode extends over the scanning wiring region where the protective film is separated, and the extended portion and the scanning wiring formed below the portion are connected to each other. A liquid crystal display device characterized in that an additional capacitance is formed by an insulating layer covered by the scanning wiring.
1 2 . 請求項 3において、 上記画素電極の一端に接続され、 保護膜が分 離された上記走査配線領域上に形成された付加容量用上部電極を有し、 この付加容量用上部電極、 この部分の下に形成された走査配線と、 及び、 この走査配線に被覆された絶縁層とにより付加容量が形成されることを 特徴とする液晶表示装置。 12. The additional capacitance upper electrode according to claim 3, further comprising an additional capacitance upper electrode connected to one end of the pixel electrode and formed on the scanning wiring region in which a protective film is separated. A liquid crystal display device, wherein an additional capacitance is formed by a scanning wiring formed below the portion and an insulating layer covered by the scanning wiring.
1 3 . 請求項 1 2において、 上記付加容量用上部電極は C rで構成され ていることを特徴とする液晶表示装置。  13. The liquid crystal display device according to claim 12, wherein the additional electrode for an additional capacitor is composed of Cr.
1 4 . 請求項 1 2において、 上記付加容量用上部電極は積層されている ことを特徴とする液晶表示装置。  14. The liquid crystal display device according to claim 12, wherein the upper electrode for additional capacitance is stacked.
1 5 . 請求項 1 4において、 上記積層される付加容量用上部電極は C r、 及び、 A 1 を含むことを特徴とする液晶表示装置。  15. The liquid crystal display device according to claim 14, wherein the laminated upper electrode for additional capacitance contains Cr and A 1.
PCT/JP1995/000590 1995-03-29 1995-03-29 Liquid crystal display WO1996030801A1 (en)

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