WO1996028848A1

WO1996028848A1 - Low-emi device circuit and its structure

Info

Publication number: WO1996028848A1
Application number: PCT/JP1995/000431
Authority: WO
Inventors: Yutaka Akiba; Kazuhiko Horikoshi; Toshiyuki Arai
Original assignee: Hitachi, Ltd.
Priority date: 1995-03-15
Filing date: 1995-03-15
Publication date: 1996-09-19
Also published as: JP3909086B2

Abstract

A low-EMI device in which components are mounted at a high density and unnecessary radiation is effectively suppressed by converting the potential fluctuation at the power supply pad with respect to ghe ground pad which occurs on switching an LSI element, etc., into Joule's heat without using any parts used as the measure against EMI. An element is formed on the surface of the LSI device by using a thin film processing. To a first by-pass capacitor (C1) connected to the power supply and ground pads, parallely connected is a circuit in which a second by-pass capacitor (C2) and a resistor (R) are connected in series. Consequently the impedance of the capacitor (C2) is sufficiently smaller than that of the resistor (R). The dc component of the Q-factor of the by-pass capacitor circuit is cut when viewed from between the power supply and ground pads, and the Q-factor with respect to the ac (high-frequency) component is low (below 10), so that the potential fluctuation between the pads is absorbed. Thus the electromagnetic radiation from the LSI device itself and wires connected to the LSI device is remarkably suppressed.

Description

Specification

Low E M I device circuit and structure

The present invention relates to an EMC-compatible slave device, which is increasingly important as the speed and density of ICs and LSI elements and circuits increase, and particularly relates to a device, a circuit board, and a device that require a means for suppressing unnecessary radiation noise. Related to electronic devices. Background art

A bypass capacitor with good frequency characteristics is inserted between the power supply terminal (pad) and ground terminal (pad) of LSI devices, etc., which are usually sources of noise, in order to suppress unnecessary radiation. Have been. When connecting a capacitor outside the LSI, even if the capacitance of the bypass capacitor is sufficiently large, the current loop from the semiconductor chip to the package lead is large, so that unnecessary width radiation is large, and one measure is taken. There is a limit. On the other hand, Japanese Patent Application Laid-Open No. 5-265757 discloses a method in which a bypass capacitor is built in an LSI to reduce the length (current length) of a current loop. However, since the potential fluctuation occurs between the source pad and the ground pad due to the resonance current flowing in the current loop, the radiation from the wiring connected to the pad cannot be removed. There is a need for a means to suppress and absorb phase shifts. The wood invention converts the range variation (AC component) of the power supply pad with respect to the ground pad at the time of switching of an LSI element or the like into joule heat without using EMI countermeasure parts, and provides The goal is to provide a low EMI device that effectively suppresses unnecessary radiation while realizing the same. Disclosure of the invention

The present invention realizes high-density mounting by lowering the Q value of a bypass capacitor by equivalently connecting a bypass capacitor formed on the active surface of an LSI device (element) and a resistor in parallel. Heat fluctuation and absorption of potential fluctuations generated between the power supply pad and ground pad are suppressed by suppressing unnecessary radiation.

On the metaphor of the LSI device, a circuit in which a second bypass capacitor C 2 and a resistor R are connected in series is connected in parallel to the first bypass capacitor C 1 connected to the power supply pad and the ground pad. As a result, with respect to the Q of the circuit from the viewpoint of the power supply pad and the ground pad, a low Q (a value of 10 or less) for the AC component as well as the DC component cut is obtained. .

A circuit in which the second bypass capacitor C 2 and the resistor R are connected in series is connected to the impedance of the second bypass capacitor IZ c 2 | for a required frequency range (ω \ ≤ ω ≤ ω 2). (= 1 Ζ ω C 2) is made sufficiently smaller than the resistor R and equivalently given by the resistor R. At this time, from the question of the power supply pad and the ground pad, the Q of the | ΰ] path is the Q (of the equivalent circuit in which the bypass capacitor C 1 of 笫 1 and the resistor R are connected in parallel. = ω C 1 R). At this time, the DC bias component is cut in a circuit, and a low Q is achieved for the AC component (high-frequency component). By setting the Q of the circuit to 10 or less, potential fluctuations (AC components) generated between the power supply pad and the ground pad can be effectively absorbed.

On the other hand, in the case of a single bypass capacitor using a material with a large tan (δ) for induction, or when a bypass capacitor and a resistor are directly connected in parallel in a circuit, Problems such as leak current occur. The present invention solves this i !! J problem by using two bypass capacitors C2. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a cross-sectional view of a low-EMI device in which a circuit is formed on the surface of an LSI device (chip), which is an example of the present invention. FIG. 2 shows a plan view of the low EMI device of FIG. 1 as viewed from above the active surface. Figure 3 shows the circuit model diagram formed on the surface of the LSI device (chip). FIG. 4 shows a circuit model diagram in a case where constraints are provided in the circuit model of FIG. Fig. 5 is an example of Kimei, and shows a process chart of the manufacturing process of a low EML device, and (a) and (b) show a cross-sectional view and a plan view in each step, respectively. FIG. 6 shows another embodiment of the wood invention, and shows a manufacturing process diagram of a low EMI device, wherein (a) and (b) show a cross-sectional view and a plan view in each step, respectively.

FIG. 7 shows another embodiment of the present invention and shows a process chart of a manufacturing process of a low EMI device, and (a) and (b) show a cross-sectional view and a plan view in each step, respectively.

FIG. 8 shows another embodiment of the present invention and shows a process chart of a manufacturing process of a low EML device, and (a) and (b) show a cross-sectional view and a plan view in each step, respectively. .

FIG. 9 shows another embodiment of the present invention, showing a process diagram of the manufacturing process of a low-EMl device, wherein (a) and (b) are cross-sectional views in each step, and FIG. Figure is shown.

FIG. 10 shows another embodiment of the wood invention, showing a process chart of a manufacturing process of a low EMI device, wherein (a) and (b) show a sectional view and a plan view in each step, respectively.

FIGS. 11A and 11B show another example of the present invention, in which the manufacturing process of a low EML device is shown in the form of a cross-sectional view and a plan view, respectively. The figure is shown. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described.

FIG. 1 is an embodiment of the present invention, and shows a cross-sectional view of a low EMI device 1 in which a circuit is formed on a surface of an LSI device (chip) by a bypass capacitor and a resistor. FIG. 2 is a plan view of the low EMI device 1 shown in FIG. 1 as viewed from above.

In FIG. 1, the outermost surface of the LSI chip 2 is covered with a silicon oxide passivation film, and a ground pad 11 for connection to an external circuit and a power pad 12 ( (Not shown), and electrode terminals such as signal pad 13 (not shown). In the low EMI device 1, the first insulating film 3, the first conductive film 4, the first dielectric film 5, the resistance film 6, and the like are formed on the surface of the LSI chip 2 on which the electrode terminals are formed. It has a circuit structure in which a rest film 7 of Π2, a dielectric film 8 of ΙΠ2, a third rest film 9, and a second insulation 010 are formed. In particular, by forming a circuit inside the electrode terminal, the external shape and area of the LSI chip 2 are not affected.

The first bypass capacitor C 1 is formed by sandwiching the first dielectric film 5 between the first conductive film 4 and the second conductive film 7, and the second bypass capacitor C 2 is formed by 笫 2 The dielectric crotch 8 is formed so as to be sandwiched between the 52 body film 7 and the third conductor film 9. The resistance R is formed by sandwiching the resistance rest film 6 between the first conductor film 4 and the third conductor film 9.

As shown in FIG. 2, the lead pattern of the ^ 5 1 conductive film 4 and the second conductive film 7

— Grounds 14 and 15 are ground chips of LSI chip 2, respectively. The pads 11 and the power supply pad 12 are taken out at the shortest distance and are connected at multiple locations. The current loop length, area, And the inductance component is greatly reduced to suppress potential fluctuations due to resonance and the like.

FIG. 3 shows a model of a circuit formed on the surface of the SI chip 2. Viewed from Grad down Dopa' de 1 1 and power pad 1 2 LSI chip 2, the second of the bus capacitor C 2 1 8 to the first bus ⁰ scan capacitor C 1 1 7 and resistor R 1 9 series Are connected in parallel. FIG. 4 shows a circuit model in a case where constraints are provided on the circuit model of FIG. In FIG. 3, the impedance of the bypass capacitor C 2 18 of 笫 2, IZ c2 I (= 1 Ζ ω C 2), is made sufficiently smaller than the resistor R 19, and the first bypass capacitor C 2 It is given by the parallel connection of 1 17 and the resistor R 19. In this circuit, the DC component cut by the second bypass capacitor C218 and the low Q (= ωC1R) for the AC component are obtained. 5 to 11 show the manufacturing process steps of the low-profile I-device 1. FIG. (A) and (b) in the figure show a sectional view and a plan view, respectively.

FIG. 5 shows a top view of the first insulating film 3 formed on the LSI chip 2. A 1-m-thick silicon oxide film is formed by CVD on the entire surface of the LSI chip 2 as a passive junction. Next, a photo process and a dry etching method are performed; 1J, and an insulating film 3 of 笫 1 is formed in a region excluding an electrode pad such as a ground pad 11 of the LSI chip 2. In order to absorb and mitigate the effect of the β on the LSI active surface formed on the LS 1 chip 2. In some cases, the sessionion film has a multilayer structure. FIG. 6 shows a process chart of the first conductive film 4 formed after the first insulating crotch 3. After the formation of the first insulation layer 3, a 500 nm thick platinum thin layer is formed on the entire surface of the LSI chip 2 as an electrode layer of the first bypass capacitor C117 by using a sputtering method. The lead pattern is connected to the ground pad 11 by a photo process and reactive dry etching. 14 and the first passivation film 4 consisting of a portion on the central passivation film of the LSI chip 2 is removed.

FIG. 7 shows a process chart of the resistor film 6 formed after the first insulating film 4. 1) (After the formation of fl 4, a cermet resistance material of chromium and silicon oxide was used, and the entire surface of the LSI chip 2 was formed to a thickness of 900 nm by a sputtering method as a resistance film. The resist film is applied to the rectangular shape along the four sides of the LSI chip 2 by a photo process and a jet etching method to form the resistive film 6. The shape of the resistive film 6 is rectangular. The shape is not limited, but the symmetrical shape is adopted to make the TS characteristics of the bypass capacitor, as viewed from the adjacent ground pad 1〗 and power supply pad 12, equal.

FIG. 8 shows a process chart of the first dielectric film 5 formed after the resistor film 6.

After the formation of the resistive film 6, a 200 nm thick tantalum oxide layer is formed on the entire surface of the LSI chip 2 by sputtering. Then, a resist rest film 6 and a dielectric rest film 5 of 1 are formed on the conductor film 4 of FIG. 1 except for a region of the ground pad 11 by a photo process and a wet etching method. In this case, on the four sides adjacent to the electrode pads such as the ground pad 11 of the LSI chip 2, the induction rest 5 of 笫 1 is formed so as to cover the conductor film 4 of 11. The length of the first invitation 5 is set in consideration of the withstand voltage and the capacitance value. The 50 nm process may be repeated 2 to 4 times. As a dielectric material, there is a method of increasing the specific dielectric constant by using barrier titanate BaTi03 or strontium titanate SrTi3. As a process, spin coating is used instead of sputtering in consideration of composition control and characteristic reproduction.

FIG. 9 shows a process diagram of the second guide rest 7 formed after the introductory rest 5 of ^ 1. After the first dielectric break 5 is formed, a 500 nm thick I gold layer is formed by sputtering over the entire surface of the LSI chip 2. This is a photo pro A second conductor crotch 7 is formed on the first dielectric film 5 as an electrode layer of the first bypass capacitor C 117 and the second bypass capacitor C 218 by recess and dry etching. . In this case, the second conductor film 7 has a lead pad 15 for connecting to the power supply pad 12. When there are a plurality of types of power supplies, the first bypass capacitor C 117 is divided into plural parts and formed in consideration of the arrangement condition of the power supply pad 12. The first conductive film 4 is used as a common ground electrode, and the second conductive film 7 forms a plurality of power electrodes.

FIG. 10 shows a process chart of the second dielectric film 8 formed after the second conductive film 7. After the formation of the second conductor crotch 7, a 200-nm-thick oxide thin film is formed on the entire surface of the LSI chip 2 by using a sputtering method. In some cases, the 5 O nm process is repeated 2 to 4 times as a growth process. Then, a part of the resistive film 6 and the upper surface of the electrode pad such as the ground pad 11 of the LSI chip 2 are removed by a photo-etching and a jet etching method. Further, the second dielectric film 8 is formed so as to form a break 4 of ^ 1 and a conduction break 7 of ^ 2. 1¾ opening 1 6 of the second dielectric Kyu胶8 provided而上resistor Kyuko 6 as _c dielectric rest material in one of the means for controlling the value of the resistor R 1 9 by its shape, In order to increase the specific induction rate, there is a case where a titanium titanate BaTi3 or strontium titanate SrTi03 is supplied.

Fig. 1 1 FIG. 9 shows a process chart of the third conductive film 9 formed after the second insulating film 8. After the formation of the second dielectric layer 8, a 500 nm thick gold thin film is formed on the entire surface of the LS1 chip 2 by using a sputtering method. This is converted into a second bypass capacitor C218 and a resistor R19 by a photo process and a dry etching method. ί52 Formed on the dielectric insulating film 8 of 2 and the resistor removal 6. In this case, on the four sides adjacent to the electrode pads such as the ground pad 11 of the LSI chip 2, the 3 rest 9 of the 3 It is formed so as not to protrude outside.

Finally, as shown in FIG. 1, after forming the third conductor film 9, a second insulating film 10 as a passivation film is formed. A 1-m-thick silicon oxide film is formed on the entire surface of the LSI chip 2 using the CVD method. This is formed in a region excluding the electrode pad such as the ground pad 11 of the LSI chip 2 by a photo process and a dry etching method. In some cases, the passivation film has two layers to improve moisture resistance. Industrial applicability

According to the present invention, on the surface of an LSI device, a circuit in which a second bypass capacitor C2 and a resistor R are connected in series is connected in parallel to a first bypass capacitor C1 connected to a power supply pad and a ground pad. To make the impedance of the second bypass capacitor C 2 sufficiently small with respect to the resistance R. As a result, the DC component of the bypass capacitor circuit viewed from between the power supply pad and the ground pad is not only a DC component but also a low Q with respect to the AC component (high-frequency component). However, it has the effect of absorbing potential fluctuations generated between the pads and greatly suppressing electromagnetic radiation from the LSI device itself and the wiring connected to it.

Claims

The scope of the claims

1. A low EMI device circuit formed on the surface of an LSI device, including a first bypass capacitor C1, a second bypass capacitor C2, a resistor R, a power supply pin, and a ground bin. A circuit in which the second bypass capacitor C2 and the resistor R are connected in series is connected in parallel to the first bypass capacitor C1 connected between the power supply pin and the ground bin. And low EMI device circuits.

2. The low EM1 device circuit according to claim 1, wherein the impedance | Zc2 | (= 1 / ωC2) of the second bypass capacitor C2 is made sufficiently smaller than the resistance R. And a low EMI device circuit.

3. In the low EMI device circuit of claim 2, Q (= ω C 1 R) of a circuit in which the first bypass capacitor C 1 and the resistor R are connected in parallel equivalently is set to 10 or less. Low EMI device circuit characterized by this.

4. In the structure formed on the surface of the LSI device, the first conduction layer, the first dielectric layer, the second conduction layer, the resistance rest layer, the second dielectric layer, and the third conduction layer. A body layer, a power pad, and a ground pad, wherein both surfaces of the second conductor layer are covered with the first invitation and the second invitation, and the first invitation The first dielectric layer and the second dielectric layer together with the first dielectric layer and the second dielectric layer; and the first dielectric layer and the second dielectric layer. (3) the insulating layer of E 笫 1 and the second conductive layer are respectively connected to the ground pad and the power supply pad of the LSI device. And low EMI device structure.

5. The low EMI device structure according to claim 4, wherein the first debris and the second deactivation / i are respectively connected to the ground pad and the power supply pad of an iW LSI device. Low EMI devices featuring point-of-contact Structure.

6. The low EMI device structure according to claim 4, wherein the first conductor layer and the second conductor layer are respectively connected to the ground pad and the power supply pad of the LSI device with a shortest distance. Low EMI device structure.